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d9a5d113 MF |
1 | /* |
2 | * U-boot - u-boot.lds.S | |
3 | * | |
a3c08363 | 4 | * Copyright (c) 2005-2010 Analog Device Inc. |
d9a5d113 MF |
5 | * |
6 | * (C) Copyright 2000-2004 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <config.h> | |
29 | #include <asm/blackfin.h> | |
30 | #undef ALIGN | |
31 | #undef ENTRY | |
d9a5d113 | 32 | |
9ff67e5e MF |
33 | #ifndef LDS_BOARD_TEXT |
34 | # define LDS_BOARD_TEXT | |
35 | #endif | |
36 | ||
d9a5d113 MF |
37 | /* If we don't actually load anything into L1 data, this will avoid |
38 | * a syntax error. If we do actually load something into L1 data, | |
39 | * we'll get a linker memory load error (which is what we'd want). | |
40 | * This is here in the first place so we can quickly test building | |
41 | * for different CPU's which may lack non-cache L1 data. | |
42 | */ | |
43 | #ifndef L1_DATA_B_SRAM | |
44 | # define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE | |
45 | # define L1_DATA_B_SRAM_SIZE 0 | |
46 | #endif | |
47 | ||
f51e0011 MF |
48 | /* The 0xC offset is so we don't clobber the tiny LDR jump block. */ |
49 | #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1 | |
50 | # define L1_CODE_ORIGIN L1_INST_SRAM | |
51 | #else | |
52 | # define L1_CODE_ORIGIN L1_INST_SRAM + 0xC | |
53 | #endif | |
54 | ||
d9a5d113 MF |
55 | OUTPUT_ARCH(bfin) |
56 | ||
57 | MEMORY | |
58 | { | |
7527feef | 59 | #if CONFIG_MEM_SIZE |
d9a5d113 | 60 | ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
7527feef MF |
61 | # define ram_code ram |
62 | # define ram_data ram | |
63 | #else | |
64 | # define ram_code l1_code | |
65 | # define ram_data l1_data | |
66 | #endif | |
f51e0011 | 67 | l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE |
d9a5d113 MF |
68 | l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
69 | } | |
70 | ||
71 | ENTRY(_start) | |
72 | SECTIONS | |
73 | { | |
b1e2c551 | 74 | .text.pre : |
d9a5d113 MF |
75 | { |
76 | cpu/blackfin/start.o (.text .text.*) | |
9ff67e5e MF |
77 | |
78 | LDS_BOARD_TEXT | |
b1e2c551 | 79 | } >ram_code |
9ff67e5e | 80 | |
b1e2c551 MF |
81 | .text.init : |
82 | { | |
d9a5d113 | 83 | cpu/blackfin/initcode.o (.text .text.*) |
b1e2c551 MF |
84 | } >ram_code |
85 | __initcode_lma = LOADADDR(.text.init); | |
86 | __initcode_len = SIZEOF(.text.init); | |
9ff67e5e | 87 | |
b1e2c551 MF |
88 | .text : |
89 | { | |
d9a5d113 | 90 | *(.text .text.*) |
7527feef | 91 | } >ram_code |
d9a5d113 MF |
92 | |
93 | .rodata : | |
94 | { | |
95 | . = ALIGN(4); | |
ed912d4d | 96 | *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
d9a5d113 | 97 | . = ALIGN(4); |
7527feef | 98 | } >ram_data |
d9a5d113 MF |
99 | |
100 | .data : | |
101 | { | |
38b9b744 | 102 | . = ALIGN(4); |
d9a5d113 MF |
103 | *(.data .data.*) |
104 | *(.data1) | |
105 | *(.sdata) | |
106 | *(.sdata2) | |
107 | *(.dynamic) | |
108 | CONSTRUCTORS | |
7527feef | 109 | } >ram_data |
d9a5d113 MF |
110 | |
111 | .u_boot_cmd : | |
112 | { | |
113 | ___u_boot_cmd_start = .; | |
114 | *(.u_boot_cmd) | |
115 | ___u_boot_cmd_end = .; | |
7527feef | 116 | } >ram_data |
d9a5d113 MF |
117 | |
118 | .text_l1 : | |
119 | { | |
120 | . = ALIGN(4); | |
121 | __stext_l1 = .; | |
122 | *(.l1.text) | |
123 | . = ALIGN(4); | |
124 | __etext_l1 = .; | |
7527feef | 125 | } >l1_code AT>ram_code |
b1e2c551 MF |
126 | __text_l1_lma = LOADADDR(.text_l1); |
127 | __text_l1_len = SIZEOF(.text_l1); | |
128 | ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!") | |
d9a5d113 MF |
129 | |
130 | .data_l1 : | |
131 | { | |
132 | . = ALIGN(4); | |
133 | __sdata_l1 = .; | |
134 | *(.l1.data) | |
135 | *(.l1.bss) | |
136 | . = ALIGN(4); | |
137 | __edata_l1 = .; | |
7527feef | 138 | } >l1_data AT>ram_data |
b1e2c551 MF |
139 | __data_l1_lma = LOADADDR(.data_l1); |
140 | __data_l1_len = SIZEOF(.data_l1); | |
141 | ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data B overflow!") | |
d9a5d113 MF |
142 | |
143 | .bss : | |
144 | { | |
145 | . = ALIGN(4); | |
d9a5d113 MF |
146 | *(.sbss) *(.scommon) |
147 | *(.dynbss) | |
148 | *(.bss .bss.*) | |
149 | *(COMMON) | |
7527feef | 150 | } >ram_data |
b1e2c551 MF |
151 | __bss_vma = ADDR(.bss); |
152 | __bss_len = SIZEOF(.bss); | |
d9a5d113 | 153 | } |