[people/ms/u-boot.git] / arch / m68k / cpu / mcf523x / cpu_init.c

/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/io.h>

#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#endif

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
	wdog_t *wdog = (wdog_t *) MMAP_WDOG;
	scm_t *scm = (scm_t *) MMAP_SCM;

	/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
	out_be16(&wdog->cr, 0);
#endif

	out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);

	/* Port configuration */
	out_8(&gpio->par_cs, 0);

#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
#endif

#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
#endif

#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
#endif

#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
#endif

#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
#endif

#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif

#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
#endif

#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
#endif

#ifdef CONFIG_SYS_I2C_FSL
	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
	CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
#endif

	icache_enable();
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
	return (0);
}

void uart_port_conf(int port)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
		break;
	case 1:
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1RXD_MASK | GPIO_PAR_UART_U1TXD_MASK);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
		break;
	case 2:
#ifdef CONFIG_SYS_UART2_PRI_GPIO
		clrbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
		setbits_be16(&gpio->par_uart,
			GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_U2TXD | GPIO_PAR_FECI2C_EMDIO_U2RXD);
#endif
		break;
	}
}

#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
	gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	if (setclear) {
		setbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_FECEMDC |
			GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
	} else {
		clrbits_8(&gpio->par_feci2c,
			GPIO_PAR_FECI2C_EMDC_MASK |
			GPIO_PAR_FECI2C_EMDIO_MASK);
	}

	return 0;
}
#endif
Commit	Line	Data
4a442d31 TL	1	/*
	2	*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
c6d88630	6	* (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
4a442d31 TL	7	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <watchdog.h>
4a442d31	30	#include <asm/immap.h>
c6d88630	31	#include <asm/io.h>
4a442d31	32
f3962d3f TL	33	#if defined(CONFIG_CMD_NET)
	34	#include <config.h>
	35	#include <net.h>
	36	#include <asm/fec.h>
	37	#endif
	38
4a442d31 TL	39	/*
	40	* Breath some life into the CPU...
	41	*
	42	* Set up the memory map,
	43	* initialize a bunch of registers,
	44	* initialize the UPM's
	45	*/
	46	void cpu_init_f(void)
	47	{
c6d88630 AW	48	gpio_t gpio = (gpio_t ) MMAP_GPIO;
	49	fbcs_t fbcs = (fbcs_t ) MMAP_FBCS;
	50	wdog_t wdog = (wdog_t ) MMAP_WDOG;
	51	scm_t scm = (scm_t ) MMAP_SCM;
4a442d31 TL	52
	53	/* watchdog is enabled by default - disable the watchdog */
	54	#ifndef CONFIG_WATCHDOG
c6d88630	55	out_be16(&wdog->cr, 0);
4a442d31 TL	56	#endif
4a442d31 TL	57
c6d88630	58	out_be32(&scm->rambar, CONFIG_SYS_INIT_RAM_ADDR \| SCM_RAMBAR_BDE);
4a442d31 TL	59
4a442d31 TL	60	/* Port configuration */
c6d88630	61	out_8(&gpio->par_cs, 0);
4a442d31	62
6d0f6bcf	63	#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
c6d88630 AW	64	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
	65	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
	66	out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
4a442d31 TL	67	#endif
4a442d31 TL	68
6d0f6bcf	69	#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
c6d88630 AW	70	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
	71	out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
	72	out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
	73	out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
4a442d31 TL	74	#endif
4a442d31 TL	75
6d0f6bcf	76	#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
c6d88630 AW	77	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
	78	out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
	79	out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
	80	out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
4a442d31 TL	81	#endif
4a442d31 TL	82
6d0f6bcf	83	#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
c6d88630 AW	84	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
	85	out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
	86	out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
	87	out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
4a442d31 TL	88	#endif
4a442d31 TL	89
6d0f6bcf	90	#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
c6d88630 AW	91	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
	92	out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
	93	out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
	94	out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
4a442d31 TL	95	#endif
4a442d31 TL	96
6d0f6bcf	97	#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
c6d88630 AW	98	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
	99	out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
	100	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
	101	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
4a442d31 TL	102	#endif
4a442d31 TL	103
6d0f6bcf	104	#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
c6d88630 AW	105	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
	106	out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
	107	out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
	108	out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
4a442d31 TL	109	#endif
4a442d31 TL	110
6d0f6bcf	111	#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
c6d88630 AW	112	setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
	113	out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
	114	out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
	115	out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
4a442d31 TL	116	#endif
4a442d31 TL	117
00f792e0	118	#ifdef CONFIG_SYS_I2C_FSL
6d0f6bcf JCPV	119	CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
6d0f6bcf JCPV	120	CONFIG_SYS_I2C_PINMUX_REG \|= CONFIG_SYS_I2C_PINMUX_SET;
4a442d31 TL	121	#endif
	122
	123	icache_enable();
	124	}
	125
	126	/*
	127	* initialize higher level parts of CPU like timers
	128	*/
	129	int cpu_init_r(void)
	130	{
	131	return (0);
	132	}
	133
52affe04	134	void uart_port_conf(int port)
4a442d31	135	{
c6d88630	136	gpio_t gpio = (gpio_t ) MMAP_GPIO;
8280f6a1 SR	137
8280f6a1 SR	138	/* Setup Ports: */
52affe04	139	switch (port) {
8280f6a1	140	case 0:
c6d88630 AW	141	clrbits_be16(&gpio->par_uart,
	142	GPIO_PAR_UART_U0RXD \| GPIO_PAR_UART_U0TXD);
	143	setbits_be16(&gpio->par_uart,
	144	GPIO_PAR_UART_U0RXD \| GPIO_PAR_UART_U0TXD);
8280f6a1 SR	145	break;
8280f6a1 SR	146	case 1:
c6d88630 AW	147	clrbits_be16(&gpio->par_uart,
	148	GPIO_PAR_UART_U1RXD_MASK \| GPIO_PAR_UART_U1TXD_MASK);
	149	setbits_be16(&gpio->par_uart,
	150	GPIO_PAR_UART_U1RXD_U1RXD \| GPIO_PAR_UART_U1TXD_U1TXD);
8280f6a1 SR	151	break;
8280f6a1 SR	152	case 2:
52affe04	153	#ifdef CONFIG_SYS_UART2_PRI_GPIO
c6d88630 AW	154	clrbits_be16(&gpio->par_uart,
	155	GPIO_PAR_UART_U2RXD \| GPIO_PAR_UART_U2TXD);
	156	setbits_be16(&gpio->par_uart,
	157	GPIO_PAR_UART_U2RXD \| GPIO_PAR_UART_U2TXD);
52affe04	158	#elif defined(CONFIG_SYS_UART2_ALT1_GPIO)
c6d88630 AW	159	clrbits_8(&gpio->par_feci2c,
	160	GPIO_PAR_FECI2C_EMDC_MASK \| GPIO_PAR_FECI2C_EMDIO_MASK);
	161	setbits_8(&gpio->par_feci2c,
	162	GPIO_PAR_FECI2C_EMDC_U2TXD \| GPIO_PAR_FECI2C_EMDIO_U2RXD);
52affe04	163	#endif
8280f6a1 SR	164	break;
8280f6a1 SR	165	}
4a442d31	166	}
f3962d3f TL	167
	168	#if defined(CONFIG_CMD_NET)
	169	int fecpin_setclear(struct eth_device *dev, int setclear)
	170	{
c6d88630	171	gpio_t gpio = (gpio_t ) MMAP_GPIO;
f3962d3f TL	172
f3962d3f TL	173	if (setclear) {
c6d88630 AW	174	setbits_8(&gpio->par_feci2c,
	175	GPIO_PAR_FECI2C_EMDC_FECEMDC \|
	176	GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
f3962d3f	177	} else {
c6d88630 AW	178	clrbits_8(&gpio->par_feci2c,
	179	GPIO_PAR_FECI2C_EMDC_MASK \|
	180	GPIO_PAR_FECI2C_EMDIO_MASK);
f3962d3f TL	181	}
	182
	183	return 0;
	184	}
	185	#endif