]> git.ipfire.org Git - people/ms/u-boot.git/blame - arch/m68k/cpu/mcf52x2/cpu_init.c
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i2c, fsl_i2c: switch to new multibus/multiadapter support
[people/ms/u-boot.git] / arch / m68k / cpu / mcf52x2 / cpu_init.c
CommitLineData
bf9e3b38
WD		 1/*
2 * (C) Copyright 2003
3 * Josef Baumgartner <josef.baumgartner@telex.de>
4 *
9acb626f
HS		 5 * MCF5282 additionals
6 * (C) Copyright 2005
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
dfc2b769
MD		 8 * (c) Copyright 2010
9 * Arcturus Networks Inc. <www.arcturusnetworks.com>
9acb626f 10 *
32dbaafa 11 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
a1436a84
TL		 12 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
13 * Hayden Fraser (Hayden.Fraser@freescale.com)
14 *
f71d9d91
MF		 15 * MCF5275 additions
16 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
17 *
bf9e3b38
WD		 18 * See file CREDITS for list of people who contributed to this
19 * project.
20 *
21 * This program is free software; you can redistribute it and/or
22 * modify it under the terms of the GNU General Public License as
23 * published by the Free Software Foundation; either version 2 of
24 * the License, or (at your option) any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY; without even the implied warranty of
977b50f8 28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
bf9e3b38
WD		 29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program; if not, write to the Free Software
33 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 * MA 02111-1307 USA
35 */
36
37#include <common.h>
38#include <watchdog.h>
83ec20bc 39#include <asm/immap.h>
32dbaafa 40#include <asm/io.h>
8c725b93 41
f3962d3f
TL		 42#if defined(CONFIG_CMD_NET)
43#include <config.h>
44#include <net.h>
45#include <asm/fec.h>
46#endif
47
012522fe
TL		 48#ifndef CONFIG_M5272
49/* Only 5272 Flexbus chipselect is different from the rest */
50void init_fbcs(void)
51{
32dbaafa 52 fbcs_t *fbcs = (fbcs_t *) (MMAP_FBCS);
012522fe
TL		 53
54#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
55 && defined(CONFIG_SYS_CS0_CTRL))
32dbaafa
AW		 56 out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
57 out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
58 out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
012522fe
TL		 59#else
60#warning "Chip Select 0 are not initialized/used"
61#endif
62#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
63 && defined(CONFIG_SYS_CS1_CTRL))
32dbaafa
AW		 64 out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
65 out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
66 out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
012522fe
TL		 67#endif
68#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
69 && defined(CONFIG_SYS_CS2_CTRL))
32dbaafa
AW		 70 out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
71 out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
72 out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
012522fe
TL		 73#endif
74#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
75 && defined(CONFIG_SYS_CS3_CTRL))
32dbaafa
AW		 76 out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
77 out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
78 out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
012522fe
TL		 79#endif
80#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
81 && defined(CONFIG_SYS_CS4_CTRL))
32dbaafa
AW		 82 out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
83 out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
84 out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
012522fe
TL		 85#endif
86#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
87 && defined(CONFIG_SYS_CS5_CTRL))
32dbaafa
AW		 88 out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
89 out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
90 out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
012522fe
TL		 91#endif
92#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \
93 && defined(CONFIG_SYS_CS6_CTRL))
32dbaafa
AW		 94 out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
95 out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
96 out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
012522fe
TL		 97#endif
98#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \
99 && defined(CONFIG_SYS_CS7_CTRL))
32dbaafa
AW		 100 out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
101 out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
102 out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
012522fe
TL		 103#endif
104}
105#endif
106
bf9a5215
TL		 107#if defined(CONFIG_M5208)
108void cpu_init_f(void)
109{
32dbaafa 110 scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
bf9a5215
TL		 111
112#ifndef CONFIG_WATCHDOG
32dbaafa 113 wdog_t *wdg = (wdog_t *) MMAP_WDOG;
bf9a5215
TL		 114
115 /* Disable the watchdog if we aren't using it */
32dbaafa 116 out_be16(&wdg->cr, 0);
bf9a5215
TL		 117#endif
118
32dbaafa
AW		 119 out_be32(&scm1->mpr, 0x77777777);
120 out_be32(&scm1->pacra, 0);
121 out_be32(&scm1->pacrb, 0);
122 out_be32(&scm1->pacrc, 0);
123 out_be32(&scm1->pacrd, 0);
124 out_be32(&scm1->pacre, 0);
125 out_be32(&scm1->pacrf, 0);
bf9a5215
TL		 126
127 /* FlexBus Chipselect */
128 init_fbcs();
129
130 icache_enable();
131}
132
133/* initialize higher level parts of CPU like timers */
134int cpu_init_r(void)
135{
136 return (0);
137}
138
52affe04 139void uart_port_conf(int port)
bf9a5215 140{
32dbaafa 141 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
bf9a5215
TL		 142
143 /* Setup Ports: */
52affe04 144 switch (port) {
bf9a5215 145 case 0:
32dbaafa
AW		 146 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
147 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U0TXD | GPIO_PAR_UART_U0RXD);
bf9a5215
TL		 148 break;
149 case 1:
32dbaafa
AW		 150 clrbits_be16(&gpio->par_uart, ~GPIO_PAR_UART0_UNMASK);
151 setbits_be16(&gpio->par_uart, GPIO_PAR_UART_U1TXD | GPIO_PAR_UART_U1RXD);
bf9a5215
TL		 152 break;
153 case 2:
154#ifdef CONFIG_SYS_UART2_PRI_GPIO
32dbaafa
AW		 155 clrbits_8(&gpio->par_timer,
156 ~(GPIO_PAR_TMR_TIN0_UNMASK | GPIO_PAR_TMR_TIN1_UNMASK));
157 setbits_8(&gpio->par_timer,
158 GPIO_PAR_TMR_TIN0_U2TXD | GPIO_PAR_TMR_TIN1_U2RXD);
bf9a5215
TL		 159#endif
160#ifdef CONFIG_SYS_UART2_ALT1_GPIO
32dbaafa
AW		 161 clrbits_8(&gpio->par_feci2c,
162 ~(GPIO_PAR_FECI2C_MDC_UNMASK | GPIO_PAR_FECI2C_MDIO_UNMASK));
163 setbits_8(&gpio->par_feci2c,
164 GPIO_PAR_FECI2C_MDC_U2TXD | GPIO_PAR_FECI2C_MDIO_U2RXD);
bf9a5215
TL		 165#endif
166#ifdef CONFIG_SYS_UART2_ALT1_GPIO
32dbaafa
AW		 167 clrbits_8(&gpio->par_feci2c,
168 ~(GPIO_PAR_FECI2C_SDA_UNMASK | GPIO_PAR_FECI2C_SCL_UNMASK));
169 setbits_8(&gpio->par_feci2c,
170 GPIO_PAR_FECI2C_SDA_U2TXD | GPIO_PAR_FECI2C_SCL_U2RXD);
bf9a5215
TL		 171#endif
172 break;
173 }
174}
175
176#if defined(CONFIG_CMD_NET)
177int fecpin_setclear(struct eth_device *dev, int setclear)
178{
32dbaafa 179 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
bf9a5215
TL		 180
181 if (setclear) {
32dbaafa
AW		 182 setbits_8(&gpio->par_fec,
183 GPIO_PAR_FEC_7W_FEC | GPIO_PAR_FEC_MII_FEC);
184 setbits_8(&gpio->par_feci2c,
185 GPIO_PAR_FECI2C_MDC_MDC | GPIO_PAR_FECI2C_MDIO_MDIO);
bf9a5215 186 } else {
32dbaafa
AW		 187 clrbits_8(&gpio->par_fec,
188 ~(GPIO_PAR_FEC_7W_UNMASK & GPIO_PAR_FEC_MII_UNMASK));
189 clrbits_8(&gpio->par_feci2c, ~GPIO_PAR_FECI2C_RMII_UNMASK);
bf9a5215
TL		 190 }
191 return 0;
192}
193#endif /* CONFIG_CMD_NET */
194#endif /* CONFIG_M5208 */
195
a1436a84
TL		 196#if defined(CONFIG_M5253)
197/*
198 * Breath some life into the CPU...
199 *
200 * Set up the memory map,
201 * initialize a bunch of registers,
202 * initialize the UPM's
203 */
204void cpu_init_f(void)
205{
206 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
207 mbar_writeByte(MCFSIM_SYPCR, 0x00);
208 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
209 mbar_writeByte(MCFSIM_SWSR, 0x00);
210 mbar_writeByte(MCFSIM_SWDICR, 0x00);
211 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
212 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
213 mbar_writeByte(MCFSIM_I2CICR, 0x00);
214 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
215 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
216 mbar_writeByte(MCFSIM_ICR6, 0x00);
217 mbar_writeByte(MCFSIM_ICR7, 0x00);
218 mbar_writeByte(MCFSIM_ICR8, 0x00);
219 mbar_writeByte(MCFSIM_ICR9, 0x00);
220 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
221
222 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
223 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
224 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
225
455ae7e8 226 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
a1436a84 227
012522fe
TL		 228 /* FlexBus Chipselect */
229 init_fbcs();
a1436a84 230
00f792e0 231#ifdef CONFIG_SYS_I2C_FSL
012522fe
TL		 232 CONFIG_SYS_I2C_PINMUX_REG =
233 CONFIG_SYS_I2C_PINMUX_REG & CONFIG_SYS_I2C_PINMUX_CLR;
6d0f6bcf
JCPV		 234 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
235#ifdef CONFIG_SYS_I2C2_OFFSET
236 CONFIG_SYS_I2C2_PINMUX_REG &= CONFIG_SYS_I2C2_PINMUX_CLR;
237 CONFIG_SYS_I2C2_PINMUX_REG |= CONFIG_SYS_I2C2_PINMUX_SET;
eec567a6
TL		 238#endif
239#endif
240
a1436a84
TL		 241 /* enable instruction cache now */
242 icache_enable();
243}
244
245/*initialize higher level parts of CPU like timers */
246int cpu_init_r(void)
247{
248 return (0);
249}
250
52affe04 251void uart_port_conf(int port)
a1436a84 252{
32dbaafa 253 u32 *par = (u32 *) MMAP_PAR;
52affe04 254
a1436a84 255 /* Setup Ports: */
52affe04 256 switch (port) {
a1436a84 257 case 1:
32dbaafa
AW		 258 clrbits_be32(par, 0x00180000);
259 setbits_be32(par, 0x00180000);
a1436a84
TL		 260 break;
261 case 2:
32dbaafa
AW		 262 clrbits_be32(par, 0x00000003);
263 clrbits_be32(par, 0xFFFFFFFC);
a1436a84
TL		 264 break;
265 }
266}
267#endif /* #if defined(CONFIG_M5253) */
268
eacbd317 269#if defined(CONFIG_M5271)
83ec20bc 270void cpu_init_f(void)
eacbd317
ZL		 271{
272#ifndef CONFIG_WATCHDOG
273 /* Disable the watchdog if we aren't using it */
274 mbar_writeShort(MCF_WTM_WCR, 0);
275#endif
276
012522fe
TL		 277 /* FlexBus Chipselect */
278 init_fbcs();
279
e0db344f
RR		 280#ifdef CONFIG_SYS_MCF_SYNCR
281 /* Set clockspeed according to board header file */
282 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR);
283#else
eacbd317 284 /* Set clockspeed to 100MHz */
e0db344f 285 mbar_writeLong(MCF_FMPLL_SYNCR,
eacbd317 286 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
e0db344f 287#endif
65f0d121 288 while (!(mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK)) ;
eacbd317
ZL		 289}
290
291/*
292 * initialize higher level parts of CPU like timers
293 */
83ec20bc 294int cpu_init_r(void)
eacbd317
ZL		 295{
296 return (0);
297}
83ec20bc 298
52affe04 299void uart_port_conf(int port)
83ec20bc 300{
52affe04
TL		 301 u16 temp;
302
83ec20bc 303 /* Setup Ports: */
52affe04 304 switch (port) {
83ec20bc 305 case 0:
52affe04
TL		 306 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xFFF3;
307 temp |= (MCF_GPIO_PAR_UART_U0TXD | MCF_GPIO_PAR_UART_U0RXD);
308 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
83ec20bc
TL		 309 break;
310 case 1:
52affe04
TL		 311 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xF0FF;
312 temp |= (MCF_GPIO_PAR_UART_U1RXD_UART1 | MCF_GPIO_PAR_UART_U1TXD_UART1);
313 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
83ec20bc
TL		 314 break;
315 case 2:
52affe04
TL		 316 temp = mbar_readShort(MCF_GPIO_PAR_UART) & 0xCFFF;
317 temp |= (0x3000);
318 mbar_writeShort(MCF_GPIO_PAR_UART, temp);
83ec20bc
TL		 319 break;
320 }
321}
f3962d3f
TL		 322
323#if defined(CONFIG_CMD_NET)
324int fecpin_setclear(struct eth_device *dev, int setclear)
325{
326 if (setclear) {
327 /* Enable Ethernet pins */
d1ef25dd
RR		 328 mbar_writeByte(MCF_GPIO_PAR_FECI2C,
329 (mbar_readByte(MCF_GPIO_PAR_FECI2C) | 0xF0));
f3962d3f
TL		 330 } else {
331 }
332
333 return 0;
334}
335#endif /* CONFIG_CMD_NET */
59d06122
RR		 336
337#if defined(CONFIG_CF_QSPI)
338
339/* Configure PIOs for SIN, SOUT, and SCK */
340void cfspi_port_conf(void)
341{
342 mbar_writeByte(MCF_GPIO_PAR_QSPI,
343 MCF_GPIO_PAR_QSPI_SIN_SIN |
344 MCF_GPIO_PAR_QSPI_SOUT_SOUT |
345 MCF_GPIO_PAR_QSPI_SCK_SCK);
346}
347#endif /* CONFIG_CF_QSPI */
348
349#endif /* CONFIG_M5271 */
eacbd317 350
8c725b93 351#if defined(CONFIG_M5272)
bf9e3b38
WD		 352/*
353 * Breath some life into the CPU...
354 *
355 * Set up the memory map,
356 * initialize a bunch of registers,
357 * initialize the UPM's
358 */
83ec20bc 359void cpu_init_f(void)
bf9e3b38
WD		 360{
361 /* if we come from RAM we assume the CPU is
362 * already initialized.
363 */
364#ifndef CONFIG_MONITOR_IS_IN_RAM
32dbaafa
AW		 365 sysctrl_t *sysctrl = (sysctrl_t *) (CONFIG_SYS_MBAR);
366 gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
367 csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
bf9e3b38 368
32dbaafa
AW		 369 out_be16(&sysctrl->sc_scr, CONFIG_SYS_SCR);
370 out_be16(&sysctrl->sc_spr, CONFIG_SYS_SPR);
bf9e3b38 371
977b50f8 372 /* Setup Ports: */
32dbaafa
AW		 373 out_be32(&gpio->gpio_pacnt, CONFIG_SYS_PACNT);
374 out_be16(&gpio->gpio_paddr, CONFIG_SYS_PADDR);
375 out_be16(&gpio->gpio_padat, CONFIG_SYS_PADAT);
376 out_be32(&gpio->gpio_pbcnt, CONFIG_SYS_PBCNT);
377 out_be16(&gpio->gpio_pbddr, CONFIG_SYS_PBDDR);
378 out_be16(&gpio->gpio_pbdat, CONFIG_SYS_PBDAT);
379 out_be32(&gpio->gpio_pdcnt, CONFIG_SYS_PDCNT);
bf9e3b38
WD		 380
381 /* Memory Controller: */
32dbaafa
AW		 382 out_be32(&csctrl->cs_br0, CONFIG_SYS_BR0_PRELIM);
383 out_be32(&csctrl->cs_or0, CONFIG_SYS_OR0_PRELIM);
bf9e3b38 384
6d0f6bcf 385#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
32dbaafa
AW		 386 out_be32(&csctrl->cs_br1, CONFIG_SYS_BR1_PRELIM);
387 out_be32(&csctrl->cs_or1, CONFIG_SYS_OR1_PRELIM);
bf9e3b38
WD		 388#endif
389
6d0f6bcf 390#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
32dbaafa
AW		 391 out_be32(&csctrl->cs_br2, CONFIG_SYS_BR2_PRELIM);
392 out_be32(&csctrl->cs_or2, CONFIG_SYS_OR2_PRELIM);
bf9e3b38
WD		 393#endif
394
6d0f6bcf 395#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
32dbaafa
AW		 396 out_be32(&csctrl->cs_br3, CONFIG_SYS_BR3_PRELIM);
397 out_be32(&csctrl->cs_or3, CONFIG_SYS_OR3_PRELIM);
bf9e3b38
WD		 398#endif
399
6d0f6bcf 400#if defined(CONFIG_SYS_OR4_PRELIM) && defined(CONFIG_SYS_BR4_PRELIM)
32dbaafa
AW		 401 out_be32(&csctrl->cs_br4, CONFIG_SYS_BR4_PRELIM);
402 out_be32(&csctrl->cs_or4, CONFIG_SYS_OR4_PRELIM);
bf9e3b38
WD		 403#endif
404
6d0f6bcf 405#if defined(CONFIG_SYS_OR5_PRELIM) && defined(CONFIG_SYS_BR5_PRELIM)
32dbaafa
AW		 406 out_be32(&csctrl->cs_br5, CONFIG_SYS_BR5_PRELIM);
407 out_be32(&csctrl->cs_or5, CONFIG_SYS_OR5_PRELIM);
bf9e3b38
WD		 408#endif
409
6d0f6bcf 410#if defined(CONFIG_SYS_OR6_PRELIM) && defined(CONFIG_SYS_BR6_PRELIM)
32dbaafa
AW		 411 out_be32(&csctrl->cs_br6, CONFIG_SYS_BR6_PRELIM);
412 out_be32(&csctrl->cs_or6, CONFIG_SYS_OR6_PRELIM);
bf9e3b38
WD		 413#endif
414
6d0f6bcf 415#if defined(CONFIG_SYS_OR7_PRELIM) && defined(CONFIG_SYS_BR7_PRELIM)
32dbaafa
AW		 416 out_be32(&csctrl->cs_br7, CONFIG_SYS_BR7_PRELIM);
417 out_be32(&csctrl->cs_or7, CONFIG_SYS_OR7_PRELIM);
bf9e3b38
WD		 418#endif
419
83ec20bc 420#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
bf9e3b38 421
977b50f8
WD		 422 /* enable instruction cache now */
423 icache_enable();
bf9e3b38
WD		 424
425}
426
427/*
428 * initialize higher level parts of CPU like timers
429 */
83ec20bc 430int cpu_init_r(void)
bf9e3b38
WD		 431{
432 return (0);
433}
bf9e3b38 434
52affe04 435void uart_port_conf(int port)
83ec20bc 436{
32dbaafa 437 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
83ec20bc
TL		 438
439 /* Setup Ports: */
52affe04 440 switch (port) {
83ec20bc 441 case 0:
32dbaafa
AW		 442 clrbits_be32(&gpio->gpio_pbcnt,
443 GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
444 setbits_be32(&gpio->gpio_pbcnt,
445 GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
83ec20bc
TL		 446 break;
447 case 1:
32dbaafa
AW		 448 clrbits_be32(&gpio->gpio_pdcnt,
449 GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
450 setbits_be32(&gpio->gpio_pdcnt,
451 GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
83ec20bc
TL		 452 break;
453 }
454}
f3962d3f
TL		 455
456#if defined(CONFIG_CMD_NET)
457int fecpin_setclear(struct eth_device *dev, int setclear)
458{
32dbaafa 459 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
f3962d3f
TL		 460
461 if (setclear) {
32dbaafa
AW		 462 setbits_be32(&gpio->gpio_pbcnt,
463 GPIO_PBCNT_E_MDC | GPIO_PBCNT_E_RXER |
464 GPIO_PBCNT_E_RXD1 | GPIO_PBCNT_E_RXD2 |
465 GPIO_PBCNT_E_RXD3 | GPIO_PBCNT_E_TXD1 |
466 GPIO_PBCNT_E_TXD2 | GPIO_PBCNT_E_TXD3);
f3962d3f
TL		 467 } else {
468 }
469 return 0;
470}
471#endif /* CONFIG_CMD_NET */
83ec20bc 472#endif /* #if defined(CONFIG_M5272) */
bf9e3b38 473
f71d9d91
MF		 474#if defined(CONFIG_M5275)
475
476/*
477 * Breathe some life into the CPU...
478 *
479 * Set up the memory map,
480 * initialize a bunch of registers,
481 * initialize the UPM's
482 */
483void cpu_init_f(void)
484{
012522fe
TL		 485 /*
486 * if we come from RAM we assume the CPU is
f71d9d91
MF		 487 * already initialized.
488 */
489
490#ifndef CONFIG_MONITOR_IS_IN_RAM
32dbaafa
AW		 491 wdog_t *wdog_reg = (wdog_t *) (MMAP_WDOG);
492 gpio_t *gpio_reg = (gpio_t *) (MMAP_GPIO);
f71d9d91
MF		 493
494 /* Kill watchdog so we can initialize the PLL */
32dbaafa 495 out_be16(&wdog_reg->wcr, 0);
f71d9d91 496
012522fe
TL		 497 /* FlexBus Chipselect */
498 init_fbcs();
f71d9d91
MF		 499#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
500
00f792e0 501#ifdef CONFIG_SYS_I2C_FSL
6d0f6bcf
JCPV		 502 CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
503 CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
f71d9d91
MF		 504#endif
505
506 /* enable instruction cache now */
507 icache_enable();
508}
509
510/*
511 * initialize higher level parts of CPU like timers
512 */
513int cpu_init_r(void)
514{
515 return (0);
516}
517
52affe04 518void uart_port_conf(int port)
f71d9d91 519{
32dbaafa 520 gpio_t *gpio = (gpio_t *) MMAP_GPIO;
f71d9d91
MF		 521
522 /* Setup Ports: */
52affe04 523 switch (port) {
f71d9d91 524 case 0:
32dbaafa
AW		 525 clrbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
526 setbits_be16(&gpio->par_uart, UART0_ENABLE_MASK);
f71d9d91
MF		 527 break;
528 case 1:
32dbaafa
AW		 529 clrbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
530 setbits_be16(&gpio->par_uart, UART1_ENABLE_MASK);
f71d9d91
MF		 531 break;
532 case 2:
32dbaafa
AW		 533 clrbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
534 setbits_be16(&gpio->par_uart, UART2_ENABLE_MASK);
f71d9d91
MF		 535 break;
536 }
537}
f3962d3f
TL		 538
539#if defined(CONFIG_CMD_NET)
540int fecpin_setclear(struct eth_device *dev, int setclear)
541{
542 struct fec_info_s *info = (struct fec_info_s *) dev->priv;
32dbaafa 543 gpio_t *gpio = (gpio_t *)MMAP_GPIO;
f3962d3f
TL		 544
545 if (setclear) {
546 /* Enable Ethernet pins */
547 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
32dbaafa
AW		 548 setbits_be16(&gpio->par_feci2c, 0x0f00);
549 setbits_8(&gpio->par_fec0hl, 0xc0);
f3962d3f 550 } else {
32dbaafa
AW		 551 setbits_be16(&gpio->par_feci2c, 0x00a0);
552 setbits_8(&gpio->par_fec1hl, 0xc0);
f3962d3f
TL		 553 }
554 } else {
555 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
32dbaafa
AW		 556 clrbits_be16(&gpio->par_feci2c, 0x0f00);
557 clrbits_8(&gpio->par_fec0hl, 0xc0);
f3962d3f 558 } else {
32dbaafa
AW		 559 clrbits_be16(&gpio->par_feci2c, 0x00a0);
560 clrbits_8(&gpio->par_fec1hl, 0xc0);
f3962d3f
TL		 561 }
562 }
563
564 return 0;
565}
566#endif /* CONFIG_CMD_NET */
f71d9d91
MF		 567#endif /* #if defined(CONFIG_M5275) */
568
83ec20bc 569#if defined(CONFIG_M5282)
bf9e3b38
WD		 570/*
571 * Breath some life into the CPU...
572 *
573 * Set up the memory map,
574 * initialize a bunch of registers,
575 * initialize the UPM's
576 */
83ec20bc 577void cpu_init_f(void)
bf9e3b38 578{
9acb626f
HS		 579#ifndef CONFIG_WATCHDOG
580 /* disable watchdog if we aren't using it */
581 MCFWTM_WCR = 0;
582#endif
583
584#ifndef CONFIG_MONITOR_IS_IN_RAM
585 /* Set speed /PLL */
83ec20bc 586 MCFCLOCK_SYNCR =
012522fe
TL		 587 MCFCLOCK_SYNCR_MFD(CONFIG_SYS_MFD) |
588 MCFCLOCK_SYNCR_RFD(CONFIG_SYS_RFD);
83ec20bc
TL		 589 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
590
591 MCFGPIO_PBCDPAR = 0xc0;
9acb626f
HS		 592
593 /* Set up the GPIO ports */
6d0f6bcf
JCPV		 594#ifdef CONFIG_SYS_PEPAR
595 MCFGPIO_PEPAR = CONFIG_SYS_PEPAR;
9acb626f 596#endif
6d0f6bcf
JCPV		 597#ifdef CONFIG_SYS_PFPAR
598 MCFGPIO_PFPAR = CONFIG_SYS_PFPAR;
9acb626f 599#endif
6d0f6bcf
JCPV		 600#ifdef CONFIG_SYS_PJPAR
601 MCFGPIO_PJPAR = CONFIG_SYS_PJPAR;
9acb626f 602#endif
6d0f6bcf
JCPV		 603#ifdef CONFIG_SYS_PSDPAR
604 MCFGPIO_PSDPAR = CONFIG_SYS_PSDPAR;
9acb626f 605#endif
6d0f6bcf
JCPV		 606#ifdef CONFIG_SYS_PASPAR
607 MCFGPIO_PASPAR = CONFIG_SYS_PASPAR;
9acb626f 608#endif
6d0f6bcf
JCPV		 609#ifdef CONFIG_SYS_PEHLPAR
610 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
9acb626f 611#endif
6d0f6bcf
JCPV		 612#ifdef CONFIG_SYS_PQSPAR
613 MCFGPIO_PQSPAR = CONFIG_SYS_PQSPAR;
9acb626f 614#endif
6d0f6bcf
JCPV		 615#ifdef CONFIG_SYS_PTCPAR
616 MCFGPIO_PTCPAR = CONFIG_SYS_PTCPAR;
9acb626f 617#endif
dfc2b769
MD		 618#if defined(CONFIG_SYS_PORTTC)
619 MCFGPIO_PORTTC = CONFIG_SYS_PORTTC;
620#endif
621#if defined(CONFIG_SYS_DDRTC)
622 MCFGPIO_DDRTC = CONFIG_SYS_DDRTC;
623#endif
6d0f6bcf
JCPV		 624#ifdef CONFIG_SYS_PTDPAR
625 MCFGPIO_PTDPAR = CONFIG_SYS_PTDPAR;
9acb626f 626#endif
6d0f6bcf
JCPV		 627#ifdef CONFIG_SYS_PUAPAR
628 MCFGPIO_PUAPAR = CONFIG_SYS_PUAPAR;
9acb626f
HS		 629#endif
630
dfc2b769
MD		 631#if defined(CONFIG_SYS_DDRD)
632 MCFGPIO_DDRD = CONFIG_SYS_DDRD;
633#endif
6d0f6bcf
JCPV		 634#ifdef CONFIG_SYS_DDRUA
635 MCFGPIO_DDRUA = CONFIG_SYS_DDRUA;
9acb626f
HS		 636#endif
637
012522fe
TL		 638 /* FlexBus Chipselect */
639 init_fbcs();
9acb626f 640
83ec20bc 641#endif /* CONFIG_MONITOR_IS_IN_RAM */
bf9e3b38 642
9acb626f
HS		 643 /* defer enabling cache until boot (see do_go) */
644 /* icache_enable(); */
bf9e3b38
WD		 645}
646
647/*
648 * initialize higher level parts of CPU like timers
649 */
83ec20bc 650int cpu_init_r(void)
bf9e3b38
WD		 651{
652 return (0);
653}
83ec20bc 654
52affe04 655void uart_port_conf(int port)
83ec20bc
TL		 656{
657 /* Setup Ports: */
52affe04 658 switch (port) {
83ec20bc
TL		 659 case 0:
660 MCFGPIO_PUAPAR &= 0xFc;
661 MCFGPIO_PUAPAR |= 0x03;
662 break;
663 case 1:
664 MCFGPIO_PUAPAR &= 0xF3;
665 MCFGPIO_PUAPAR |= 0x0C;
666 break;
667 case 2:
668 MCFGPIO_PASPAR &= 0xFF0F;
669 MCFGPIO_PASPAR |= 0x00A0;
670 break;
671 }
672}
f3962d3f
TL		 673
674#if defined(CONFIG_CMD_NET)
675int fecpin_setclear(struct eth_device *dev, int setclear)
676{
677 if (setclear) {
678 MCFGPIO_PASPAR |= 0x0F00;
679 MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
680 } else {
681 MCFGPIO_PASPAR &= 0xF0FF;
682 MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
683 }
684 return 0;
685}
686#endif /* CONFIG_CMD_NET */
bf9e3b38 687#endif
8c725b93
SR		 688
689#if defined(CONFIG_M5249)
690/*
691 * Breath some life into the CPU...
692 *
693 * Set up the memory map,
694 * initialize a bunch of registers,
695 * initialize the UPM's
696 */
83ec20bc 697void cpu_init_f(void)
8c725b93 698{
8c725b93
SR		 699 /*
700 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
83ec20bc
TL		 701 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
702 * which is their primary function.
703 * ~Jeremy
8c725b93 704 */
6d0f6bcf
JCPV		 705 mbar2_writeLong(MCFSIM_GPIO_FUNC, CONFIG_SYS_GPIO_FUNC);
706 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CONFIG_SYS_GPIO1_FUNC);
707 mbar2_writeLong(MCFSIM_GPIO_EN, CONFIG_SYS_GPIO_EN);
708 mbar2_writeLong(MCFSIM_GPIO1_EN, CONFIG_SYS_GPIO1_EN);
709 mbar2_writeLong(MCFSIM_GPIO_OUT, CONFIG_SYS_GPIO_OUT);
710 mbar2_writeLong(MCFSIM_GPIO1_OUT, CONFIG_SYS_GPIO1_OUT);
8c725b93
SR		 711
712 /*
713 * dBug Compliance:
714 * You can verify these values by using dBug's 'ird'
715 * (Internal Register Display) command
716 * ~Jeremy
717 *
977b50f8 718 */
83ec20bc 719 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
8c725b93
SR		 720 mbar_writeByte(MCFSIM_SYPCR, 0x00);
721 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
722 mbar_writeByte(MCFSIM_SWSR, 0x00);
723 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
724 mbar_writeByte(MCFSIM_SWDICR, 0x00);
725 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
726 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
727 mbar_writeByte(MCFSIM_I2CICR, 0x00);
728 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
729 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
730 mbar_writeByte(MCFSIM_ICR6, 0x00);
731 mbar_writeByte(MCFSIM_ICR7, 0x00);
732 mbar_writeByte(MCFSIM_ICR8, 0x00);
733 mbar_writeByte(MCFSIM_ICR9, 0x00);
734 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
735
736 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
977b50f8 737 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
8c725b93 738 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
83ec20bc 739 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
8c725b93
SR		 740
741 /* Setup interrupt priorities for gpio7 */
742 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
743
744 /* IDE Config registers */
745 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
746 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
747
012522fe
TL		 748 /* FlexBus Chipselect */
749 init_fbcs();
8c725b93
SR		 750
751 /* enable instruction cache now */
752 icache_enable();
753}
754
755/*
756 * initialize higher level parts of CPU like timers
757 */
83ec20bc 758int cpu_init_r(void)
8c725b93
SR		 759{
760 return (0);
761}
83ec20bc 762
52affe04 763void uart_port_conf(int port)
83ec20bc 764{
83ec20bc
TL		 765}
766#endif /* #if defined(CONFIG_M5249) */
"Das U-Boot" Source Tree