[people/ms/u-boot.git] / arch / m68k / cpu / mcf5445x / cpu_init.c

/*
 *
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/immap.h>
#include <asm/processor.h>
#include <asm/rtc.h>

#if defined(CONFIG_CMD_NET)
#include <config.h>
#include <net.h>
#include <asm/fec.h>
#endif

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f(void)
{
	volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;

	scm1->mpr = 0x77777777;
	scm1->pacra = 0;
	scm1->pacrb = 0;
	scm1->pacrc = 0;
	scm1->pacrd = 0;
	scm1->pacre = 0;
	scm1->pacrf = 0;
	scm1->pacrg = 0;

	/* FlexBus */
	gpio->par_be =
	    GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
	    GPIO_PAR_BE_BE0_BE0;
	gpio->par_fbctl =
	    GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
	    GPIO_PAR_FBCTL_TS_TS;

#if !defined(CONFIG_CF_SBF)
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
#endif
#endif

#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
	/* Latch chipselect */
	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
#endif

#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
#endif

#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
#endif

#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
#endif

#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
#endif

	/*
	 * now the flash base address is no longer at 0 (Newer ColdFire family
	 * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
	 * also move to the new location.
	 */
	if (CONFIG_SYS_CS0_BASE != 0)
		setvbr(CONFIG_SYS_CS0_BASE);

#ifdef CONFIG_FSL_I2C
	gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
#endif

	icache_enable();
}

/*
 * initialize higher level parts of CPU like timers
 */
int cpu_init_r(void)
{
#ifdef CONFIG_MCFRTC
	volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
	volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;

	rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
	rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
#endif

	return (0);
}

void uart_port_conf(int port)
{
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	/* Setup Ports: */
	switch (port) {
	case 0:
		gpio->par_uart &=
		    ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
		gpio->par_uart |=
		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
		break;
	case 1:
#ifdef CONFIG_SYS_UART1_PRI_GPIO
		gpio->par_uart &=
		    ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
		gpio->par_uart |=
		    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
		gpio->par_ssi &=
		    (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK);
		gpio->par_ssi |=
		    (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
#endif
		break;
	case 2:
#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
		gpio->par_timer &=
		    (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK);
		gpio->par_timer |=
		    (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
		gpio->par_timer &=
		    (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK);
		gpio->par_timer |=
		    (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
#endif
		break;
	}
}

#if defined(CONFIG_CMD_NET)
int fecpin_setclear(struct eth_device *dev, int setclear)
{
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
	struct fec_info_s *info = (struct fec_info_s *)dev->priv;

	if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
			gpio->par_feci2c |=
			    (GPIO_PAR_FECI2C_MDC0_MDC0 |
			     GPIO_PAR_FECI2C_MDIO0_MDIO0);
		else
			gpio->par_feci2c |=
			    (GPIO_PAR_FECI2C_MDC1_MDC1 |
			     GPIO_PAR_FECI2C_MDIO1_MDIO1);
#else
		gpio->par_feci2c |=
		    (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
#endif

		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
			gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
		else
			gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
	} else {
		gpio->par_feci2c &=
		    ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);

		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
			gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
		else
			gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
	}
	return 0;
}
#endif

#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
	    GPIO_PAR_DSPI_SCK_SCK;
}

int cfspi_claim_bus(uint bus, uint cs)
{
	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
		return -1;

	/* Clear FIFO and resume transfer */
	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);

	switch (cs) {
	case 0:
		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
		break;
	case 1:
		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
		gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
		break;
	case 2:
		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
		gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
		break;
	case 3:
		gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
		gpio->par_dma |= GPIO_PAR_DMA_DACK0_PCS3;
		break;
	case 5:
		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
		gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
		break;
	}

	return 0;
}

void cfspi_release_bus(uint bus, uint cs)
{
	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;

	dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);	/* Clear FIFO */

	switch (cs) {
	case 0:
		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
		break;
	case 1:
		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
		break;
	case 2:
		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
		break;
	case 3:
		gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
		break;
	case 5:
		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
		break;
	}
}
#endif
Commit	Line	Data
8ae158cd TL	1	/*
	2	*
	3	* (C) Copyright 2000-2003
	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	*
	6	* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
	7	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29	#include <watchdog.h>
8ae158cd	30	#include <asm/immap.h>
68e4e76a	31	#include <asm/processor.h>
8ae158cd TL	32	#include <asm/rtc.h>
8ae158cd TL	33
f3962d3f TL	34	#if defined(CONFIG_CMD_NET)
	35	#include <config.h>
	36	#include <net.h>
	37	#include <asm/fec.h>
	38	#endif
	39
8ae158cd TL	40	/*
	41	* Breath some life into the CPU...
	42	*
	43	* Set up the memory map,
	44	* initialize a bunch of registers,
	45	* initialize the UPM's
	46	*/
	47	void cpu_init_f(void)
	48	{
	49	volatile scm1_t scm1 = (scm1_t ) MMAP_SCM1;
	50	volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	51	volatile fbcs_t fbcs = (fbcs_t ) MMAP_FBCS;
	52
	53	scm1->mpr = 0x77777777;
	54	scm1->pacra = 0;
	55	scm1->pacrb = 0;
	56	scm1->pacrc = 0;
	57	scm1->pacrd = 0;
	58	scm1->pacre = 0;
	59	scm1->pacrf = 0;
	60	scm1->pacrg = 0;
	61
	62	/* FlexBus */
	63	gpio->par_be =
	64	GPIO_PAR_BE_BE3_BE3 \| GPIO_PAR_BE_BE2_BE2 \| GPIO_PAR_BE_BE1_BE1 \|
	65	GPIO_PAR_BE_BE0_BE0;
	66	gpio->par_fbctl =
	67	GPIO_PAR_FBCTL_OE \| GPIO_PAR_FBCTL_TA_TA \| GPIO_PAR_FBCTL_RW_RW \|
	68	GPIO_PAR_FBCTL_TS_TS;
	69
9f751551	70	#if !defined(CONFIG_CF_SBF)
6d0f6bcf JCPV	71	#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
	72	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
	73	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
	74	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
8ae158cd	75	#endif
9f751551	76	#endif
8ae158cd	77
6d0f6bcf	78	#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
8ae158cd	79	/* Latch chipselect */
6d0f6bcf JCPV	80	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
	81	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
	82	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
8ae158cd TL	83	#endif
8ae158cd TL	84
6d0f6bcf JCPV	85	#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
	86	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
	87	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
	88	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
8ae158cd TL	89	#endif
8ae158cd TL	90
6d0f6bcf JCPV	91	#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
	92	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
	93	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
	94	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
8ae158cd TL	95	#endif
8ae158cd TL	96
6d0f6bcf JCPV	97	#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
	98	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
	99	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
	100	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
8ae158cd TL	101	#endif
8ae158cd TL	102
6d0f6bcf JCPV	103	#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
	104	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
	105	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
	106	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
8ae158cd TL	107	#endif
8ae158cd TL	108
68e4e76a TL	109	/*
	110	* now the flash base address is no longer at 0 (Newer ColdFire family
	111	* boot at address 0 instead of 0xFFnn_nnnn). The vector table must
	112	* also move to the new location.
	113	*/
	114	if (CONFIG_SYS_CS0_BASE != 0)
	115	setvbr(CONFIG_SYS_CS0_BASE);
	116
8ae158cd TL	117	#ifdef CONFIG_FSL_I2C
	118	gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL \| GPIO_PAR_FECI2C_SDA_SDA;
	119	#endif
	120
	121	icache_enable();
	122	}
	123
	124	/*
	125	* initialize higher level parts of CPU like timers
	126	*/
	127	int cpu_init_r(void)
	128	{
bc3ccb13	129	#ifdef CONFIG_MCFRTC
6d0f6bcf	130	volatile rtc_t rtc = (volatile rtc_t )(CONFIG_SYS_MCFRTC_BASE);
8ae158cd	131	volatile rtcex_t rtcex = (volatile rtcex_t )&rtc->extended;
8ae158cd	132
6d0f6bcf JCPV	133	rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
6d0f6bcf JCPV	134	rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
8ae158cd TL	135	#endif
	136
	137	return (0);
	138	}
	139
52affe04	140	void uart_port_conf(int port)
8ae158cd TL	141	{
	142	volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	143
	144	/* Setup Ports: */
52affe04	145	switch (port) {
8ae158cd	146	case 0:
52affe04 TL	147	gpio->par_uart &=
	148	~(GPIO_PAR_UART_U0TXD_U0TXD \| GPIO_PAR_UART_U0RXD_U0RXD);
	149	gpio->par_uart \|=
8ae158cd TL	150	(GPIO_PAR_UART_U0TXD_U0TXD \| GPIO_PAR_UART_U0RXD_U0RXD);
	151	break;
	152	case 1:
52affe04 TL	153	#ifdef CONFIG_SYS_UART1_PRI_GPIO
	154	gpio->par_uart &=
	155	~(GPIO_PAR_UART_U1TXD_U1TXD \| GPIO_PAR_UART_U1RXD_U1RXD);
	156	gpio->par_uart \|=
8ae158cd	157	(GPIO_PAR_UART_U1TXD_U1TXD \| GPIO_PAR_UART_U1RXD_U1RXD);
52affe04 TL	158	#elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
	159	gpio->par_ssi &=
	160	(GPIO_PAR_SSI_SRXD_UNMASK \| GPIO_PAR_SSI_STXD_UNMASK);
	161	gpio->par_ssi \|=
	162	(GPIO_PAR_SSI_SRXD_U1RXD \| GPIO_PAR_SSI_STXD_U1TXD);
	163	#endif
	164	break;
	165	case 2:
	166	#if defined(CONFIG_SYS_UART2_ALT1_GPIO)
	167	gpio->par_timer &=
	168	(GPIO_PAR_TIMER_T3IN_UNMASK \| GPIO_PAR_TIMER_T2IN_UNMASK);
	169	gpio->par_timer \|=
	170	(GPIO_PAR_TIMER_T3IN_U2RXD \| GPIO_PAR_TIMER_T2IN_U2TXD);
	171	#elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
	172	gpio->par_timer &=
	173	(GPIO_PAR_FECI2C_SCL_UNMASK \| GPIO_PAR_FECI2C_SDA_UNMASK);
	174	gpio->par_timer \|=
	175	(GPIO_PAR_FECI2C_SCL_U2TXD \| GPIO_PAR_FECI2C_SDA_U2RXD);
	176	#endif
8ae158cd TL	177	break;
	178	}
	179	}
f3962d3f TL	180
	181	#if defined(CONFIG_CMD_NET)
	182	int fecpin_setclear(struct eth_device *dev, int setclear)
	183	{
	184	volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	185	struct fec_info_s info = (struct fec_info_s )dev->priv;
	186
	187	if (setclear) {
ae490997 WW	188	#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
	189	if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
	190	gpio->par_feci2c \|=
	191	(GPIO_PAR_FECI2C_MDC0_MDC0 \|
	192	GPIO_PAR_FECI2C_MDIO0_MDIO0);
	193	else
	194	gpio->par_feci2c \|=
	195	(GPIO_PAR_FECI2C_MDC1_MDC1 \|
	196	GPIO_PAR_FECI2C_MDIO1_MDIO1);
	197	#else
f3962d3f TL	198	gpio->par_feci2c \|=
f3962d3f TL	199	(GPIO_PAR_FECI2C_MDC0_MDC0 \| GPIO_PAR_FECI2C_MDIO0_MDIO0);
ae490997	200	#endif
f3962d3f TL	201
	202	if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
	203	gpio->par_fec \|= GPIO_PAR_FEC_FEC0_RMII_GPIO;
	204	else
	205	gpio->par_fec \|= GPIO_PAR_FEC_FEC1_RMII_ATA;
	206	} else {
	207	gpio->par_feci2c &=
	208	~(GPIO_PAR_FECI2C_MDC0_MDC0 \| GPIO_PAR_FECI2C_MDIO0_MDIO0);
	209
	210	if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
d04c1efa	211	gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
f3962d3f	212	else
d04c1efa	213	gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
f3962d3f TL	214	}
	215	return 0;
	216	}
	217	#endif
ee0a8462 TL	218
	219	#ifdef CONFIG_CF_DSPI
	220	void cfspi_port_conf(void)
	221	{
	222	volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	223
	224	gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN \| GPIO_PAR_DSPI_SOUT_SOUT \|
	225	GPIO_PAR_DSPI_SCK_SCK;
	226	}
	227
	228	int cfspi_claim_bus(uint bus, uint cs)
	229	{
	230	volatile dspi_t dspi = (dspi_t ) MMAP_DSPI;
	231	volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	232
	233	if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
	234	return -1;
	235
	236	/* Clear FIFO and resume transfer */
	237	dspi->mcr &= ~(DSPI_MCR_CTXF \| DSPI_MCR_CRXF);
	238
	239	switch (cs) {
	240	case 0:
	241	gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
	242	gpio->par_dspi \|= GPIO_PAR_DSPI_PCS0_PCS0;
	243	break;
	244	case 1:
	245	gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
	246	gpio->par_dspi \|= GPIO_PAR_DSPI_PCS1_PCS1;
	247	break;
	248	case 2:
	249	gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
	250	gpio->par_dspi \|= GPIO_PAR_DSPI_PCS2_PCS2;
	251	break;
e9b43cae WW	252	case 3:
	253	gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
	254	gpio->par_dma \|= GPIO_PAR_DMA_DACK0_PCS3;
	255	break;
ee0a8462 TL	256	case 5:
	257	gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
	258	gpio->par_dspi \|= GPIO_PAR_DSPI_PCS5_PCS5;
	259	break;
	260	}
	261
	262	return 0;
	263	}
	264
	265	void cfspi_release_bus(uint bus, uint cs)
	266	{
	267	volatile dspi_t dspi = (dspi_t ) MMAP_DSPI;
	268	volatile gpio_t gpio = (gpio_t ) MMAP_GPIO;
	269
	270	dspi->mcr &= ~(DSPI_MCR_CTXF \| DSPI_MCR_CRXF); /* Clear FIFO */
	271
	272	switch (cs) {
	273	case 0:
	274	gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
	275	break;
	276	case 1:
	277	gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
	278	break;
	279	case 2:
	280	gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
	281	break;
e9b43cae WW	282	case 3:
	283	gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
	284	break;
ee0a8462 TL	285	case 5:
	286	gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
	287	break;
	288	}
	289	}
	290	#endif