[people/ms/u-boot.git] / arch / m68k / cpu / mcf5445x / speed.c

/*
 *
 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>

#include <asm/immap.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/*
 * Low Power Divider specifications
 */
#define CLOCK_LPD_MIN		(1 << 0)	/* Divider (decoded) */
#define CLOCK_LPD_MAX		(1 << 15)	/* Divider (decoded) */

#define CLOCK_PLL_FVCO_MAX	540000000
#define CLOCK_PLL_FVCO_MIN	300000000

#define CLOCK_PLL_FSYS_MAX	266666666
#define CLOCK_PLL_FSYS_MIN	100000000
#define MHZ			1000000

void clock_enter_limp(int lpdiv)
{
	ccm_t *ccm = (ccm_t *)MMAP_CCM;
	int i, j;

	/* Check bounds of divider */
	if (lpdiv < CLOCK_LPD_MIN)
		lpdiv = CLOCK_LPD_MIN;
	if (lpdiv > CLOCK_LPD_MAX)
		lpdiv = CLOCK_LPD_MAX;

	/* Round divider down to nearest power of two */
	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;

#ifdef CONFIG_MCF5445x
	/* Apply the divider to the system clock */
	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
#endif

	/* Enable Limp Mode */
	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
}

/*
 * brief   Exit Limp mode
 * warning The PLL should be set and locked prior to exiting Limp mode
 */
void clock_exit_limp(void)
{
	ccm_t *ccm = (ccm_t *)MMAP_CCM;
	pll_t *pll = (pll_t *)MMAP_PLL;

	/* Exit Limp mode */
	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);

	/* Wait for the PLL to lock */
	while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
		;
}

#ifdef CONFIG_MCF5441x
void setup_5441x_clocks(void)
{
	ccm_t *ccm = (ccm_t *)MMAP_CCM;
	pll_t *pll = (pll_t *)MMAP_PLL;
	int temp, vco = 0, bootmod_ccr, pdr;

	bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;

	switch (bootmod_ccr) {
	case 0:
		out_be32(&pll->pcr, 0x00000013);
		out_be32(&pll->pdr, 0x00e70c61);
		clock_exit_limp();
		break;
	case 2:
		break;
	case 3:
		break;
	}

	/*Change frequency for Modelo SER1 USB host*/
#ifdef CONFIG_LOW_MCFCLK
	temp = in_be32(&pll->pcr);
	temp &= ~0x3f;
	temp |= 5;
	out_be32(&pll->pcr, temp);

	temp = in_be32(&pll->pdr);
	temp &= ~0x001f0000;
	temp |= 0x00040000;
	out_be32(&pll->pdr, temp);
	__asm__("tpf");
#endif

	setbits_be16(&ccm->misccr2, 0x02);

	vco =  ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
		CONFIG_SYS_INPUT_CLKSRC;
	gd->arch.vco_clk = vco;

	gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */

	pdr = in_be32(&pll->pdr);
	temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
	gd->cpu_clk = vco / temp;	/* cpu clock */
	gd->arch.flb_clk = vco / temp;	/* FlexBus clock */
	gd->arch.flb_clk >>= 1;
	if (in_be16(ccm->misccr2) & 2)		/* fsys/4 */
		gd->arch.flb_clk >>= 1;

	temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
	gd->bus_clk = vco / temp;	/* bus clock */

}
#endif

#ifdef CONFIG_MCF5445x
void setup_5445x_clocks(void)
{
	ccm_t *ccm = (ccm_t *)MMAP_CCM;
	pll_t *pll = (pll_t *)MMAP_PLL;
	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
	int pllmult_pci[] = { 12, 6, 16, 8 };
	int vco = 0, temp, fbtemp, pcrvalue;
	int *pPllmult = NULL;
	u16 fbpll_mask;
#ifdef CONFIG_PCI
	int bPci;
#endif

#ifdef CONFIG_M54455EVB
	u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
#endif
	u8 bootmode;

	/* To determine PCI is present or not */
	if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
	    ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
		pPllmult = &pllmult_pci[0];
		fbpll_mask = 3;		/* 11b */
#ifdef CONFIG_PCI
		bPci = 1;
#endif
	} else {
		pPllmult = &pllmult_nopci[0];
		fbpll_mask = 7;		/* 111b */
#ifdef CONFIG_PCI
		gd->pci_clk = 0;
		bPci = 0;
#endif
	}

#ifdef CONFIG_M54455EVB
	bootmode = (in_8(cpld) & 0x03);

	if (bootmode != 3) {
		/* Temporary read from CCR- fixed fb issue, must be the same clock
		   as pci or input clock, causing cpld/fpga read inconsistancy */
		fbtemp = pPllmult[ccm->ccr & fbpll_mask];

		/* Break down into small pieces, code still in flex bus */
		pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
		temp = fbtemp - 1;
		pcrvalue |= PLL_PCR_OUTDIV3(temp);

		out_be32(&pll->pcr, pcrvalue);
	}
#endif
#ifdef CONFIG_M54451EVB
	/* No external logic to read the bootmode, hard coded from built */
#ifdef CONFIG_CF_SBF
	bootmode = 3;
#else
	bootmode = 2;

	/* default value is 16 mul, set to 20 mul */
	pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
	out_be32(&pll->pcr, pcrvalue);
	while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
		;
#endif
#endif

	if (bootmode == 0) {
		/* RCON mode */
		vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;

		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
			/* invaild range, re-set in PCR */
			int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
			int i, j, bus;

			j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
			for (i = j; i < 0xFF; i++) {
				vco = i * CONFIG_SYS_INPUT_CLKSRC;
				if (vco >= CLOCK_PLL_FVCO_MIN) {
					bus = vco / temp;
					if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
						continue;
					else
						break;
				}
			}
			pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
			fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
			pcrvalue |= ((i << 24) | fbtemp);

			out_be32(&pll->pcr, pcrvalue);
		}
		gd->arch.vco_clk = vco;	/* Vco clock */
	} else if (bootmode == 2) {
		/* Normal mode */
		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
			/* Default value */
			pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
			pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
			out_be32(&pll->pcr, pcrvalue);
			vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
		}
		gd->arch.vco_clk = vco;	/* Vco clock */
	} else if (bootmode == 3) {
		/* serial mode */
		vco =  ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
		gd->arch.vco_clk = vco;	/* Vco clock */
	}

	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
		/* Limp mode */
	} else {
		gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */

		temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
		gd->cpu_clk = vco / temp;	/* cpu clock */

		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
		gd->bus_clk = vco / temp;	/* bus clock */

		temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
		gd->arch.flb_clk = vco / temp;	/* FlexBus clock */

#ifdef CONFIG_PCI
		if (bPci) {
			temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
			gd->pci_clk = vco / temp;	/* PCI clock */
		}
#endif
	}

#ifdef CONFIG_SYS_I2C_FSL
	gd->arch.i2c1_clk = gd->bus_clk;
#endif
}
#endif

/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
int get_clocks(void)
{
#ifdef CONFIG_MCF5441x
	setup_5441x_clocks();
#endif
#ifdef CONFIG_MCF5445x
	setup_5445x_clocks();
#endif

#ifdef CONFIG_SYS_FSL_I2C
	gd->arch.i2c1_clk = gd->bus_clk;
#endif

	return (0);
}
Commit	Line	Data
8ae158cd TL	1	/*
8ae158cd TL	2	*
198cafbf	3	* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
8ae158cd TL	4	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <common.h>
	26	#include <asm/processor.h>
	27
	28	#include <asm/immap.h>
198cafbf	29	#include <asm/io.h>
8ae158cd TL	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	/*
	34	* Low Power Divider specifications
	35	*/
	36	#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
	37	#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
	38
	39	#define CLOCK_PLL_FVCO_MAX 540000000
	40	#define CLOCK_PLL_FVCO_MIN 300000000
	41
	42	#define CLOCK_PLL_FSYS_MAX 266666666
	43	#define CLOCK_PLL_FSYS_MIN 100000000
	44	#define MHZ 1000000
	45
	46	void clock_enter_limp(int lpdiv)
	47	{
198cafbf	48	ccm_t ccm = (ccm_t )MMAP_CCM;
8ae158cd TL	49	int i, j;
	50
	51	/* Check bounds of divider */
	52	if (lpdiv < CLOCK_LPD_MIN)
	53	lpdiv = CLOCK_LPD_MIN;
	54	if (lpdiv > CLOCK_LPD_MAX)
	55	lpdiv = CLOCK_LPD_MAX;
	56
	57	/* Round divider down to nearest power of two */
	58	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
	59
45370e18	60	#ifdef CONFIG_MCF5445x
8ae158cd	61	/* Apply the divider to the system clock */
198cafbf	62	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
45370e18	63	#endif
8ae158cd TL	64
8ae158cd TL	65	/* Enable Limp Mode */
198cafbf	66	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
8ae158cd TL	67	}
	68
	69	/*
	70	* brief Exit Limp mode
	71	* warning The PLL should be set and locked prior to exiting Limp mode
	72	*/
	73	void clock_exit_limp(void)
	74	{
198cafbf AW	75	ccm_t ccm = (ccm_t )MMAP_CCM;
198cafbf AW	76	pll_t pll = (pll_t )MMAP_PLL;
8ae158cd TL	77
8ae158cd TL	78	/* Exit Limp mode */
198cafbf	79	clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
8ae158cd TL	80
8ae158cd TL	81	/* Wait for the PLL to lock */
198cafbf AW	82	while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
198cafbf AW	83	;
8ae158cd TL	84	}
8ae158cd TL	85
45370e18 AW	86	#ifdef CONFIG_MCF5441x
45370e18 AW	87	void setup_5441x_clocks(void)
8ae158cd	88	{
45370e18 AW	89	ccm_t ccm = (ccm_t )MMAP_CCM;
	90	pll_t pll = (pll_t )MMAP_PLL;
	91	int temp, vco = 0, bootmod_ccr, pdr;
	92
	93	bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
	94
	95	switch (bootmod_ccr) {
	96	case 0:
	97	out_be32(&pll->pcr, 0x00000013);
	98	out_be32(&pll->pdr, 0x00e70c61);
	99	clock_exit_limp();
	100	break;
	101	case 2:
	102	break;
	103	case 3:
	104	break;
	105	}
9f751551	106
45370e18 AW	107	/Change frequency for Modelo SER1 USB host/
	108	#ifdef CONFIG_LOW_MCFCLK
	109	temp = in_be32(&pll->pcr);
	110	temp &= ~0x3f;
	111	temp \|= 5;
	112	out_be32(&pll->pcr, temp);
	113
	114	temp = in_be32(&pll->pdr);
	115	temp &= ~0x001f0000;
	116	temp \|= 0x00040000;
	117	out_be32(&pll->pdr, temp);
	118	__asm__("tpf");
	119	#endif
	120
	121	setbits_be16(&ccm->misccr2, 0x02);
	122
	123	vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
	124	CONFIG_SYS_INPUT_CLKSRC;
1b9591c2	125	gd->arch.vco_clk = vco;
45370e18	126
1b9591c2	127	gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
45370e18 AW	128
	129	pdr = in_be32(&pll->pdr);
	130	temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
	131	gd->cpu_clk = vco / temp; /* cpu clock */
1b9591c2 JJ	132	gd->arch.flb_clk = vco / temp; /* FlexBus clock */
1b9591c2 JJ	133	gd->arch.flb_clk >>= 1;
45370e18	134	if (in_be16(ccm->misccr2) & 2) /* fsys/4 */
1b9591c2	135	gd->arch.flb_clk >>= 1;
45370e18 AW	136
	137	temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
	138	gd->bus_clk = vco / temp; /* bus clock */
	139
	140	}
	141	#endif
	142
	143	#ifdef CONFIG_MCF5445x
	144	void setup_5445x_clocks(void)
	145	{
198cafbf AW	146	ccm_t ccm = (ccm_t )MMAP_CCM;
198cafbf AW	147	pll_t pll = (pll_t )MMAP_PLL;
8ae158cd TL	148	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
8ae158cd TL	149	int pllmult_pci[] = { 12, 6, 16, 8 };
c1568ca5	150	int vco = 0, temp, fbtemp, pcrvalue;
8ae158cd TL	151	int *pPllmult = NULL;
8ae158cd TL	152	u16 fbpll_mask;
c1568ca5 MV	153	#ifdef CONFIG_PCI
	154	int bPci;
	155	#endif
9f751551 TL	156
9f751551 TL	157	#ifdef CONFIG_M54455EVB
198cafbf	158	u8 cpld = (u8 )(CONFIG_SYS_CS2_BASE + 3);
9f751551 TL	159	#endif
9f751551 TL	160	u8 bootmode;
8ae158cd TL	161
8ae158cd TL	162	/* To determine PCI is present or not */
198cafbf AW	163	if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) \|\|
198cafbf AW	164	((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
8ae158cd	165	pPllmult = &pllmult_pci[0];
9f751551	166	fbpll_mask = 3; /* 11b */
c1568ca5	167	#ifdef CONFIG_PCI
8ae158cd	168	bPci = 1;
c1568ca5	169	#endif
8ae158cd TL	170	} else {
8ae158cd TL	171	pPllmult = &pllmult_nopci[0];
9f751551	172	fbpll_mask = 7; /* 111b */
8ae158cd TL	173	#ifdef CONFIG_PCI
8ae158cd TL	174	gd->pci_clk = 0;
8ae158cd	175	bPci = 0;
c1568ca5	176	#endif
8ae158cd TL	177	}
	178
	179	#ifdef CONFIG_M54455EVB
198cafbf	180	bootmode = (in_8(cpld) & 0x03);
8ae158cd	181
9f751551 TL	182	if (bootmode != 3) {
	183	/* Temporary read from CCR- fixed fb issue, must be the same clock
	184	as pci or input clock, causing cpld/fpga read inconsistancy */
	185	fbtemp = pPllmult[ccm->ccr & fbpll_mask];
8ae158cd	186
9f751551	187	/* Break down into small pieces, code still in flex bus */
198cafbf	188	pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
9f751551 TL	189	temp = fbtemp - 1;
	190	pcrvalue \|= PLL_PCR_OUTDIV3(temp);
	191
198cafbf	192	out_be32(&pll->pcr, pcrvalue);
9f751551 TL	193	}
	194	#endif
	195	#ifdef CONFIG_M54451EVB
	196	/* No external logic to read the bootmode, hard coded from built */
	197	#ifdef CONFIG_CF_SBF
	198	bootmode = 3;
	199	#else
	200	bootmode = 2;
	201
	202	/* default value is 16 mul, set to 20 mul */
198cafbf AW	203	pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) \| 0x14000000;
	204	out_be32(&pll->pcr, pcrvalue);
	205	while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
	206	;
9f751551 TL	207	#endif
9f751551 TL	208	#endif
8ae158cd	209
9f751551	210	if (bootmode == 0) {
8ae158cd	211	/* RCON mode */
6d0f6bcf	212	vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
8ae158cd TL	213
	214	if ((vco < CLOCK_PLL_FVCO_MIN) \|\| (vco > CLOCK_PLL_FVCO_MAX)) {
	215	/* invaild range, re-set in PCR */
198cafbf	216	int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
8ae158cd TL	217	int i, j, bus;
8ae158cd TL	218
198cafbf	219	j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
8ae158cd	220	for (i = j; i < 0xFF; i++) {
6d0f6bcf	221	vco = i * CONFIG_SYS_INPUT_CLKSRC;
8ae158cd TL	222	if (vco >= CLOCK_PLL_FVCO_MIN) {
	223	bus = vco / temp;
	224	if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
	225	continue;
	226	else
	227	break;
	228	}
	229	}
198cafbf	230	pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
8ae158cd TL	231	fbtemp = ((i - 1) << 8) \| ((i - 1) << 12);
	232	pcrvalue \|= ((i << 24) \| fbtemp);
	233
198cafbf	234	out_be32(&pll->pcr, pcrvalue);
8ae158cd	235	}
7e2592fd	236	gd->arch.vco_clk = vco; /* Vco clock */
9f751551	237	} else if (bootmode == 2) {
8ae158cd	238	/* Normal mode */
198cafbf	239	vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
9f751551 TL	240	if ((vco < CLOCK_PLL_FVCO_MIN) \|\| (vco > CLOCK_PLL_FVCO_MAX)) {
9f751551 TL	241	/* Default value */
198cafbf AW	242	pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
	243	pcrvalue \|= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
	244	out_be32(&pll->pcr, pcrvalue);
	245	vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
9f751551	246	}
7e2592fd	247	gd->arch.vco_clk = vco; /* Vco clock */
9f751551	248	} else if (bootmode == 3) {
8ae158cd	249	/* serial mode */
198cafbf	250	vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
7e2592fd	251	gd->arch.vco_clk = vco; /* Vco clock */
8ae158cd	252	}
8ae158cd	253
198cafbf	254	if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
8ae158cd TL	255	/* Limp mode */
8ae158cd TL	256	} else {
7e2592fd	257	gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
8ae158cd	258
198cafbf	259	temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
8ae158cd TL	260	gd->cpu_clk = vco / temp; /* cpu clock */
8ae158cd TL	261
198cafbf	262	temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
8ae158cd TL	263	gd->bus_clk = vco / temp; /* bus clock */
8ae158cd TL	264
198cafbf	265	temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
7e2592fd	266	gd->arch.flb_clk = vco / temp; /* FlexBus clock */
8ae158cd TL	267
	268	#ifdef CONFIG_PCI
	269	if (bPci) {
198cafbf	270	temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
8ae158cd TL	271	gd->pci_clk = vco / temp; /* PCI clock */
	272	}
	273	#endif
	274	}
	275
00f792e0	276	#ifdef CONFIG_SYS_I2C_FSL
609e6ec3	277	gd->arch.i2c1_clk = gd->bus_clk;
45370e18 AW	278	#endif
	279	}
	280	#endif
	281
	282	/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
	283	int get_clocks(void)
	284	{
	285	#ifdef CONFIG_MCF5441x
	286	setup_5441x_clocks();
	287	#endif
	288	#ifdef CONFIG_MCF5445x
	289	setup_5445x_clocks();
	290	#endif
	291
00f792e0	292	#ifdef CONFIG_SYS_FSL_I2C
609e6ec3	293	gd->arch.i2c1_clk = gd->bus_clk;
eec567a6 TL	294	#endif
eec567a6 TL	295
8ae158cd TL	296	return (0);
8ae158cd TL	297	}