[people/ms/u-boot.git] / arch / m68k / include / asm / coldfire / dspi.h

/*
 * MCF5227x Internal Memory Map
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __DSPI_H__
#define __DSPI_H__

/* DMA Serial Peripheral Interface (DSPI) */
typedef struct dspi {
	u32 mcr;	/* 0x00 */
	u32 resv0;	/* 0x04 */
	u32 tcr;	/* 0x08 */
	u32 ctar[8];	/* 0x0C - 0x28 */
	u32 sr;		/* 0x2C */
	u32 irsr;	/* 0x30 */
	u32 tfr;	/* 0x34 - PUSHR */
	u16 resv1;	/* 0x38 */
	u16 rfr;	/* 0x3A - POPR */
#ifdef CONFIG_MCF547x_8x
	u32 tfdr[4];	/* 0x3C */
	u8 resv2[0x30];	/* 0x40 */
	u32 rfdr[4];	/* 0x7C */
#else
	u32 tfdr[16];	/* 0x3C */
	u32 rfdr[16];	/* 0x7C */
#endif
} dspi_t;

/* Module configuration */
#define DSPI_MCR_MSTR			(0x80000000)
#define DSPI_MCR_CSCK			(0x40000000)
#define DSPI_MCR_DCONF(x)		(((x)&0x03)<<28)
#define DSPI_MCR_FRZ			(0x08000000)
#define DSPI_MCR_MTFE			(0x04000000)
#define DSPI_MCR_PCSSE			(0x02000000)
#define DSPI_MCR_ROOE			(0x01000000)
#define DSPI_MCR_CSIS7			(0x00800000)
#define DSPI_MCR_CSIS6			(0x00400000)
#define DSPI_MCR_CSIS5			(0x00200000)
#define DSPI_MCR_CSIS4			(0x00100000)
#define DSPI_MCR_CSIS3			(0x00080000)
#define DSPI_MCR_CSIS2			(0x00040000)
#define DSPI_MCR_CSIS1			(0x00020000)
#define DSPI_MCR_CSIS0			(0x00010000)
#define DSPI_MCR_MDIS			(0x00004000)
#define DSPI_MCR_DTXF			(0x00002000)
#define DSPI_MCR_DRXF			(0x00001000)
#define DSPI_MCR_CTXF			(0x00000800)
#define DSPI_MCR_CRXF			(0x00000400)
#define DSPI_MCR_SMPL_PT(x)		(((x)&0x03)<<8)
#define DSPI_MCR_HALT			(0x00000001)

/* Transfer count */
#define DSPI_TCR_SPI_TCNT(x)		(((x)&0x0000FFFF)<<16)

/* Clock and transfer attributes */
#define DSPI_CTAR_DBR			(0x80000000)
#define DSPI_CTAR_TRSZ(x)		(((x)&0x0F)<<27)
#define DSPI_CTAR_CPOL			(0x04000000)
#define DSPI_CTAR_CPHA			(0x02000000)
#define DSPI_CTAR_LSBFE			(0x01000000)
#define DSPI_CTAR_PCSSCK(x)		(((x)&0x03)<<22)
#define DSPI_CTAR_PCSSCK_7CLK		(0x00A00000)
#define DSPI_CTAR_PCSSCK_5CLK		(0x00800000)
#define DSPI_CTAR_PCSSCK_3CLK		(0x00400000)
#define DSPI_CTAR_PCSSCK_1CLK		(0x00000000)
#define DSPI_CTAR_PASC(x)		(((x)&0x03)<<20)
#define DSPI_CTAR_PASC_7CLK		(0x00300000)
#define DSPI_CTAR_PASC_5CLK		(0x00200000)
#define DSPI_CTAR_PASC_3CLK		(0x00100000)
#define DSPI_CTAR_PASC_1CLK		(0x00000000)
#define DSPI_CTAR_PDT(x)		(((x)&0x03)<<18)
#define DSPI_CTAR_PDT_7CLK		(0x000A0000)
#define DSPI_CTAR_PDT_5CLK		(0x00080000)
#define DSPI_CTAR_PDT_3CLK		(0x00040000)
#define DSPI_CTAR_PDT_1CLK		(0x00000000)
#define DSPI_CTAR_PBR(x)		(((x)&0x03)<<16)
#define DSPI_CTAR_PBR_7CLK		(0x00030000)
#define DSPI_CTAR_PBR_5CLK		(0x00020000)
#define DSPI_CTAR_PBR_3CLK		(0x00010000)
#define DSPI_CTAR_PBR_1CLK		(0x00000000)
#define DSPI_CTAR_CSSCK(x)		(((x)&0x0F)<<12)
#define DSPI_CTAR_ASC(x)		(((x)&0x0F)<<8)
#define DSPI_CTAR_DT(x)			(((x)&0x0F)<<4)
#define DSPI_CTAR_BR(x)			(((x)&0x0F))

/* Status */
#define DSPI_SR_TCF			(0x80000000)
#define DSPI_SR_TXRXS			(0x40000000)
#define DSPI_SR_EOQF			(0x10000000)
#define DSPI_SR_TFUF			(0x08000000)
#define DSPI_SR_TFFF			(0x02000000)
#define DSPI_SR_RFOF			(0x00080000)
#define DSPI_SR_RFDF			(0x00020000)
#define DSPI_SR_TXCTR(x)		(((x)&0x0F)<<12)
#define DSPI_SR_TXPTR(x)		(((x)&0x0F)<<8)
#define DSPI_SR_RXCTR(x)		(((x)&0x0F)<<4)
#define DSPI_SR_RXPTR(x)		(((x)&0x0F))

/* DMA/interrupt request selct and enable */
#define DSPI_IRSR_TCFE			(0x80000000)
#define DSPI_IRSR_EOQFE			(0x10000000)
#define DSPI_IRSR_TFUFE			(0x08000000)
#define DSPI_IRSR_TFFFE			(0x02000000)
#define DSPI_IRSR_TFFFS			(0x01000000)
#define DSPI_IRSR_RFOFE			(0x00080000)
#define DSPI_IRSR_RFDFE			(0x00020000)
#define DSPI_IRSR_RFDFS			(0x00010000)

/* Transfer control - 32-bit access */
#define DSPI_TFR_CONT			(0x80000000)
#define DSPI_TFR_CTAS(x)		(((x)&0x07)<<12)
#define DSPI_TFR_EOQ			(0x08000000)
#define DSPI_TFR_CTCNT			(0x04000000)
#define DSPI_TFR_CS7			(0x00800000)
#define DSPI_TFR_CS6			(0x00400000)
#define DSPI_TFR_CS5			(0x00200000)
#define DSPI_TFR_CS4			(0x00100000)
#define DSPI_TFR_CS3			(0x00080000)
#define DSPI_TFR_CS2			(0x00040000)
#define DSPI_TFR_CS1			(0x00020000)
#define DSPI_TFR_CS0			(0x00010000)

/* Transfer Fifo */
#define DSPI_TFR_TXDATA(x)		(((x)&0xFFFF))

/* Bit definitions and macros for DRFR */
#define DSPI_RFR_RXDATA(x)		(((x)&0xFFFF))

/* Bit definitions and macros for DTFDR group */
#define DSPI_TFDR_TXDATA(x)		(((x)&0x0000FFFF))
#define DSPI_TFDR_TXCMD(x)		(((x)&0x0000FFFF)<<16)

/* Bit definitions and macros for DRFDR group */
#define DSPI_RFDR_RXDATA(x)		(((x)&0x0000FFFF))

#endif				/* __DSPI_H__ */
Commit	Line	Data
7af7751d TL	1	/*
	2	* MCF5227x Internal Memory Map
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
7af7751d TL	8	*/
	9
	10	#ifndef __DSPI_H__
	11	#define __DSPI_H__
	12
ee0a8462	13	/* DMA Serial Peripheral Interface (DSPI) */
7af7751d	14	typedef struct dspi {
ee0a8462 TL	15	u32 mcr; /* 0x00 */
	16	u32 resv0; /* 0x04 */
	17	u32 tcr; /* 0x08 */
	18	u32 ctar[8]; /* 0x0C - 0x28 */
	19	u32 sr; /* 0x2C */
	20	u32 irsr; /* 0x30 */
	21	u32 tfr; /* 0x34 - PUSHR */
	22	u16 resv1; /* 0x38 */
	23	u16 rfr; /* 0x3A - POPR */
012522fe	24	#ifdef CONFIG_MCF547x_8x
ee0a8462 TL	25	u32 tfdr[4]; /* 0x3C */
	26	u8 resv2[0x30]; /* 0x40 */
	27	u32 rfdr[4]; /* 0x7C */
012522fe	28	#else
ee0a8462 TL	29	u32 tfdr[16]; /* 0x3C */
ee0a8462 TL	30	u32 rfdr[16]; /* 0x7C */
012522fe	31	#endif
7af7751d TL	32	} dspi_t;
7af7751d TL	33
ee0a8462 TL	34	/* Module configuration */
	35	#define DSPI_MCR_MSTR (0x80000000)
	36	#define DSPI_MCR_CSCK (0x40000000)
	37	#define DSPI_MCR_DCONF(x) (((x)&0x03)<<28)
	38	#define DSPI_MCR_FRZ (0x08000000)
	39	#define DSPI_MCR_MTFE (0x04000000)
	40	#define DSPI_MCR_PCSSE (0x02000000)
	41	#define DSPI_MCR_ROOE (0x01000000)
	42	#define DSPI_MCR_CSIS7 (0x00800000)
	43	#define DSPI_MCR_CSIS6 (0x00400000)
	44	#define DSPI_MCR_CSIS5 (0x00200000)
	45	#define DSPI_MCR_CSIS4 (0x00100000)
	46	#define DSPI_MCR_CSIS3 (0x00080000)
	47	#define DSPI_MCR_CSIS2 (0x00040000)
	48	#define DSPI_MCR_CSIS1 (0x00020000)
	49	#define DSPI_MCR_CSIS0 (0x00010000)
	50	#define DSPI_MCR_MDIS (0x00004000)
	51	#define DSPI_MCR_DTXF (0x00002000)
	52	#define DSPI_MCR_DRXF (0x00001000)
	53	#define DSPI_MCR_CTXF (0x00000800)
	54	#define DSPI_MCR_CRXF (0x00000400)
	55	#define DSPI_MCR_SMPL_PT(x) (((x)&0x03)<<8)
	56	#define DSPI_MCR_HALT (0x00000001)
	57
	58	/* Transfer count */
	59	#define DSPI_TCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
7af7751d	60
ee0a8462 TL	61	/* Clock and transfer attributes */
	62	#define DSPI_CTAR_DBR (0x80000000)
	63	#define DSPI_CTAR_TRSZ(x) (((x)&0x0F)<<27)
	64	#define DSPI_CTAR_CPOL (0x04000000)
	65	#define DSPI_CTAR_CPHA (0x02000000)
	66	#define DSPI_CTAR_LSBFE (0x01000000)
	67	#define DSPI_CTAR_PCSSCK(x) (((x)&0x03)<<22)
	68	#define DSPI_CTAR_PCSSCK_7CLK (0x00A00000)
	69	#define DSPI_CTAR_PCSSCK_5CLK (0x00800000)
	70	#define DSPI_CTAR_PCSSCK_3CLK (0x00400000)
	71	#define DSPI_CTAR_PCSSCK_1CLK (0x00000000)
	72	#define DSPI_CTAR_PASC(x) (((x)&0x03)<<20)
	73	#define DSPI_CTAR_PASC_7CLK (0x00300000)
	74	#define DSPI_CTAR_PASC_5CLK (0x00200000)
	75	#define DSPI_CTAR_PASC_3CLK (0x00100000)
	76	#define DSPI_CTAR_PASC_1CLK (0x00000000)
	77	#define DSPI_CTAR_PDT(x) (((x)&0x03)<<18)
	78	#define DSPI_CTAR_PDT_7CLK (0x000A0000)
	79	#define DSPI_CTAR_PDT_5CLK (0x00080000)
	80	#define DSPI_CTAR_PDT_3CLK (0x00040000)
	81	#define DSPI_CTAR_PDT_1CLK (0x00000000)
	82	#define DSPI_CTAR_PBR(x) (((x)&0x03)<<16)
	83	#define DSPI_CTAR_PBR_7CLK (0x00030000)
	84	#define DSPI_CTAR_PBR_5CLK (0x00020000)
	85	#define DSPI_CTAR_PBR_3CLK (0x00010000)
	86	#define DSPI_CTAR_PBR_1CLK (0x00000000)
	87	#define DSPI_CTAR_CSSCK(x) (((x)&0x0F)<<12)
	88	#define DSPI_CTAR_ASC(x) (((x)&0x0F)<<8)
	89	#define DSPI_CTAR_DT(x) (((x)&0x0F)<<4)
	90	#define DSPI_CTAR_BR(x) (((x)&0x0F))
7af7751d	91
ee0a8462 TL	92	/* Status */
	93	#define DSPI_SR_TCF (0x80000000)
	94	#define DSPI_SR_TXRXS (0x40000000)
	95	#define DSPI_SR_EOQF (0x10000000)
	96	#define DSPI_SR_TFUF (0x08000000)
	97	#define DSPI_SR_TFFF (0x02000000)
	98	#define DSPI_SR_RFOF (0x00080000)
	99	#define DSPI_SR_RFDF (0x00020000)
	100	#define DSPI_SR_TXCTR(x) (((x)&0x0F)<<12)
	101	#define DSPI_SR_TXPTR(x) (((x)&0x0F)<<8)
	102	#define DSPI_SR_RXCTR(x) (((x)&0x0F)<<4)
	103	#define DSPI_SR_RXPTR(x) (((x)&0x0F))
7af7751d	104
ee0a8462 TL	105	/* DMA/interrupt request selct and enable */
	106	#define DSPI_IRSR_TCFE (0x80000000)
	107	#define DSPI_IRSR_EOQFE (0x10000000)
	108	#define DSPI_IRSR_TFUFE (0x08000000)
	109	#define DSPI_IRSR_TFFFE (0x02000000)
	110	#define DSPI_IRSR_TFFFS (0x01000000)
	111	#define DSPI_IRSR_RFOFE (0x00080000)
	112	#define DSPI_IRSR_RFDFE (0x00020000)
	113	#define DSPI_IRSR_RFDFS (0x00010000)
7af7751d	114
ee0a8462 TL	115	/* Transfer control - 32-bit access */
	116	#define DSPI_TFR_CONT (0x80000000)
	117	#define DSPI_TFR_CTAS(x) (((x)&0x07)<<12)
	118	#define DSPI_TFR_EOQ (0x08000000)
	119	#define DSPI_TFR_CTCNT (0x04000000)
	120	#define DSPI_TFR_CS7 (0x00800000)
	121	#define DSPI_TFR_CS6 (0x00400000)
	122	#define DSPI_TFR_CS5 (0x00200000)
	123	#define DSPI_TFR_CS4 (0x00100000)
	124	#define DSPI_TFR_CS3 (0x00080000)
	125	#define DSPI_TFR_CS2 (0x00040000)
	126	#define DSPI_TFR_CS1 (0x00020000)
	127	#define DSPI_TFR_CS0 (0x00010000)
7af7751d	128
ee0a8462 TL	129	/* Transfer Fifo */
ee0a8462 TL	130	#define DSPI_TFR_TXDATA(x) (((x)&0xFFFF))
7af7751d TL	131
7af7751d TL	132	/* Bit definitions and macros for DRFR */
ee0a8462	133	#define DSPI_RFR_RXDATA(x) (((x)&0xFFFF))
7af7751d TL	134
7af7751d TL	135	/* Bit definitions and macros for DTFDR group */
ee0a8462 TL	136	#define DSPI_TFDR_TXDATA(x) (((x)&0x0000FFFF))
ee0a8462 TL	137	#define DSPI_TFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
7af7751d TL	138
7af7751d TL	139	/* Bit definitions and macros for DRFDR group */
ee0a8462	140	#define DSPI_RFDR_RXDATA(x) (((x)&0x0000FFFF))
bae61eef	141
7af7751d	142	#endif /* __DSPI_H__ */