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4e5ca3eb | 1 | /* |
bf9e3b38 WD |
2 | * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> |
3 | * | |
4 | * (C) Copyright 2000 | |
4e5ca3eb WD |
5 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
bf9e3b38 | 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
4e5ca3eb WD |
18 | * GNU General Public License for more details. |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | ||
52b01760 TL |
28 | #include <asm/timer.h> |
29 | #include <asm/immap.h> | |
42a83765 | 30 | #include <watchdog.h> |
bf9e3b38 | 31 | |
99c03c17 TL |
32 | DECLARE_GLOBAL_DATA_PTR; |
33 | ||
42a83765 RR |
34 | static volatile ulong timestamp = 0; |
35 | ||
36 | #ifndef CONFIG_SYS_WATCHDOG_FREQ | |
37 | #define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2) | |
38 | #endif | |
cd42deeb | 39 | |
8e585f02 | 40 | #if defined(CONFIG_MCFTMR) |
6d0f6bcf | 41 | #ifndef CONFIG_SYS_UDELAY_BASE |
8e585f02 TL |
42 | # error "uDelay base not defined!" |
43 | #endif | |
44 | ||
6d0f6bcf | 45 | #if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK) |
8e585f02 TL |
46 | # error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" |
47 | #endif | |
52b01760 | 48 | extern void dtimer_intr_setup(void); |
8e585f02 | 49 | |
3eb90bad | 50 | void __udelay(unsigned long usec) |
8e585f02 | 51 | { |
6d0f6bcf | 52 | volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_UDELAY_BASE); |
8e585f02 TL |
53 | uint start, now, tmp; |
54 | ||
55 | while (usec > 0) { | |
56 | if (usec > 65000) | |
57 | tmp = 65000; | |
58 | else | |
59 | tmp = usec; | |
60 | usec = usec - tmp; | |
61 | ||
62 | /* Set up TIMER 3 as timebase clock */ | |
63 | timerp->tmr = DTIM_DTMR_RST_RST; | |
64 | timerp->tcn = 0; | |
65 | /* set period to 1 us */ | |
66 | timerp->tmr = | |
6d0f6bcf | 67 | CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | DTIM_DTMR_FRR | |
52b01760 | 68 | DTIM_DTMR_RST_EN; |
8e585f02 TL |
69 | |
70 | start = now = timerp->tcn; | |
71 | while (now < start + tmp) | |
72 | now = timerp->tcn; | |
73 | } | |
74 | } | |
75 | ||
76 | void dtimer_interrupt(void *not_used) | |
77 | { | |
6d0f6bcf | 78 | volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE); |
8e585f02 TL |
79 | |
80 | /* check for timer interrupt asserted */ | |
6d0f6bcf | 81 | if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) { |
8e585f02 TL |
82 | timerp->ter = (DTIM_DTER_CAP | DTIM_DTER_REF); |
83 | timestamp++; | |
42a83765 RR |
84 | |
85 | #if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG) | |
86 | if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) { | |
87 | WATCHDOG_RESET (); | |
88 | } | |
89 | #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */ | |
8e585f02 TL |
90 | return; |
91 | } | |
92 | } | |
93 | ||
94 | void timer_init(void) | |
95 | { | |
6d0f6bcf | 96 | volatile dtmr_t *timerp = (dtmr_t *) (CONFIG_SYS_TMR_BASE); |
8e585f02 TL |
97 | |
98 | timestamp = 0; | |
99 | ||
100 | timerp->tcn = 0; | |
101 | timerp->trr = 0; | |
102 | ||
103 | /* Set up TIMER 4 as clock */ | |
104 | timerp->tmr = DTIM_DTMR_RST_RST; | |
105 | ||
52b01760 | 106 | /* initialize and enable timer interrupt */ |
6d0f6bcf | 107 | irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0); |
8e585f02 TL |
108 | |
109 | timerp->tcn = 0; | |
110 | timerp->trr = 1000; /* Interrupt every ms */ | |
111 | ||
52b01760 | 112 | dtimer_intr_setup(); |
8e585f02 TL |
113 | |
114 | /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ | |
6d0f6bcf | 115 | timerp->tmr = CONFIG_SYS_TIMER_PRESCALER | DTIM_DTMR_CLK_DIV1 | |
8e585f02 TL |
116 | DTIM_DTMR_FRR | DTIM_DTMR_ORRI | DTIM_DTMR_RST_EN; |
117 | } | |
118 | ||
119 | void reset_timer(void) | |
120 | { | |
121 | timestamp = 0; | |
122 | } | |
123 | ||
124 | ulong get_timer(ulong base) | |
125 | { | |
126 | return (timestamp - base); | |
127 | } | |
128 | ||
129 | void set_timer(ulong t) | |
130 | { | |
131 | timestamp = t; | |
132 | } | |
133 | #endif /* CONFIG_MCFTMR */ | |
134 | ||
135 | #if defined(CONFIG_MCFPIT) | |
6d0f6bcf JCPV |
136 | #if !defined(CONFIG_SYS_PIT_BASE) |
137 | # error "CONFIG_SYS_PIT_BASE not defined!" | |
8e585f02 TL |
138 | #endif |
139 | ||
140 | static unsigned short lastinc; | |
141 | ||
3eb90bad | 142 | void __udelay(unsigned long usec) |
8e585f02 | 143 | { |
6d0f6bcf | 144 | volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_UDELAY_BASE); |
8e585f02 TL |
145 | uint tmp; |
146 | ||
147 | while (usec > 0) { | |
148 | if (usec > 65000) | |
149 | tmp = 65000; | |
150 | else | |
151 | tmp = usec; | |
152 | usec = usec - tmp; | |
153 | ||
154 | /* Set up TIMER 3 as timebase clock */ | |
155 | timerp->pcsr = PIT_PCSR_OVW; | |
156 | timerp->pmr = 0; | |
157 | /* set period to 1 us */ | |
6d0f6bcf | 158 | timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN; |
8e585f02 TL |
159 | |
160 | timerp->pmr = tmp; | |
161 | while (timerp->pcntr > 0) ; | |
162 | } | |
163 | } | |
164 | ||
165 | void timer_init(void) | |
166 | { | |
6d0f6bcf | 167 | volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE); |
8e585f02 TL |
168 | timestamp = 0; |
169 | ||
170 | /* Set up TIMER 4 as poll clock */ | |
171 | timerp->pcsr = PIT_PCSR_OVW; | |
172 | timerp->pmr = lastinc = 0; | |
6d0f6bcf | 173 | timerp->pcsr |= PIT_PCSR_PRE(CONFIG_SYS_PIT_PRESCALE) | PIT_PCSR_EN; |
8e585f02 TL |
174 | } |
175 | ||
176 | void set_timer(ulong t) | |
177 | { | |
6d0f6bcf | 178 | volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE); |
8e585f02 TL |
179 | |
180 | timestamp = 0; | |
181 | timerp->pmr = lastinc = 0; | |
182 | } | |
183 | ||
184 | ulong get_timer(ulong base) | |
185 | { | |
186 | unsigned short now, diff; | |
6d0f6bcf | 187 | volatile pit_t *timerp = (pit_t *) (CONFIG_SYS_PIT_BASE); |
8e585f02 TL |
188 | |
189 | now = timerp->pcntr; | |
190 | diff = -(now - lastinc); | |
191 | ||
192 | timestamp += diff; | |
193 | lastinc = now; | |
194 | return timestamp - base; | |
195 | } | |
196 | ||
197 | void wait_ticks(unsigned long ticks) | |
198 | { | |
199 | set_timer(0); | |
200 | while (get_timer(0) < ticks) ; | |
201 | } | |
202 | #endif /* CONFIG_MCFPIT */ | |
cd42deeb | 203 | |
70f05ac3 WD |
204 | /* |
205 | * This function is derived from PowerPC code (read timebase as long long). | |
206 | * On M68K it just returns the timer value. | |
207 | */ | |
208 | unsigned long long get_ticks(void) | |
209 | { | |
210 | return get_timer(0); | |
211 | } | |
212 | ||
f2302d44 SR |
213 | unsigned long usec2ticks(unsigned long usec) |
214 | { | |
215 | return get_timer(usec); | |
216 | } | |
217 | ||
70f05ac3 WD |
218 | /* |
219 | * This function is derived from PowerPC code (timebase clock frequency). | |
220 | * On M68K it returns the number of timer ticks per second. | |
221 | */ | |
52b01760 | 222 | ulong get_tbclk(void) |
70f05ac3 WD |
223 | { |
224 | ulong tbclk; | |
6d0f6bcf | 225 | tbclk = CONFIG_SYS_HZ; |
70f05ac3 WD |
226 | return tbclk; |
227 | } |