[people/ms/u-boot.git] / arch / microblaze / include / asm / cache.h

/*
 * Copyright (c) 2011 The Chromium OS Authors.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __MICROBLAZE_CACHE_H__
#define __MICROBLAZE_CACHE_H__

/*
 * The microblaze can have either a 4 or 16 byte cacheline depending on whether
 * you are using OPB(4) or CacheLink(16).  If the board config has not specified
 * a cacheline size we assume the larger value of 16 bytes for DMA buffer
 * alignment.
 */
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN	16
#endif

#endif /* __MICROBLAZE_CACHE_H__ */
Commit	Line	Data
ee729afd AS	1	/*
ee729afd AS	2	* Copyright (c) 2011 The Chromium OS Authors.
ee729afd	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
ee729afd AS	5	*/
	6
	7	#ifndef __MICROBLAZE_CACHE_H__
	8	#define __MICROBLAZE_CACHE_H__
	9
	10	/*
	11	* The microblaze can have either a 4 or 16 byte cacheline depending on whether
	12	* you are using OPB(4) or CacheLink(16). If the board config has not specified
	13	* a cacheline size we assume the larger value of 16 bytes for DMA buffer
	14	* alignment.
	15	*/
	16	#ifdef CONFIG_SYS_CACHELINE_SIZE
	17	#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
	18	#else
	19	#define ARCH_DMA_MINALIGN 16
	20	#endif
	21
	22	#endif /* __MICROBLAZE_CACHE_H__ */