[people/ms/u-boot.git] / arch / mips / Kconfig

menu "MIPS architecture"
	depends on MIPS

config SYS_ARCH
	default "mips"

config SYS_CPU
	default "mips32" if CPU_MIPS32
	default "mips64" if CPU_MIPS64

choice
	prompt "Target select"
	optional

config TARGET_QEMU_MIPS
	bool "Support qemu-mips"
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SUPPORTS_CPU_MIPS64_R1
	select SUPPORTS_CPU_MIPS64_R2
	select ROM_EXCEPTION_VECTORS

config TARGET_MALTA
	bool "Support malta"
	select DM
	select DM_SERIAL
	select DYNAMIC_IO_PORT_BASE
	select MIPS_CM
	select MIPS_L2_CACHE
	select OF_CONTROL
	select OF_ISA_BUS
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SUPPORTS_CPU_MIPS32_R6
	select SUPPORTS_CPU_MIPS64_R1
	select SUPPORTS_CPU_MIPS64_R2
	select SUPPORTS_CPU_MIPS64_R6
	select SWAP_IO_SPACE
	select MIPS_L1_CACHE_SHIFT_6
	select ROM_EXCEPTION_VECTORS

config TARGET_VCT
	bool "Support vct"
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD
	select ROM_EXCEPTION_VECTORS

config TARGET_DBAU1X00
	bool "Support dbau1x00"
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD
	select ROM_EXCEPTION_VECTORS
	select MIPS_TUNE_4KC

config TARGET_PB1X00
	bool "Support pb1x00"
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SYS_MIPS_CACHE_INIT_RAM_LOAD
	select ROM_EXCEPTION_VECTORS
	select MIPS_TUNE_4KC

config ARCH_ATH79
	bool "Support QCA/Atheros ath79"
	select OF_CONTROL
	select DM

config ARCH_BMIPS
	bool "Support BMIPS SoCs"
	select OF_CONTROL
	select DM
	select CLK
	select CPU
	select RAM
	select SYSRESET

config MACH_PIC32
	bool "Support Microchip PIC32"
	select OF_CONTROL
	select DM

config TARGET_BOSTON
	bool "Support Boston"
	select DM
	select DM_SERIAL
	select OF_CONTROL
	select MIPS_CM
	select MIPS_L1_CACHE_SHIFT_6
	select MIPS_L2_CACHE
	select OF_BOARD_SETUP
	select SUPPORTS_BIG_ENDIAN
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select SUPPORTS_CPU_MIPS32_R6
	select SUPPORTS_CPU_MIPS64_R1
	select SUPPORTS_CPU_MIPS64_R2
	select SUPPORTS_CPU_MIPS64_R6
	select ROM_EXCEPTION_VECTORS

config TARGET_XILFPGA
	bool "Support Imagination Xilfpga"
	select OF_CONTROL
	select DM
	select DM_SERIAL
	select DM_GPIO
	select DM_ETH
	select SUPPORTS_LITTLE_ENDIAN
	select SUPPORTS_CPU_MIPS32_R1
	select SUPPORTS_CPU_MIPS32_R2
	select MIPS_L1_CACHE_SHIFT_4
	select ROM_EXCEPTION_VECTORS
	help
	  This supports IMGTEC MIPSfpga platform

endchoice

source "board/dbau1x00/Kconfig"
source "board/imgtec/boston/Kconfig"
source "board/imgtec/malta/Kconfig"
source "board/imgtec/xilfpga/Kconfig"
source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-bmips/Kconfig"
source "arch/mips/mach-pic32/Kconfig"

if MIPS

choice
	prompt "Endianness selection"
	help
	  Some MIPS boards can be configured for either little or big endian
	  byte order. These modes require different U-Boot images. In general there
	  is one preferred byteorder for a particular system but some systems are
	  just as commonly used in the one or the other endianness.

config SYS_BIG_ENDIAN
	bool "Big endian"
	depends on SUPPORTS_BIG_ENDIAN

config SYS_LITTLE_ENDIAN
	bool "Little endian"
	depends on SUPPORTS_LITTLE_ENDIAN

endchoice

choice
	prompt "CPU selection"
	default CPU_MIPS32_R2

config CPU_MIPS32_R1
	bool "MIPS32 Release 1"
	depends on SUPPORTS_CPU_MIPS32_R1
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 1 through 5 of the
	  MIPS32 architecture.

config CPU_MIPS32_R2
	bool "MIPS32 Release 2"
	depends on SUPPORTS_CPU_MIPS32_R2
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 2 through 5 of the
	  MIPS32 architecture.

config CPU_MIPS32_R6
	bool "MIPS32 Release 6"
	depends on SUPPORTS_CPU_MIPS32_R6
	select 32BIT
	help
	  Choose this option to build an U-Boot for release 6 or later of the
	  MIPS32 architecture.

config CPU_MIPS64_R1
	bool "MIPS64 Release 1"
	depends on SUPPORTS_CPU_MIPS64_R1
	select 64BIT
	help
	  Choose this option to build a kernel for release 1 through 5 of the
	  MIPS64 architecture.

config CPU_MIPS64_R2
	bool "MIPS64 Release 2"
	depends on SUPPORTS_CPU_MIPS64_R2
	select 64BIT
	help
	  Choose this option to build a kernel for release 2 through 5 of the
	  MIPS64 architecture.

config CPU_MIPS64_R6
	bool "MIPS64 Release 6"
	depends on SUPPORTS_CPU_MIPS64_R6
	select 64BIT
	help
	  Choose this option to build a kernel for release 6 or later of the
	  MIPS64 architecture.

endchoice

menu "General setup"

config ROM_EXCEPTION_VECTORS
	bool "Build U-Boot image with exception vectors"
	help
	  Enable this to include exception vectors in the U-Boot image. This is
	  required if the U-Boot entry point is equal to the address of the
	  CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
	  U-Boot booted from parallel NOR flash).
	  Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
	  In that case the image size will be reduced by 0x500 bytes.

config MIPS_CM_BASE
	hex "MIPS CM GCR Base Address"
	depends on MIPS_CM
	default 0x16100000 if TARGET_BOSTON
	default 0x1fbf8000
	help
	  The physical base address at which to map the MIPS Coherence Manager
	  Global Configuration Registers (GCRs). This should be set such that
	  the GCRs occupy a region of the physical address space which is
	  otherwise unused, or at minimum that software doesn't need to access.

endmenu

menu "OS boot interface"

config MIPS_BOOT_CMDLINE_LEGACY
	bool "Hand over legacy command line to Linux kernel"
	default y
	help
	  Enable this option if you want U-Boot to hand over the Yamon-style
	  command line to the kernel. All bootargs will be prepared as argc/argv
	  compatible list. The argument count (argc) is stored in register $a0.
	  The address of the argument list (argv) is stored in register $a1.

config MIPS_BOOT_ENV_LEGACY
	bool "Hand over legacy environment to Linux kernel"
	default y
	help
	  Enable this option if you want U-Boot to hand over the Yamon-style
	  environment to the kernel. Information like memory size, initrd
	  address and size will be prepared as zero-terminated key/value list.
	  The address of the environment is stored in register $a2.

config MIPS_BOOT_FDT
	bool "Hand over a flattened device tree to Linux kernel"
	default n
	help
	  Enable this option if you want U-Boot to hand over a flattened
	  device tree to the kernel. According to UHI register $a0 will be set
	  to -2 and the FDT address is stored in $a1.

endmenu

config SUPPORTS_BIG_ENDIAN
	bool

config SUPPORTS_LITTLE_ENDIAN
	bool

config SUPPORTS_CPU_MIPS32_R1
	bool

config SUPPORTS_CPU_MIPS32_R2
	bool

config SUPPORTS_CPU_MIPS32_R6
	bool

config SUPPORTS_CPU_MIPS64_R1
	bool

config SUPPORTS_CPU_MIPS64_R2
	bool

config SUPPORTS_CPU_MIPS64_R6
	bool

config CPU_MIPS32
	bool
	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6

config CPU_MIPS64
	bool
	default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6

config MIPS_TUNE_4KC
	bool

config MIPS_TUNE_14KC
	bool

config MIPS_TUNE_24KC
	bool

config MIPS_TUNE_34KC
	bool

config MIPS_TUNE_74KC
	bool

config 32BIT
	bool

config 64BIT
	bool

config SWAP_IO_SPACE
	bool

config SYS_MIPS_CACHE_INIT_RAM_LOAD
	bool

config MIPS_INIT_STACK_IN_SRAM
	bool
	default n
	help
	  Select this if the initial stack frame could be setup in SRAM.
	  Normally the initial stack frame is set up in DRAM which is often
	  only available after lowlevel_init. With this option the initial
	  stack frame and the early C environment is set up before
	  lowlevel_init. Thus lowlevel_init does not need to be implemented
	  in assembler.

config SYS_DCACHE_SIZE
	int
	default 0
	help
	  The total size of the L1 Dcache, if known at compile time.

config SYS_DCACHE_LINE_SIZE
	int
	default 0
	help
	  The size of L1 Dcache lines, if known at compile time.

config SYS_ICACHE_SIZE
	int
	default 0
	help
	  The total size of the L1 ICache, if known at compile time.

config SYS_ICACHE_LINE_SIZE
	int
	default 0
	help
	  The size of L1 Icache lines, if known at compile time.

config SYS_CACHE_SIZE_AUTO
	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
		SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
	help
	  Select this (or let it be auto-selected by not defining any cache
	  sizes) in order to allow U-Boot to automatically detect the sizes
	  of caches at runtime. This has a small cost in code size & runtime
	  so if you know the cache configuration for your system at compile
	  time it would be beneficial to configure it.

config MIPS_L1_CACHE_SHIFT_4
	bool

config MIPS_L1_CACHE_SHIFT_5
	bool

config MIPS_L1_CACHE_SHIFT_6
	bool

config MIPS_L1_CACHE_SHIFT_7
	bool

config MIPS_L1_CACHE_SHIFT
	int
	default "7" if MIPS_L1_CACHE_SHIFT_7
	default "6" if MIPS_L1_CACHE_SHIFT_6
	default "5" if MIPS_L1_CACHE_SHIFT_5
	default "4" if MIPS_L1_CACHE_SHIFT_4
	default "5"

config MIPS_L2_CACHE
	bool
	help
	  Select this if your system includes an L2 cache and you want U-Boot
	  to initialise & maintain it.

config DYNAMIC_IO_PORT_BASE
	bool

config MIPS_CM
	bool
	help
	  Select this if your system contains a MIPS Coherence Manager and you
	  wish U-Boot to configure it or make use of it to retrieve system
	  information such as cache configuration.

endif

endmenu
Commit	Line	Data
dd84058d MY	1	menu "MIPS architecture"
	2	depends on MIPS
	3
	4	config SYS_ARCH
dd84058d MY	5	default "mips"
dd84058d MY	6
b9863b6d	7	config SYS_CPU
20286cdf PB	8	default "mips32" if CPU_MIPS32
20286cdf PB	9	default "mips64" if CPU_MIPS64
b9863b6d	10
dd84058d MY	11	choice
dd84058d MY	12	prompt "Target select"
a26cd049	13	optional
dd84058d MY	14
	15	config TARGET_QEMU_MIPS
	16	bool "Support qemu-mips"
0e1dc345 DS	17	select SUPPORTS_BIG_ENDIAN
0e1dc345 DS	18	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	19	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	20	select SUPPORTS_CPU_MIPS32_R2
aa45f75e DS	21	select SUPPORTS_CPU_MIPS64_R1
aa45f75e DS	22	select SUPPORTS_CPU_MIPS64_R2
af3971f8	23	select ROM_EXCEPTION_VECTORS
dd84058d MY	24
	25	config TARGET_MALTA
	26	bool "Support malta"
6242aa13 PB	27	select DM
6242aa13 PB	28	select DM_SERIAL
05e34255	29	select DYNAMIC_IO_PORT_BASE
566ce04d PB	30	select MIPS_CM
566ce04d PB	31	select MIPS_L2_CACHE
6242aa13 PB	32	select OF_CONTROL
6242aa13 PB	33	select OF_ISA_BUS
0e1dc345 DS	34	select SUPPORTS_BIG_ENDIAN
0e1dc345 DS	35	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	36	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	37	select SUPPORTS_CPU_MIPS32_R2
40ba13c9	38	select SUPPORTS_CPU_MIPS32_R6
0f832b9c PB	39	select SUPPORTS_CPU_MIPS64_R1
	40	select SUPPORTS_CPU_MIPS64_R2
	41	select SUPPORTS_CPU_MIPS64_R6
9d638eea	42	select SWAP_IO_SPACE
f53830e7	43	select MIPS_L1_CACHE_SHIFT_6
af3971f8	44	select ROM_EXCEPTION_VECTORS
dd84058d MY	45
	46	config TARGET_VCT
	47	bool "Support vct"
0e1dc345	48	select SUPPORTS_BIG_ENDIAN
02611cbb DS	49	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	50	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	51	select SYS_MIPS_CACHE_INIT_RAM_LOAD
af3971f8	52	select ROM_EXCEPTION_VECTORS
dd84058d MY	53
	54	config TARGET_DBAU1X00
	55	bool "Support dbau1x00"
0e1dc345 DS	56	select SUPPORTS_BIG_ENDIAN
0e1dc345 DS	57	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	58	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	59	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	60	select SYS_MIPS_CACHE_INIT_RAM_LOAD
af3971f8	61	select ROM_EXCEPTION_VECTORS
0315a289	62	select MIPS_TUNE_4KC
dd84058d MY	63
	64	config TARGET_PB1X00
	65	bool "Support pb1x00"
0e1dc345	66	select SUPPORTS_LITTLE_ENDIAN
02611cbb DS	67	select SUPPORTS_CPU_MIPS32_R1
02611cbb DS	68	select SUPPORTS_CPU_MIPS32_R2
dd7c7200	69	select SYS_MIPS_CACHE_INIT_RAM_LOAD
af3971f8	70	select ROM_EXCEPTION_VECTORS
0315a289	71	select MIPS_TUNE_4KC
dd84058d	72
1d3d0f1f WW	73	config ARCH_ATH79
	74	bool "Support QCA/Atheros ath79"
	75	select OF_CONTROL
	76	select DM
	77
ee422142 ÁFR	78	config ARCH_BMIPS
	79	bool "Support BMIPS SoCs"
	80	select OF_CONTROL
	81	select DM
	82	select CLK
	83	select CPU
	84	select RAM
	85	select SYSRESET
	86
32c1a6ee PCM	87	config MACH_PIC32
	88	bool "Support Microchip PIC32"
	89	select OF_CONTROL
	90	select DM
	91
ad8783cb PB	92	config TARGET_BOSTON
	93	bool "Support Boston"
	94	select DM
	95	select DM_SERIAL
	96	select OF_CONTROL
	97	select MIPS_CM
	98	select MIPS_L1_CACHE_SHIFT_6
	99	select MIPS_L2_CACHE
d2b12a57	100	select OF_BOARD_SETUP
ad8783cb PB	101	select SUPPORTS_BIG_ENDIAN
	102	select SUPPORTS_LITTLE_ENDIAN
	103	select SUPPORTS_CPU_MIPS32_R1
	104	select SUPPORTS_CPU_MIPS32_R2
	105	select SUPPORTS_CPU_MIPS32_R6
	106	select SUPPORTS_CPU_MIPS64_R1
	107	select SUPPORTS_CPU_MIPS64_R2
	108	select SUPPORTS_CPU_MIPS64_R6
af3971f8	109	select ROM_EXCEPTION_VECTORS
ad8783cb	110
ebf2b9e3 ZLK	111	config TARGET_XILFPGA
	112	bool "Support Imagination Xilfpga"
	113	select OF_CONTROL
	114	select DM
	115	select DM_SERIAL
	116	select DM_GPIO
	117	select DM_ETH
	118	select SUPPORTS_LITTLE_ENDIAN
	119	select SUPPORTS_CPU_MIPS32_R1
	120	select SUPPORTS_CPU_MIPS32_R2
	121	select MIPS_L1_CACHE_SHIFT_4
af3971f8	122	select ROM_EXCEPTION_VECTORS
ebf2b9e3 ZLK	123	help
	124	This supports IMGTEC MIPSfpga platform
	125
dd84058d MY	126	endchoice
	127
	128	source "board/dbau1x00/Kconfig"
ad8783cb	129	source "board/imgtec/boston/Kconfig"
dd84058d	130	source "board/imgtec/malta/Kconfig"
ebf2b9e3	131	source "board/imgtec/xilfpga/Kconfig"
dd84058d MY	132	source "board/micronas/vct/Kconfig"
	133	source "board/pb1x00/Kconfig"
	134	source "board/qemu-mips/Kconfig"
1d3d0f1f	135	source "arch/mips/mach-ath79/Kconfig"
ee422142	136	source "arch/mips/mach-bmips/Kconfig"
32c1a6ee	137	source "arch/mips/mach-pic32/Kconfig"
dd84058d	138
0e1dc345 DS	139	if MIPS
	140
	141	choice
	142	prompt "Endianness selection"
	143	help
	144	Some MIPS boards can be configured for either little or big endian
	145	byte order. These modes require different U-Boot images. In general there
	146	is one preferred byteorder for a particular system but some systems are
	147	just as commonly used in the one or the other endianness.
	148
	149	config SYS_BIG_ENDIAN
	150	bool "Big endian"
	151	depends on SUPPORTS_BIG_ENDIAN
	152
	153	config SYS_LITTLE_ENDIAN
	154	bool "Little endian"
	155	depends on SUPPORTS_LITTLE_ENDIAN
	156
	157	endchoice
	158
02611cbb DS	159	choice
	160	prompt "CPU selection"
	161	default CPU_MIPS32_R2
	162
	163	config CPU_MIPS32_R1
	164	bool "MIPS32 Release 1"
	165	depends on SUPPORTS_CPU_MIPS32_R1
	166	select 32BIT
	167	help
c52ebea1	168	Choose this option to build an U-Boot for release 1 through 5 of the
02611cbb DS	169	MIPS32 architecture.
	170
	171	config CPU_MIPS32_R2
	172	bool "MIPS32 Release 2"
	173	depends on SUPPORTS_CPU_MIPS32_R2
	174	select 32BIT
	175	help
c52ebea1 PB	176	Choose this option to build an U-Boot for release 2 through 5 of the
	177	MIPS32 architecture.
	178
	179	config CPU_MIPS32_R6
	180	bool "MIPS32 Release 6"
	181	depends on SUPPORTS_CPU_MIPS32_R6
	182	select 32BIT
	183	help
	184	Choose this option to build an U-Boot for release 6 or later of the
02611cbb DS	185	MIPS32 architecture.
	186
	187	config CPU_MIPS64_R1
	188	bool "MIPS64 Release 1"
	189	depends on SUPPORTS_CPU_MIPS64_R1
	190	select 64BIT
	191	help
c52ebea1	192	Choose this option to build a kernel for release 1 through 5 of the
02611cbb DS	193	MIPS64 architecture.
	194
	195	config CPU_MIPS64_R2
	196	bool "MIPS64 Release 2"
	197	depends on SUPPORTS_CPU_MIPS64_R2
	198	select 64BIT
	199	help
c52ebea1 PB	200	Choose this option to build a kernel for release 2 through 5 of the
	201	MIPS64 architecture.
	202
	203	config CPU_MIPS64_R6
	204	bool "MIPS64 Release 6"
	205	depends on SUPPORTS_CPU_MIPS64_R6
	206	select 64BIT
	207	help
	208	Choose this option to build a kernel for release 6 or later of the
02611cbb DS	209	MIPS64 architecture.
	210
	211	endchoice
	212
af3971f8 DS	213	menu "General setup"
	214
	215	config ROM_EXCEPTION_VECTORS
	216	bool "Build U-Boot image with exception vectors"
	217	help
	218	Enable this to include exception vectors in the U-Boot image. This is
	219	required if the U-Boot entry point is equal to the address of the
	220	CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
	221	U-Boot booted from parallel NOR flash).
	222	Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
	223	In that case the image size will be reduced by 0x500 bytes.
	224
939a255a PB	225	config MIPS_CM_BASE
	226	hex "MIPS CM GCR Base Address"
	227	depends on MIPS_CM
ed048e7c	228	default 0x16100000 if TARGET_BOSTON
939a255a PB	229	default 0x1fbf8000
	230	help
	231	The physical base address at which to map the MIPS Coherence Manager
	232	Global Configuration Registers (GCRs). This should be set such that
	233	the GCRs occupy a region of the physical address space which is
	234	otherwise unused, or at minimum that software doesn't need to access.
	235
af3971f8 DS	236	endmenu
af3971f8 DS	237
25fc664f DS	238	menu "OS boot interface"
	239
	240	config MIPS_BOOT_CMDLINE_LEGACY
	241	bool "Hand over legacy command line to Linux kernel"
	242	default y
	243	help
	244	Enable this option if you want U-Boot to hand over the Yamon-style
	245	command line to the kernel. All bootargs will be prepared as argc/argv
	246	compatible list. The argument count (argc) is stored in register $a0.
	247	The address of the argument list (argv) is stored in register $a1.
	248
ca65e585 DS	249	config MIPS_BOOT_ENV_LEGACY
	250	bool "Hand over legacy environment to Linux kernel"
	251	default y
	252	help
	253	Enable this option if you want U-Boot to hand over the Yamon-style
	254	environment to the kernel. Information like memory size, initrd
	255	address and size will be prepared as zero-terminated key/value list.
1cc0a9f4	256	The address of the environment is stored in register $a2.
ca65e585	257
5002d8cc	258	config MIPS_BOOT_FDT
90b1c9fa	259	bool "Hand over a flattened device tree to Linux kernel"
5002d8cc DS	260	default n
	261	help
	262	Enable this option if you want U-Boot to hand over a flattened
90b1c9fa DS	263	device tree to the kernel. According to UHI register $a0 will be set
90b1c9fa DS	264	to -2 and the FDT address is stored in $a1.
5002d8cc	265
25fc664f DS	266	endmenu
25fc664f DS	267
0e1dc345 DS	268	config SUPPORTS_BIG_ENDIAN
	269	bool
	270
	271	config SUPPORTS_LITTLE_ENDIAN
	272	bool
	273
02611cbb DS	274	config SUPPORTS_CPU_MIPS32_R1
	275	bool
	276
	277	config SUPPORTS_CPU_MIPS32_R2
	278	bool
	279
c52ebea1 PB	280	config SUPPORTS_CPU_MIPS32_R6
	281	bool
	282
02611cbb DS	283	config SUPPORTS_CPU_MIPS64_R1
	284	bool
	285
	286	config SUPPORTS_CPU_MIPS64_R2
	287	bool
	288
c52ebea1 PB	289	config SUPPORTS_CPU_MIPS64_R6
	290	bool
	291
c57dafb5 DS	292	config CPU_MIPS32
c57dafb5 DS	293	bool
c52ebea1	294	default y if CPU_MIPS32_R1 \|\| CPU_MIPS32_R2 \|\| CPU_MIPS32_R6
c57dafb5 DS	295
	296	config CPU_MIPS64
	297	bool
c52ebea1	298	default y if CPU_MIPS64_R1 \|\| CPU_MIPS64_R2 \|\| CPU_MIPS64_R6
c57dafb5	299
0315a289 DS	300	config MIPS_TUNE_4KC
	301	bool
	302
	303	config MIPS_TUNE_14KC
	304	bool
	305
	306	config MIPS_TUNE_24KC
	307	bool
	308
5f9cc363 DS	309	config MIPS_TUNE_34KC
	310	bool
	311
0a0a958b MV	312	config MIPS_TUNE_74KC
	313	bool
	314
02611cbb DS	315	config 32BIT
	316	bool
	317
	318	config 64BIT
	319	bool
	320
9d638eea DS	321	config SWAP_IO_SPACE
	322	bool
	323
dd7c7200 PB	324	config SYS_MIPS_CACHE_INIT_RAM_LOAD
	325	bool
	326
924ad866 DS	327	config MIPS_INIT_STACK_IN_SRAM
	328	bool
	329	default n
	330	help
	331	Select this if the initial stack frame could be setup in SRAM.
	332	Normally the initial stack frame is set up in DRAM which is often
	333	only available after lowlevel_init. With this option the initial
	334	stack frame and the early C environment is set up before
	335	lowlevel_init. Thus lowlevel_init does not need to be implemented
	336	in assembler.
	337
ace3be4f PB	338	config SYS_DCACHE_SIZE
	339	int
	340	default 0
	341	help
	342	The total size of the L1 Dcache, if known at compile time.
	343
37228621	344	config SYS_DCACHE_LINE_SIZE
4b7b0a0f	345	int
37228621 PB	346	default 0
	347	help
	348	The size of L1 Dcache lines, if known at compile time.
	349
ace3be4f PB	350	config SYS_ICACHE_SIZE
	351	int
	352	default 0
	353	help
	354	The total size of the L1 ICache, if known at compile time.
	355
37228621	356	config SYS_ICACHE_LINE_SIZE
ace3be4f PB	357	int
	358	default 0
	359	help
37228621	360	The size of L1 Icache lines, if known at compile time.
ace3be4f PB	361
	362	config SYS_CACHE_SIZE_AUTO
	363	def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
37228621	364	SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0
ace3be4f PB	365	help
	366	Select this (or let it be auto-selected by not defining any cache
	367	sizes) in order to allow U-Boot to automatically detect the sizes
	368	of caches at runtime. This has a small cost in code size & runtime
	369	so if you know the cache configuration for your system at compile
	370	time it would be beneficial to configure it.
	371
f53830e7 DS	372	config MIPS_L1_CACHE_SHIFT_4
	373	bool
	374
	375	config MIPS_L1_CACHE_SHIFT_5
	376	bool
	377
	378	config MIPS_L1_CACHE_SHIFT_6
	379	bool
	380
	381	config MIPS_L1_CACHE_SHIFT_7
	382	bool
	383
	384	config MIPS_L1_CACHE_SHIFT
	385	int
	386	default "7" if MIPS_L1_CACHE_SHIFT_7
	387	default "6" if MIPS_L1_CACHE_SHIFT_6
	388	default "5" if MIPS_L1_CACHE_SHIFT_5
	389	default "4" if MIPS_L1_CACHE_SHIFT_4
	390	default "5"
	391
4baa0ab6 PB	392	config MIPS_L2_CACHE
	393	bool
	394	help
	395	Select this if your system includes an L2 cache and you want U-Boot
	396	to initialise & maintain it.
	397
05e34255 PB	398	config DYNAMIC_IO_PORT_BASE
	399	bool
	400
b2b135d9 PB	401	config MIPS_CM
	402	bool
	403	help
	404	Select this if your system contains a MIPS Coherence Manager and you
	405	wish U-Boot to configure it or make use of it to retrieve system
	406	information such as cache configuration.
	407
0e1dc345 DS	408	endif
0e1dc345 DS	409
dd84058d	410	endmenu