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[people/ms/u-boot.git] / arch / mips / cpu / mips32 / au1x00 / au1x00_usb_ohci.c
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265817c7
WD		 1/*
2 * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
3 *
4 * (C) Copyright 2003
792a09eb 5 * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
265817c7 6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
265817c7
WD		 8 * Note: Part of this code has been derived from linux
9 *
10 */
11/*
12 * IMPORTANT NOTES
c7d703f3 13 * 1 - this driver is intended for use with USB Mass Storage Devices
265817c7
WD		 14 * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
15 */
16
17#include <config.h>
18
79b51ff8 19#ifdef CONFIG_USB_OHCI
265817c7
WD		 20
21/* #include <pci.h> no PCI on the AU1x00 */
22
23#include <common.h>
24#include <malloc.h>
25#include <asm/io.h>
26#include <asm/au1x00.h>
27#include <usb.h>
28#include "au1x00_usb_ohci.h"
29
30#define OHCI_USE_NPS /* force NoPowerSwitching mode */
31#define OHCI_VERBOSE_DEBUG /* not always helpful */
32#define OHCI_FILL_TRACE
33
34#define USBH_ENABLE_BE (1<<0)
35#define USBH_ENABLE_C (1<<1)
36#define USBH_ENABLE_E (1<<2)
37#define USBH_ENABLE_CE (1<<3)
38#define USBH_ENABLE_RD (1<<4)
39
c7d703f3 40#ifdef __LITTLE_ENDIAN
265817c7
WD		 41#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
42#else
43#define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
44#endif
45
46
47/* For initializing controller (mask in an HCFS mode too) */
48#define OHCI_CONTROL_INIT \
49 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
50
51#undef readl
52#undef writel
53
54#define readl(a) au_readl((long)(a))
55#define writel(v,a) au_writel((v),(int)(a))
56
57#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
58
59#define DEBUG
60#ifdef DEBUG
61#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
62#else
63#define dbg(format, arg...) do {} while(0)
64#endif /* DEBUG */
65#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
66#define SHOW_INFO
67#ifdef SHOW_INFO
68#define info(format, arg...) printf("INFO: " format "\n", ## arg)
69#else
70#define info(format, arg...) do {} while(0)
71#endif
72
73#define m16_swap(x) swap_16(x)
74#define m32_swap(x) swap_32(x)
75
76/* global ohci_t */
77static ohci_t gohci;
78/* this must be aligned to a 256 byte boundary */
79struct ohci_hcca ghcca[1];
80/* a pointer to the aligned storage */
81struct ohci_hcca *phcca;
82/* this allocates EDs for all possible endpoints */
83struct ohci_device ohci_dev;
84/* urb_priv */
85urb_priv_t urb_priv;
86/* RHSC flag */
87int got_rhsc;
88/* device which was disconnected */
89struct usb_device *devgone;
90
91/*-------------------------------------------------------------------------*/
92
93/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
94 * The erratum (#4) description is incorrect. AMD's workaround waits
95 * till some bits (mostly reserved) are clear; ok for all revs.
96 */
97#define OHCI_QUIRK_AMD756 0xabcd
98#define read_roothub(hc, register, mask) ({ \
99 u32 temp = readl (&hc->regs->roothub.register); \
100 if (hc->flags & OHCI_QUIRK_AMD756) \
101 while (temp & mask) \
102 temp = readl (&hc->regs->roothub.register); \
103 temp; })
104
105static u32 roothub_a (struct ohci *hc)
106 { return read_roothub (hc, a, 0xfc0fe000); }
107static inline u32 roothub_b (struct ohci *hc)
108 { return readl (&hc->regs->roothub.b); }
109static inline u32 roothub_status (struct ohci *hc)
110 { return readl (&hc->regs->roothub.status); }
111static u32 roothub_portstatus (struct ohci *hc, int i)
112 { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
113
114
115/* forward declaration */
116static int hc_interrupt (void);
117static void
118td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
119 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
120
121/*-------------------------------------------------------------------------*
122 * URB support functions
123 *-------------------------------------------------------------------------*/
124
125/* free HCD-private data associated with this URB */
126
127static void urb_free_priv (urb_priv_t * urb)
128{
129 int i;
130 int last;
131 struct td * td;
132
133 last = urb->length - 1;
134 if (last >= 0) {
135 for (i = 0; i <= last; i++) {
136 td = urb->td[i];
137 if (td) {
138 td->usb_dev = NULL;
139 urb->td[i] = NULL;
140 }
141 }
142 }
143}
144
145/*-------------------------------------------------------------------------*/
146
147#ifdef DEBUG
148static int sohci_get_current_frame_number (struct usb_device * dev);
149
150/* debug| print the main components of an URB
151 * small: 0) header + data packets 1) just header */
152
153static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
154 int transfer_len, struct devrequest * setup, char * str, int small)
155{
156 urb_priv_t * purb = &urb_priv;
157
158 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
159 str,
160 sohci_get_current_frame_number (dev),
161 usb_pipedevice (pipe),
162 usb_pipeendpoint (pipe),
163 usb_pipeout (pipe)? 'O': 'I',
164 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
165 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
166 purb->actual_length,
167 transfer_len, dev->status);
168#ifdef OHCI_VERBOSE_DEBUG
169 if (!small) {
170 int i, len;
171
172 if (usb_pipecontrol (pipe)) {
173 printf (__FILE__ ": cmd(8):");
174 for (i = 0; i < 8 ; i++)
175 printf (" %02x", ((__u8 *) setup) [i]);
176 printf ("\n");
177 }
178 if (transfer_len > 0 && buffer) {
179 printf (__FILE__ ": data(%d/%d):",
180 purb->actual_length,
181 transfer_len);
182 len = usb_pipeout (pipe)?
183 transfer_len: purb->actual_length;
184 for (i = 0; i < 16 && i < len; i++)
185 printf (" %02x", ((__u8 *) buffer) [i]);
186 printf ("%s\n", i < len? "...": "");
187 }
188 }
189#endif
190}
191
192/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
193void ep_print_int_eds (ohci_t *ohci, char * str) {
194 int i, j;
195 __u32 * ed_p;
196 for (i= 0; i < 32; i++) {
197 j = 5;
198 ed_p = &(ohci->hcca->int_table [i]);
199 if (*ed_p == 0)
200 continue;
201 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
202 while (*ed_p != 0 && j--) {
203 ed_t *ed = (ed_t *)m32_swap(ed_p);
204 printf (" ed: %4x;", ed->hwINFO);
205 ed_p = &ed->hwNextED;
206 }
207 printf ("\n");
208 }
209}
210
211static void ohci_dump_intr_mask (char *label, __u32 mask)
212{
213 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
214 label,
215 mask,
216 (mask & OHCI_INTR_MIE) ? " MIE" : "",
217 (mask & OHCI_INTR_OC) ? " OC" : "",
218 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
219 (mask & OHCI_INTR_FNO) ? " FNO" : "",
220 (mask & OHCI_INTR_UE) ? " UE" : "",
221 (mask & OHCI_INTR_RD) ? " RD" : "",
222 (mask & OHCI_INTR_SF) ? " SF" : "",
223 (mask & OHCI_INTR_WDH) ? " WDH" : "",
224 (mask & OHCI_INTR_SO) ? " SO" : ""
225 );
226}
227
228static void maybe_print_eds (char *label, __u32 value)
229{
230 ed_t *edp = (ed_t *)value;
231
232 if (value) {
233 dbg ("%s %08x", label, value);
234 dbg ("%08x", edp->hwINFO);
235 dbg ("%08x", edp->hwTailP);
236 dbg ("%08x", edp->hwHeadP);
237 dbg ("%08x", edp->hwNextED);
238 }
239}
240
241static char * hcfs2string (int state)
242{
243 switch (state) {
244 case OHCI_USB_RESET: return "reset";
245 case OHCI_USB_RESUME: return "resume";
246 case OHCI_USB_OPER: return "operational";
247 case OHCI_USB_SUSPEND: return "suspend";
248 }
249 return "?";
250}
251
252/* dump control and status registers */
253static void ohci_dump_status (ohci_t *controller)
254{
255 struct ohci_regs *regs = controller->regs;
256 __u32 temp;
257
258 temp = readl (&regs->revision) & 0xff;
259 if (temp != 0x10)
260 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
261
262 temp = readl (&regs->control);
263 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
264 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
265 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
266 (temp & OHCI_CTRL_IR) ? " IR" : "",
267 hcfs2string (temp & OHCI_CTRL_HCFS),
268 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
269 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
270 (temp & OHCI_CTRL_IE) ? " IE" : "",
271 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
272 temp & OHCI_CTRL_CBSR
273 );
274
275 temp = readl (&regs->cmdstatus);
276 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
277 (temp & OHCI_SOC) >> 16,
278 (temp & OHCI_OCR) ? " OCR" : "",
279 (temp & OHCI_BLF) ? " BLF" : "",
280 (temp & OHCI_CLF) ? " CLF" : "",
281 (temp & OHCI_HCR) ? " HCR" : ""
282 );
283
284 ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
285 ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
286
287 maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
288
289 maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
290 maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
291
292 maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
293 maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
294
295 maybe_print_eds ("donehead", readl (&regs->donehead));
296}
297
298static void ohci_dump_roothub (ohci_t *controller, int verbose)
299{
300 __u32 temp, ndp, i;
301
302 temp = roothub_a (controller);
303 ndp = (temp & RH_A_NDP);
304
305 if (verbose) {
306 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
307 ((temp & RH_A_POTPGT) >> 24) & 0xff,
308 (temp & RH_A_NOCP) ? " NOCP" : "",
309 (temp & RH_A_OCPM) ? " OCPM" : "",
310 (temp & RH_A_DT) ? " DT" : "",
311 (temp & RH_A_NPS) ? " NPS" : "",
312 (temp & RH_A_PSM) ? " PSM" : "",
313 ndp
314 );
315 temp = roothub_b (controller);
316 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
317 temp,
318 (temp & RH_B_PPCM) >> 16,
319 (temp & RH_B_DR)
320 );
321 temp = roothub_status (controller);
322 dbg ("roothub.status: %08x%s%s%s%s%s%s",
323 temp,
324 (temp & RH_HS_CRWE) ? " CRWE" : "",
325 (temp & RH_HS_OCIC) ? " OCIC" : "",
326 (temp & RH_HS_LPSC) ? " LPSC" : "",
327 (temp & RH_HS_DRWE) ? " DRWE" : "",
328 (temp & RH_HS_OCI) ? " OCI" : "",
329 (temp & RH_HS_LPS) ? " LPS" : ""
330 );
331 }
332
333 for (i = 0; i < ndp; i++) {
334 temp = roothub_portstatus (controller, i);
335 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
336 i,
337 temp,
338 (temp & RH_PS_PRSC) ? " PRSC" : "",
339 (temp & RH_PS_OCIC) ? " OCIC" : "",
340 (temp & RH_PS_PSSC) ? " PSSC" : "",
341 (temp & RH_PS_PESC) ? " PESC" : "",
342 (temp & RH_PS_CSC) ? " CSC" : "",
343
344 (temp & RH_PS_LSDA) ? " LSDA" : "",
345 (temp & RH_PS_PPS) ? " PPS" : "",
346 (temp & RH_PS_PRS) ? " PRS" : "",
347 (temp & RH_PS_POCI) ? " POCI" : "",
348 (temp & RH_PS_PSS) ? " PSS" : "",
349
350 (temp & RH_PS_PES) ? " PES" : "",
351 (temp & RH_PS_CCS) ? " CCS" : ""
352 );
353 }
354}
355
356static void ohci_dump (ohci_t *controller, int verbose)
357{
358 dbg ("OHCI controller usb-%s state", controller->slot_name);
359
360 /* dumps some of the state we know about */
361 ohci_dump_status (controller);
362 if (verbose)
363 ep_print_int_eds (controller, "hcca");
364 dbg ("hcca frame #%04x", controller->hcca->frame_no);
365 ohci_dump_roothub (controller, 1);
366}
367
368
369#endif /* DEBUG */
370
371/*-------------------------------------------------------------------------*
372 * Interface functions (URB)
373 *-------------------------------------------------------------------------*/
374
375/* get a transfer request */
376
377int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
378 int transfer_len, struct devrequest *setup, int interval)
379{
380 ohci_t *ohci;
381 ed_t * ed;
382 urb_priv_t *purb_priv;
383 int i, size = 0;
384
385 ohci = &gohci;
386
387 /* when controller's hung, permit only roothub cleanup attempts
388 * such as powering down ports */
389 if (ohci->disabled) {
390 err("sohci_submit_job: EPIPE");
391 return -1;
392 }
393
394 /* every endpoint has a ed, locate and fill it */
395 if (!(ed = ep_add_ed (dev, pipe))) {
396 err("sohci_submit_job: ENOMEM");
397 return -1;
398 }
399
400 /* for the private part of the URB we need the number of TDs (size) */
401 switch (usb_pipetype (pipe)) {
402 case PIPE_BULK: /* one TD for every 4096 Byte */
403 size = (transfer_len - 1) / 4096 + 1;
404 break;
405 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
406 size = (transfer_len == 0)? 2:
407 (transfer_len - 1) / 4096 + 3;
408 break;
409 }
410
411 if (size >= (N_URB_TD - 1)) {
412 err("need %d TDs, only have %d", size, N_URB_TD);
413 return -1;
414 }
415 purb_priv = &urb_priv;
416 purb_priv->pipe = pipe;
417
418 /* fill the private part of the URB */
419 purb_priv->length = size;
420 purb_priv->ed = ed;
421 purb_priv->actual_length = 0;
422
423 /* allocate the TDs */
424 /* note that td[0] was allocated in ep_add_ed */
425 for (i = 0; i < size; i++) {
426 purb_priv->td[i] = td_alloc (dev);
427 if (!purb_priv->td[i]) {
428 purb_priv->length = i;
429 urb_free_priv (purb_priv);
430 err("sohci_submit_job: ENOMEM");
431 return -1;
432 }
433 }
434
435 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
436 urb_free_priv (purb_priv);
437 err("sohci_submit_job: EINVAL");
438 return -1;
439 }
440
441 /* link the ed into a chain if is not already */
442 if (ed->state != ED_OPER)
443 ep_link (ohci, ed);
444
445 /* fill the TDs and link it to the ed */
446 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
447
448 return 0;
449}
450
451/*-------------------------------------------------------------------------*/
452
453#ifdef DEBUG
454/* tell us the current USB frame number */
455
456static int sohci_get_current_frame_number (struct usb_device *usb_dev)
457{
458 ohci_t *ohci = &gohci;
459
460 return m16_swap (ohci->hcca->frame_no);
461}
462#endif
463
464/*-------------------------------------------------------------------------*
465 * ED handling functions
466 *-------------------------------------------------------------------------*/
467
468/* link an ed into one of the HC chains */
469
470static int ep_link (ohci_t *ohci, ed_t *edi)
471{
472 volatile ed_t *ed = edi;
473
474 ed->state = ED_OPER;
475
476 switch (ed->type) {
477 case PIPE_CONTROL:
478 ed->hwNextED = 0;
479 if (ohci->ed_controltail == NULL) {
480 writel ((long)ed, &ohci->regs->ed_controlhead);
481 } else {
482 ohci->ed_controltail->hwNextED = m32_swap (ed);
483 }
484 ed->ed_prev = ohci->ed_controltail;
485 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
486 !ohci->ed_rm_list[1] && !ohci->sleeping) {
487 ohci->hc_control |= OHCI_CTRL_CLE;
488 writel (ohci->hc_control, &ohci->regs->control);
489 }
490 ohci->ed_controltail = edi;
491 break;
492
493 case PIPE_BULK:
494 ed->hwNextED = 0;
495 if (ohci->ed_bulktail == NULL) {
496 writel ((long)ed, &ohci->regs->ed_bulkhead);
497 } else {
498 ohci->ed_bulktail->hwNextED = m32_swap (ed);
499 }
500 ed->ed_prev = ohci->ed_bulktail;
501 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
502 !ohci->ed_rm_list[1] && !ohci->sleeping) {
503 ohci->hc_control |= OHCI_CTRL_BLE;
504 writel (ohci->hc_control, &ohci->regs->control);
505 }
506 ohci->ed_bulktail = edi;
507 break;
508 }
509 return 0;
510}
511
512/*-------------------------------------------------------------------------*/
513
514/* unlink an ed from one of the HC chains.
515 * just the link to the ed is unlinked.
516 * the link from the ed still points to another operational ed or 0
517 * so the HC can eventually finish the processing of the unlinked ed */
518
519static int ep_unlink (ohci_t *ohci, ed_t *ed)
520{
521 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
522
523 switch (ed->type) {
524 case PIPE_CONTROL:
525 if (ed->ed_prev == NULL) {
526 if (!ed->hwNextED) {
527 ohci->hc_control &= ~OHCI_CTRL_CLE;
528 writel (ohci->hc_control, &ohci->regs->control);
529 }
530 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
531 } else {
532 ed->ed_prev->hwNextED = ed->hwNextED;
533 }
534 if (ohci->ed_controltail == ed) {
535 ohci->ed_controltail = ed->ed_prev;
536 } else {
537 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
538 }
539 break;
540
541 case PIPE_BULK:
542 if (ed->ed_prev == NULL) {
543 if (!ed->hwNextED) {
544 ohci->hc_control &= ~OHCI_CTRL_BLE;
545 writel (ohci->hc_control, &ohci->regs->control);
546 }
547 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
548 } else {
549 ed->ed_prev->hwNextED = ed->hwNextED;
550 }
551 if (ohci->ed_bulktail == ed) {
552 ohci->ed_bulktail = ed->ed_prev;
553 } else {
554 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
555 }
556 break;
557 }
558 ed->state = ED_UNLINK;
559 return 0;
560}
561
562
563/*-------------------------------------------------------------------------*/
564
565/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
566 * but the USB stack is a little bit stateless so we do it at every transaction
567 * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
568 * in all other cases the state is left unchanged
569 * the ed info fields are setted anyway even though most of them should not change */
570
571static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
572{
573 td_t *td;
574 ed_t *ed_ret;
575 volatile ed_t *ed;
576
577 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
578 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
579
580 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
581 err("ep_add_ed: pending delete");
582 /* pending delete request */
583 return NULL;
584 }
585
586 if (ed->state == ED_NEW) {
587 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
588 /* dummy td; end of td list for ed */
589 td = td_alloc (usb_dev);
590 ed->hwTailP = m32_swap (td);
591 ed->hwHeadP = ed->hwTailP;
592 ed->state = ED_UNLINK;
593 ed->type = usb_pipetype (pipe);
594 ohci_dev.ed_cnt++;
595 }
596
597 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
598 | usb_pipeendpoint (pipe) << 7
599 | (usb_pipeisoc (pipe)? 0x8000: 0)
600 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
c60795f4 601 | (usb_dev->speed == USB_SPEED_LOW) << 13
265817c7
WD		 602 | usb_maxpacket (usb_dev, pipe) << 16);
603
604 return ed_ret;
605}
606
607/*-------------------------------------------------------------------------*
608 * TD handling functions
609 *-------------------------------------------------------------------------*/
610
611/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
612
613static void td_fill (ohci_t *ohci, unsigned int info,
614 void *data, int len,
615 struct usb_device *dev, int index, urb_priv_t *urb_priv)
616{
617 volatile td_t *td, *td_pt;
618#ifdef OHCI_FILL_TRACE
619 int i;
620#endif
621
622 if (index > urb_priv->length) {
623 err("index > length");
624 return;
625 }
626 /* use this td as the next dummy */
627 td_pt = urb_priv->td [index];
628 td_pt->hwNextTD = 0;
629
630 /* fill the old dummy TD */
631 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
632
633 td->ed = urb_priv->ed;
634 td->next_dl_td = NULL;
635 td->index = index;
636 td->data = (__u32)data;
637#ifdef OHCI_FILL_TRACE
9dbc3667
RB		 638 if (1 || (usb_pipebulk(urb_priv->pipe) &&
639 usb_pipeout(urb_priv->pipe))) {
265817c7
WD		 640 for (i = 0; i < len; i++)
641 printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
642 }
643#endif
644 if (!len)
645 data = 0;
646
647 td->hwINFO = m32_swap (info);
648 td->hwCBP = m32_swap (data);
649 if (data)
650 td->hwBE = m32_swap (data + len - 1);
651 else
652 td->hwBE = 0;
653 td->hwNextTD = m32_swap (td_pt);
654 td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
655
656 /* append to queue */
657 td->ed->hwTailP = td->hwNextTD;
658}
659
660/*-------------------------------------------------------------------------*/
661
662/* prepare all TDs of a transfer */
663
664#define kseg_to_phys(x) ((void *)((__u32)(x) - 0x80000000))
665
666static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
667 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
668{
669 ohci_t *ohci = &gohci;
670 int data_len = transfer_len;
671 void *data;
672 int cnt = 0;
673 __u32 info = 0;
674 unsigned int toggle = 0;
675
676 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
677 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
678 toggle = TD_T_TOGGLE;
679 } else {
680 toggle = TD_T_DATA0;
681 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
682 }
683 urb->td_cnt = 0;
684 if (data_len)
685 data = kseg_to_phys(buffer);
686 else
687 data = 0;
688
689 switch (usb_pipetype (pipe)) {
690 case PIPE_BULK:
691 info = usb_pipeout (pipe)?
692 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
693 while(data_len > 4096) {
694 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
695 data += 4096; data_len -= 4096; cnt++;
696 }
697 info = usb_pipeout (pipe)?
698 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
699 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
700 cnt++;
701
702 if (!ohci->sleeping)
703 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
704 break;
705
706 case PIPE_CONTROL:
707 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
708 td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
709 if (data_len > 0) {
710 info = usb_pipeout (pipe)?
711 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
712 /* NOTE: mishandles transfers >8K, some >4K */
713 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
714 }
715 info = usb_pipeout (pipe)?
716 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
717 td_fill (ohci, info, data, 0, dev, cnt++, urb);
718 if (!ohci->sleeping)
719 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
720 break;
721 }
722 if (urb->length != cnt)
723 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
724}
725
726/*-------------------------------------------------------------------------*
727 * Done List handling functions
728 *-------------------------------------------------------------------------*/
729
730
731/* calculate the transfer length and update the urb */
732
733static void dl_transfer_length(td_t * td)
734{
735 __u32 tdINFO, tdBE, tdCBP;
736 urb_priv_t *lurb_priv = &urb_priv;
737
738 tdINFO = m32_swap (td->hwINFO);
739 tdBE = m32_swap (td->hwBE);
740 tdCBP = m32_swap (td->hwCBP);
741
742
9dbc3667 743 if (!(usb_pipecontrol(lurb_priv->pipe) &&
265817c7
WD		 744 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
745 if (tdBE != 0) {
746 if (td->hwCBP == 0)
747 lurb_priv->actual_length += tdBE - td->data + 1;
748 else
749 lurb_priv->actual_length += tdCBP - td->data;
750 }
751 }
752}
753
754/*-------------------------------------------------------------------------*/
755
756/* replies to the request have to be on a FIFO basis so
757 * we reverse the reversed done-list */
758
759static td_t * dl_reverse_done_list (ohci_t *ohci)
760{
761 __u32 td_list_hc;
762 td_t *td_rev = NULL;
763 td_t *td_list = NULL;
764 urb_priv_t *lurb_priv = NULL;
765
766 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
767 ohci->hcca->done_head = 0;
768
769 while (td_list_hc) {
770 td_list = (td_t *)td_list_hc;
771
772 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
773 lurb_priv = &urb_priv;
774 dbg(" USB-error/status: %x : %p",
775 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
776 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
777 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
778 td_list->ed->hwHeadP =
779 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
780 (td_list->ed->hwHeadP & m32_swap (0x2));
781 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
782 } else
783 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
784 }
785 }
786
787 td_list->next_dl_td = td_rev;
788 td_rev = td_list;
789 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
790 }
791 return td_list;
792}
793
794/*-------------------------------------------------------------------------*/
795
796/* td done list */
797static int dl_done_list (ohci_t *ohci, td_t *td_list)
798{
799 td_t *td_list_next = NULL;
800 ed_t *ed;
801 int cc = 0;
802 int stat = 0;
803 /* urb_t *urb; */
804 urb_priv_t *lurb_priv;
805 __u32 tdINFO, edHeadP, edTailP;
806
807 while (td_list) {
808 td_list_next = td_list->next_dl_td;
809
810 lurb_priv = &urb_priv;
811 tdINFO = m32_swap (td_list->hwINFO);
812
813 ed = td_list->ed;
814
815 dl_transfer_length(td_list);
816
817 /* error code of transfer */
818 cc = TD_CC_GET (tdINFO);
819 if (cc != 0) {
820 dbg("ConditionCode %#x", cc);
821 stat = cc_to_error[cc];
822 }
823
824 if (ed->state != ED_NEW) {
825 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
826 edTailP = m32_swap (ed->hwTailP);
827
828 /* unlink eds if they are not busy */
829 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
830 ep_unlink (ohci, ed);
831 }
832
833 td_list = td_list_next;
834 }
835 return stat;
836}
837
838/*-------------------------------------------------------------------------*
839 * Virtual Root Hub
840 *-------------------------------------------------------------------------*/
841
842/* Device descriptor */
843static __u8 root_hub_dev_des[] =
844{
845 0x12, /* __u8 bLength; */
846 0x01, /* __u8 bDescriptorType; Device */
847 0x10, /* __u16 bcdUSB; v1.1 */
848 0x01,
849 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
850 0x00, /* __u8 bDeviceSubClass; */
851 0x00, /* __u8 bDeviceProtocol; */
852 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
853 0x00, /* __u16 idVendor; */
854 0x00,
855 0x00, /* __u16 idProduct; */
856 0x00,
857 0x00, /* __u16 bcdDevice; */
858 0x00,
859 0x00, /* __u8 iManufacturer; */
860 0x01, /* __u8 iProduct; */
861 0x00, /* __u8 iSerialNumber; */
862 0x01 /* __u8 bNumConfigurations; */
863};
864
865
866/* Configuration descriptor */
867static __u8 root_hub_config_des[] =
868{
869 0x09, /* __u8 bLength; */
870 0x02, /* __u8 bDescriptorType; Configuration */
871 0x19, /* __u16 wTotalLength; */
872 0x00,
873 0x01, /* __u8 bNumInterfaces; */
874 0x01, /* __u8 bConfigurationValue; */
875 0x00, /* __u8 iConfiguration; */
876 0x40, /* __u8 bmAttributes;
877 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
878 0x00, /* __u8 MaxPower; */
879
880 /* interface */
881 0x09, /* __u8 if_bLength; */
882 0x04, /* __u8 if_bDescriptorType; Interface */
883 0x00, /* __u8 if_bInterfaceNumber; */
884 0x00, /* __u8 if_bAlternateSetting; */
885 0x01, /* __u8 if_bNumEndpoints; */
886 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
887 0x00, /* __u8 if_bInterfaceSubClass; */
888 0x00, /* __u8 if_bInterfaceProtocol; */
889 0x00, /* __u8 if_iInterface; */
890
891 /* endpoint */
892 0x07, /* __u8 ep_bLength; */
893 0x05, /* __u8 ep_bDescriptorType; Endpoint */
894 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
895 0x03, /* __u8 ep_bmAttributes; Interrupt */
896 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
897 0x00,
898 0xff /* __u8 ep_bInterval; 255 ms */
899};
900
901static unsigned char root_hub_str_index0[] =
902{
903 0x04, /* __u8 bLength; */
904 0x03, /* __u8 bDescriptorType; String-descriptor */
905 0x09, /* __u8 lang ID */
906 0x04, /* __u8 lang ID */
907};
908
909static unsigned char root_hub_str_index1[] =
910{
911 28, /* __u8 bLength; */
912 0x03, /* __u8 bDescriptorType; String-descriptor */
913 'O', /* __u8 Unicode */
914 0, /* __u8 Unicode */
915 'H', /* __u8 Unicode */
916 0, /* __u8 Unicode */
917 'C', /* __u8 Unicode */
918 0, /* __u8 Unicode */
919 'I', /* __u8 Unicode */
920 0, /* __u8 Unicode */
921 ' ', /* __u8 Unicode */
922 0, /* __u8 Unicode */
923 'R', /* __u8 Unicode */
924 0, /* __u8 Unicode */
925 'o', /* __u8 Unicode */
926 0, /* __u8 Unicode */
927 'o', /* __u8 Unicode */
928 0, /* __u8 Unicode */
929 't', /* __u8 Unicode */
930 0, /* __u8 Unicode */
931 ' ', /* __u8 Unicode */
932 0, /* __u8 Unicode */
933 'H', /* __u8 Unicode */
934 0, /* __u8 Unicode */
935 'u', /* __u8 Unicode */
936 0, /* __u8 Unicode */
937 'b', /* __u8 Unicode */
938 0, /* __u8 Unicode */
939};
940
941/* Hub class-specific descriptor is constructed dynamically */
942
943
944/*-------------------------------------------------------------------------*/
945
946#define OK(x) len = (x); break
947#ifdef DEBUG
948#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
949#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
950#else
951#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
952#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
953#endif
954#define RD_RH_STAT roothub_status(&gohci)
955#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
956
957/* request to virtual root hub */
958
959int rh_check_port_status(ohci_t *controller)
960{
961 __u32 temp, ndp, i;
962 int res;
963
964 res = -1;
965 temp = roothub_a (controller);
966 ndp = (temp & RH_A_NDP);
967 for (i = 0; i < ndp; i++) {
968 temp = roothub_portstatus (controller, i);
969 /* check for a device disconnect */
970 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
971 (RH_PS_PESC | RH_PS_CSC)) &&
972 ((temp & RH_PS_CCS) == 0)) {
973 res = i;
974 break;
975 }
976 }
977 return res;
978}
979
980static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
981 void *buffer, int transfer_len, struct devrequest *cmd)
982{
983 void * data = buffer;
984 int leni = transfer_len;
985 int len = 0;
986 int stat = 0;
987 __u32 datab[4];
988 __u8 *data_buf = (__u8 *)datab;
989 __u16 bmRType_bReq;
990 __u16 wValue;
991 __u16 wIndex;
992 __u16 wLength;
993
994#ifdef DEBUG
995urb_priv.actual_length = 0;
996pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
997#else
5b84dd67 998 mdelay(1);
265817c7 999#endif
9dbc3667 1000 if (usb_pipeint(pipe)) {
265817c7
WD		 1001 info("Root-Hub submit IRQ: NOT implemented");
1002 return 0;
1003 }
1004
1005 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
1006 wValue = m16_swap (cmd->value);
1007 wIndex = m16_swap (cmd->index);
1008 wLength = m16_swap (cmd->length);
1009
1010 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1011 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1012
1013 switch (bmRType_bReq) {
1014 /* Request Destination:
1015 without flags: Device,
1016 RH_INTERFACE: interface,
1017 RH_ENDPOINT: endpoint,
1018 RH_CLASS means HUB here,
1019 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1020 */
1021
1022 case RH_GET_STATUS:
1023 *(__u16 *) data_buf = m16_swap (1); OK (2);
1024 case RH_GET_STATUS | RH_INTERFACE:
1025 *(__u16 *) data_buf = m16_swap (0); OK (2);
1026 case RH_GET_STATUS | RH_ENDPOINT:
1027 *(__u16 *) data_buf = m16_swap (0); OK (2);
1028 case RH_GET_STATUS | RH_CLASS:
1029 *(__u32 *) data_buf = m32_swap (
1030 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1031 OK (4);
1032 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
1033 *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
1034
1035 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1036 switch (wValue) {
1037 case (RH_ENDPOINT_STALL): OK (0);
1038 }
1039 break;
1040
1041 case RH_CLEAR_FEATURE | RH_CLASS:
1042 switch (wValue) {
1043 case RH_C_HUB_LOCAL_POWER:
1044 OK(0);
1045 case (RH_C_HUB_OVER_CURRENT):
1046 WR_RH_STAT(RH_HS_OCIC); OK (0);
1047 }
1048 break;
1049
1050 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1051 switch (wValue) {
1052 case (RH_PORT_ENABLE):
1053 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1054 case (RH_PORT_SUSPEND):
1055 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1056 case (RH_PORT_POWER):
1057 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1058 case (RH_C_PORT_CONNECTION):
1059 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1060 case (RH_C_PORT_ENABLE):
1061 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1062 case (RH_C_PORT_SUSPEND):
1063 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1064 case (RH_C_PORT_OVER_CURRENT):
1065 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1066 case (RH_C_PORT_RESET):
1067 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1068 }
1069 break;
1070
1071 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1072 switch (wValue) {
1073 case (RH_PORT_SUSPEND):
1074 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1075 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1076 if (RD_RH_PORTSTAT & RH_PS_CCS)
1077 WR_RH_PORTSTAT (RH_PS_PRS);
1078 OK (0);
1079 case (RH_PORT_POWER):
1080 WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
1081 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1082 if (RD_RH_PORTSTAT & RH_PS_CCS)
1083 WR_RH_PORTSTAT (RH_PS_PES );
1084 OK (0);
1085 }
1086 break;
1087
1088 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1089
1090 case RH_GET_DESCRIPTOR:
1091 switch ((wValue & 0xff00) >> 8) {
1092 case (0x01): /* device descriptor */
1093 len = min_t(unsigned int,
1094 leni,
1095 min_t(unsigned int,
1096 sizeof (root_hub_dev_des),
1097 wLength));
1098 data_buf = root_hub_dev_des; OK(len);
1099 case (0x02): /* configuration descriptor */
1100 len = min_t(unsigned int,
1101 leni,
1102 min_t(unsigned int,
1103 sizeof (root_hub_config_des),
1104 wLength));
1105 data_buf = root_hub_config_des; OK(len);
1106 case (0x03): /* string descriptors */
1107 if(wValue==0x0300) {
1108 len = min_t(unsigned int,
1109 leni,
1110 min_t(unsigned int,
1111 sizeof (root_hub_str_index0),
1112 wLength));
1113 data_buf = root_hub_str_index0;
1114 OK(len);
1115 }
1116 if(wValue==0x0301) {
1117 len = min_t(unsigned int,
1118 leni,
1119 min_t(unsigned int,
1120 sizeof (root_hub_str_index1),
1121 wLength));
1122 data_buf = root_hub_str_index1;
1123 OK(len);
1124 }
1125 default:
1126 stat = USB_ST_STALLED;
1127 }
1128 break;
1129
1130 case RH_GET_DESCRIPTOR | RH_CLASS:
1131 {
1132 __u32 temp = roothub_a (&gohci);
1133
1134 data_buf [0] = 9; /* min length; */
1135 data_buf [1] = 0x29;
1136 data_buf [2] = temp & RH_A_NDP;
1137 data_buf [3] = 0;
1138 if (temp & RH_A_PSM) /* per-port power switching? */
1139 data_buf [3] |= 0x1;
1140 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1141 data_buf [3] |= 0x10;
1142 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1143 data_buf [3] |= 0x8;
1144
1145 /* corresponds to data_buf[4-7] */
1146 datab [1] = 0;
1147 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1148 temp = roothub_b (&gohci);
1149 data_buf [7] = temp & RH_B_DR;
1150 if (data_buf [2] < 7) {
1151 data_buf [8] = 0xff;
1152 } else {
1153 data_buf [0] += 2;
1154 data_buf [8] = (temp & RH_B_DR) >> 8;
1155 data_buf [10] = data_buf [9] = 0xff;
1156 }
1157
1158 len = min_t(unsigned int, leni,
1159 min_t(unsigned int, data_buf [0], wLength));
1160 OK (len);
1161 }
1162
1163 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1164
1165 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1166
1167 default:
1168 dbg ("unsupported root hub command");
1169 stat = USB_ST_STALLED;
1170 }
1171
1172#ifdef DEBUG
1173 ohci_dump_roothub (&gohci, 1);
1174#else
5b84dd67 1175 mdelay(1);
265817c7
WD		 1176#endif
1177
1178 len = min_t(int, len, leni);
1179 if (data != data_buf)
1180 memcpy (data, data_buf, len);
1181 dev->act_len = len;
1182 dev->status = stat;
1183
1184#ifdef DEBUG
1185 if (transfer_len)
1186 urb_priv.actual_length = transfer_len;
1187 pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1188#else
5b84dd67 1189 mdelay(1);
265817c7
WD		 1190#endif
1191
1192 return stat;
1193}
1194
1195/*-------------------------------------------------------------------------*/
1196
1197/* common code for handling submit messages - used for all but root hub */
1198/* accesses. */
1199int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1200 int transfer_len, struct devrequest *setup, int interval)
1201{
1202 int stat = 0;
1203 int maxsize = usb_maxpacket(dev, pipe);
1204 int timeout;
1205
1206 /* device pulled? Shortcut the action. */
1207 if (devgone == dev) {
1208 dev->status = USB_ST_CRC_ERR;
1209 return 0;
1210 }
1211
1212#ifdef DEBUG
1213 urb_priv.actual_length = 0;
1214 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1215#else
5b84dd67 1216 mdelay(1);
265817c7
WD		 1217#endif
1218 if (!maxsize) {
1219 err("submit_common_message: pipesize for pipe %lx is zero",
1220 pipe);
1221 return -1;
1222 }
1223
1224 if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1225 err("sohci_submit_job failed");
1226 return -1;
1227 }
1228
5b84dd67 1229 mdelay(10);
265817c7
WD		 1230 /* ohci_dump_status(&gohci); */
1231
1232 /* allow more time for a BULK device to react - some are slow */
1233#define BULK_TO 5000 /* timeout in milliseconds */
9dbc3667 1234 if (usb_pipebulk(pipe))
265817c7
WD		 1235 timeout = BULK_TO;
1236 else
1237 timeout = 100;
1238
1239 timeout *= 4;
1240 /* wait for it to complete */
1241 for (;;) {
1242 /* check whether the controller is done */
1243 stat = hc_interrupt();
1244 if (stat < 0) {
1245 stat = USB_ST_CRC_ERR;
1246 break;
1247 }
1248 if (stat >= 0 && stat != 0xff) {
1249 /* 0xff is returned for an SF-interrupt */
1250 break;
1251 }
1252 if (--timeout) {
5b84dd67 1253 udelay(250); /* mdelay(1); */
265817c7
WD		 1254 } else {
1255 err("CTL:TIMEOUT ");
1256 stat = USB_ST_CRC_ERR;
1257 break;
1258 }
1259 }
1260 /* we got an Root Hub Status Change interrupt */
1261 if (got_rhsc) {
1262#ifdef DEBUG
1263 ohci_dump_roothub (&gohci, 1);
1264#endif
1265 got_rhsc = 0;
1266 /* abuse timeout */
1267 timeout = rh_check_port_status(&gohci);
1268 if (timeout >= 0) {
1269#if 0 /* this does nothing useful, but leave it here in case that changes */
1270 /* the called routine adds 1 to the passed value */
1271 usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1272#endif
1273 /*
1274 * XXX
1275 * This is potentially dangerous because it assumes
1276 * that only one device is ever plugged in!
1277 */
1278 devgone = dev;
1279 }
1280 }
1281
1282 dev->status = stat;
1283 dev->act_len = transfer_len;
1284
1285#ifdef DEBUG
1286 pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1287#else
5b84dd67 1288 mdelay(1);
265817c7
WD		 1289#endif
1290
1291 /* free TDs in urb_priv */
1292 urb_free_priv (&urb_priv);
1293 return 0;
1294}
1295
1296/* submit routines called from usb.c */
1297int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1298 int transfer_len)
1299{
1300 info("submit_bulk_msg");
1301 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1302}
1303
1304int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1305 int transfer_len, struct devrequest *setup)
1306{
1307 int maxsize = usb_maxpacket(dev, pipe);
1308
1309 info("submit_control_msg");
1310#ifdef DEBUG
1311 urb_priv.actual_length = 0;
1312 pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1313#else
5b84dd67 1314 mdelay(1);
265817c7
WD		 1315#endif
1316 if (!maxsize) {
1317 err("submit_control_message: pipesize for pipe %lx is zero",
1318 pipe);
1319 return -1;
1320 }
1321 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1322 gohci.rh.dev = dev;
1323 /* root hub - redirect */
1324 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1325 setup);
1326 }
1327
1328 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1329}
1330
1331int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1332 int transfer_len, int interval)
1333{
1334 info("submit_int_msg");
1335 return -1;
1336}
1337
1338/*-------------------------------------------------------------------------*
1339 * HC functions
1340 *-------------------------------------------------------------------------*/
1341
1342/* reset the HC and BUS */
1343
1344static int hc_reset (ohci_t *ohci)
1345{
1346 int timeout = 30;
1347 int smm_timeout = 50; /* 0,5 sec */
1348
1349 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1350 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1351 info("USB HC TakeOver from SMM");
1352 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
5b84dd67 1353 mdelay (10);
265817c7
WD		 1354 if (--smm_timeout == 0) {
1355 err("USB HC TakeOver failed!");
1356 return -1;
1357 }
1358 }
1359 }
1360
1361 /* Disable HC interrupts */
1362 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1363
1364 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1365 ohci->slot_name,
1366 readl (&ohci->regs->control));
1367
1368 /* Reset USB (needed by some controllers) */
1369 writel (0, &ohci->regs->control);
1370
1371 /* HC Reset requires max 10 us delay */
1372 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1373 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1374 if (--timeout == 0) {
1375 err("USB HC reset timed out!");
1376 return -1;
1377 }
1378 udelay (1);
1379 }
1380 return 0;
1381}
1382
1383/*-------------------------------------------------------------------------*/
1384
1385/* Start an OHCI controller, set the BUS operational
1386 * enable interrupts
1387 * connect the virtual root hub */
1388
1389static int hc_start (ohci_t * ohci)
1390{
1391 __u32 mask;
1392 unsigned int fminterval;
1393
1394 ohci->disabled = 1;
1395
1396 /* Tell the controller where the control and bulk lists are
1397 * The lists are empty now. */
1398
1399 writel (0, &ohci->regs->ed_controlhead);
1400 writel (0, &ohci->regs->ed_bulkhead);
1401
1402 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1403
1404 fminterval = 0x2edf;
1405 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1406 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1407 writel (fminterval, &ohci->regs->fminterval);
1408 writel (0x628, &ohci->regs->lsthresh);
1409
1410 /* start controller operations */
1411 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1412 ohci->disabled = 0;
1413 writel (ohci->hc_control, &ohci->regs->control);
1414
1415 /* disable all interrupts */
1416 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1417 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1418 OHCI_INTR_OC | OHCI_INTR_MIE);
1419 writel (mask, &ohci->regs->intrdisable);
1420 /* clear all interrupts */
1421 mask &= ~OHCI_INTR_MIE;
1422 writel (mask, &ohci->regs->intrstatus);
1423 /* Choose the interrupts we care about now - but w/o MIE */
1424 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1425 writel (mask, &ohci->regs->intrenable);
1426
1427#ifdef OHCI_USE_NPS
1428 /* required for AMD-756 and some Mac platforms */
1429 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1430 &ohci->regs->roothub.a);
1431 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1432#endif /* OHCI_USE_NPS */
1433
265817c7
WD		 1434 /* POTPGT delay is bits 24-31, in 2 ms units. */
1435 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1436
1437 /* connect the virtual root hub */
1438 ohci->rh.devnum = 0;
1439
1440 return 0;
1441}
1442
1443/*-------------------------------------------------------------------------*/
1444
1445/* an interrupt happens */
1446
1447static int
1448hc_interrupt (void)
1449{
1450 ohci_t *ohci = &gohci;
1451 struct ohci_regs *regs = ohci->regs;
1452 int ints;
1453 int stat = -1;
1454
1455 if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1456 ints = OHCI_INTR_WDH;
1457 } else {
1458 ints = readl (&regs->intrstatus);
1459 }
1460
1461 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1462
1463 if (ints & OHCI_INTR_RHSC) {
1464 got_rhsc = 1;
1465 }
1466
1467 if (ints & OHCI_INTR_UE) {
1468 ohci->disabled++;
1469 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1470 ohci->slot_name);
1471 /* e.g. due to PCI Master/Target Abort */
1472
1473#ifdef DEBUG
1474 ohci_dump (ohci, 1);
1475#else
5b84dd67 1476 mdelay(1);
265817c7
WD		 1477#endif
1478 /* FIXME: be optimistic, hope that bug won't repeat often. */
1479 /* Make some non-interrupt context restart the controller. */
1480 /* Count and limit the retries though; either hardware or */
1481 /* software errors can go forever... */
1482 hc_reset (ohci);
1483 return -1;
1484 }
1485
1486 if (ints & OHCI_INTR_WDH) {
5b84dd67 1487 mdelay(1);
265817c7
WD		 1488 writel (OHCI_INTR_WDH, &regs->intrdisable);
1489 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1490 writel (OHCI_INTR_WDH, &regs->intrenable);
1491 }
1492
1493 if (ints & OHCI_INTR_SO) {
1494 dbg("USB Schedule overrun\n");
1495 writel (OHCI_INTR_SO, &regs->intrenable);
1496 stat = -1;
1497 }
1498
1499 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1500 if (ints & OHCI_INTR_SF) {
1501 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
5b84dd67 1502 mdelay(1);
265817c7
WD		 1503 writel (OHCI_INTR_SF, &regs->intrdisable);
1504 if (ohci->ed_rm_list[frame] != NULL)
1505 writel (OHCI_INTR_SF, &regs->intrenable);
1506 stat = 0xff;
1507 }
1508
1509 writel (ints, &regs->intrstatus);
1510 return stat;
1511}
1512
1513/*-------------------------------------------------------------------------*/
1514
1515/*-------------------------------------------------------------------------*/
1516
1517/* De-allocate all resources.. */
1518
1519static void hc_release_ohci (ohci_t *ohci)
1520{
1521 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1522
1523 if (!ohci->disabled)
1524 hc_reset (ohci);
1525}
1526
1527/*-------------------------------------------------------------------------*/
1528
1529#define __read_32bit_c0_register(source, sel) \
1530({ int __res; \
1531 if (sel == 0) \
1532 __asm__ __volatile__( \
1533 "mfc0\t%0, " #source "\n\t" \
1534 : "=r" (__res)); \
1535 else \
1536 __asm__ __volatile__( \
1537 ".set\tmips32\n\t" \
1538 "mfc0\t%0, " #source ", " #sel "\n\t" \
1539 ".set\tmips0\n\t" \
1540 : "=r" (__res)); \
1541 __res; \
1542})
1543
1544#define read_c0_prid() __read_32bit_c0_register($15, 0)
1545
1546/*
1547 * low level initalisation routine, called from usb.c
1548 */
1549static char ohci_inited = 0;
1550
c7e3b2b5 1551int usb_lowlevel_init(int index, void **controller)
265817c7
WD		 1552{
1553 u32 pin_func;
1554 u32 sys_freqctrl, sys_clksrc;
1555 u32 prid = read_c0_prid();
1556
1557 dbg("in usb_lowlevel_init\n");
1558
1559 /* zero and disable FREQ2 */
1560 sys_freqctrl = au_readl(SYS_FREQCTRL0);
1561 sys_freqctrl &= ~0xFFF00000;
1562 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1563
1564 /* zero and disable USBH/USBD clocks */
1565 sys_clksrc = au_readl(SYS_CLKSRC);
1566 sys_clksrc &= ~0x00007FE0;
1567 au_writel(sys_clksrc, SYS_CLKSRC);
1568
1569 sys_freqctrl = au_readl(SYS_FREQCTRL0);
1570 sys_freqctrl &= ~0xFFF00000;
1571
1572 sys_clksrc = au_readl(SYS_CLKSRC);
1573 sys_clksrc &= ~0x00007FE0;
1574
1575 switch (prid & 0x000000FF) {
1576 case 0x00: /* DA */
1577 case 0x01: /* HA */
1578 case 0x02: /* HB */
1579 /* CPU core freq to 48MHz to slow it way down... */
1580 au_writel(4, SYS_CPUPLL);
1581
1582 /*
1583 * Setup 48MHz FREQ2 from CPUPLL for USB Host
1584 */
1585 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
1586 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
1587 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1588
1589 /* CPU core freq to 384MHz */
1590 au_writel(0x20, SYS_CPUPLL);
1591
1592 printf("Au1000: 48MHz OHCI workaround enabled\n");
1593 break;
1594
1595 default: /* HC and newer */
1596 /* FREQ2 = aux/2 = 48 MHz */
1597 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
1598 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1599 break;
1600 }
1601
1602 /*
1603 * Route 48MHz FREQ2 into USB Host and/or Device
1604 */
1605 sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
1606 au_writel(sys_clksrc, SYS_CLKSRC);
1607
1608 /* configure pins GPIO[14:9] as GPIO */
1609 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
1610
1611 au_writel(pin_func, SYS_PINFUNC);
1612 au_writel(0x2800, SYS_TRIOUTCLR);
1613 au_writel(0x0030, SYS_OUTPUTCLR);
1614
1615 dbg("OHCI board setup complete\n");
1616
1617 /* enable host controller */
1618 au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
1619 udelay(1000);
1620 au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
1621 udelay(1000);
1622
1623 /* wait for reset complete (read register twice; see au1500 errata) */
1624 while (au_readl(USB_HOST_CONFIG),
1625 !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
1626 udelay(1000);
1627
1628 dbg("OHCI clock running\n");
1629
1630 memset (&gohci, 0, sizeof (ohci_t));
1631 memset (&urb_priv, 0, sizeof (urb_priv_t));
1632
1633 /* align the storage */
1634 if ((__u32)&ghcca[0] & 0xff) {
1635 err("HCCA not aligned!!");
1636 return -1;
1637 }
1638 phcca = &ghcca[0];
1639 info("aligned ghcca %p", phcca);
1640 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1641 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1642 err("EDs not aligned!!");
1643 return -1;
1644 }
1645 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1646 if ((__u32)gtd & 0x7) {
1647 err("TDs not aligned!!");
1648 return -1;
1649 }
1650 ptd = gtd;
1651 gohci.hcca = phcca;
1652 memset (phcca, 0, sizeof (struct ohci_hcca));
1653
1654 gohci.disabled = 1;
1655 gohci.sleeping = 0;
1656 gohci.irq = -1;
1657 gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
1658
1659 gohci.flags = 0;
1660 gohci.slot_name = "au1x00";
1661
1662 dbg("OHCI revision: 0x%08x\n"
1663 " RH: a: 0x%08x b: 0x%08x\n",
1664 readl(&gohci.regs->revision),
1665 readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
1666
1667 if (hc_reset (&gohci) < 0)
1668 goto errout;
1669
1670 /* FIXME this is a second HC reset; why?? */
1671 writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
5b84dd67 1672 mdelay (10);
265817c7
WD		 1673
1674 if (hc_start (&gohci) < 0)
1675 goto errout;
1676
1677#ifdef DEBUG
1678 ohci_dump (&gohci, 1);
1679#else
5b84dd67 1680 mdelay(1);
265817c7
WD		 1681#endif
1682 ohci_inited = 1;
1683 return 0;
1684
1685 errout:
1686 err("OHCI initialization error\n");
1687 hc_release_ohci (&gohci);
1688 /* Initialization failed */
1689 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1690 return -1;
1691}
1692
c7e3b2b5 1693int usb_lowlevel_stop(int index)
265817c7
WD		 1694{
1695 /* this gets called really early - before the controller has */
1696 /* even been initialized! */
1697 if (!ohci_inited)
1698 return 0;
1699 /* TODO release any interrupts, etc. */
1700 /* call hc_release_ohci() here ? */
1701 hc_reset (&gohci);
1702 /* may not want to do this */
1703 /* Disable clock */
1704 au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1705 return 0;
1706}
1707
1708#endif /* CONFIG_USB_OHCI */
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