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Commit | Line | Data |
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c021880a WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
c021880a WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <command.h> | |
5dfb3ee3 | 10 | #include <netdev.h> |
5da627a4 | 11 | #include <asm/mipsregs.h> |
ccf8f824 | 12 | #include <asm/cacheops.h> |
b0c66af5 | 13 | #include <asm/reboot.h> |
ccf8f824 SK |
14 | |
15 | #define cache_op(op,addr) \ | |
16 | __asm__ __volatile__( \ | |
17 | " .set push \n" \ | |
18 | " .set noreorder \n" \ | |
19 | " .set mips3\n\t \n" \ | |
20 | " cache %0, %1 \n" \ | |
21 | " .set pop \n" \ | |
22 | : \ | |
23 | : "i" (op), "R" (*(unsigned char *)(addr))) | |
c021880a | 24 | |
b0c66af5 SK |
25 | void __attribute__((weak)) _machine_restart(void) |
26 | { | |
27 | } | |
28 | ||
54841ab5 | 29 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
c021880a | 30 | { |
b0c66af5 | 31 | _machine_restart(); |
3e38691e | 32 | |
c021880a WD |
33 | fprintf(stderr, "*** reset failed ***\n"); |
34 | return 0; | |
35 | } | |
36 | ||
03c031d5 | 37 | void flush_cache(ulong start_addr, ulong size) |
c021880a | 38 | { |
6d0f6bcf | 39 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; |
ccf8f824 SK |
40 | unsigned long addr = start_addr & ~(lsize - 1); |
41 | unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); | |
42 | ||
dc344589 YC |
43 | /* aend will be miscalculated when size is zero, so we return here */ |
44 | if (size == 0) | |
45 | return; | |
46 | ||
ccf8f824 | 47 | while (1) { |
cb0a6a1e ZZ |
48 | cache_op(HIT_WRITEBACK_INV_D, addr); |
49 | cache_op(HIT_INVALIDATE_I, addr); | |
ccf8f824 SK |
50 | if (addr == aend) |
51 | break; | |
52 | addr += lsize; | |
53 | } | |
c021880a | 54 | } |
5da627a4 | 55 | |
03d3bfb0 SR |
56 | void flush_dcache_range(ulong start_addr, ulong stop) |
57 | { | |
58 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; | |
59 | unsigned long addr = start_addr & ~(lsize - 1); | |
60 | unsigned long aend = (stop - 1) & ~(lsize - 1); | |
61 | ||
62 | while (1) { | |
cb0a6a1e | 63 | cache_op(HIT_WRITEBACK_INV_D, addr); |
03d3bfb0 SR |
64 | if (addr == aend) |
65 | break; | |
66 | addr += lsize; | |
67 | } | |
68 | } | |
69 | ||
70 | void invalidate_dcache_range(ulong start_addr, ulong stop) | |
71 | { | |
72 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; | |
73 | unsigned long addr = start_addr & ~(lsize - 1); | |
74 | unsigned long aend = (stop - 1) & ~(lsize - 1); | |
75 | ||
76 | while (1) { | |
cb0a6a1e | 77 | cache_op(HIT_INVALIDATE_D, addr); |
03d3bfb0 SR |
78 | if (addr == aend) |
79 | break; | |
80 | addr += lsize; | |
81 | } | |
82 | } | |
83 | ||
03c031d5 SK |
84 | void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) |
85 | { | |
e2ad8426 SK |
86 | write_c0_entrylo0(low0); |
87 | write_c0_pagemask(pagemask); | |
88 | write_c0_entrylo1(low1); | |
89 | write_c0_entryhi(hi); | |
90 | write_c0_index(index); | |
5da627a4 WD |
91 | tlb_write_indexed(); |
92 | } | |
5dfb3ee3 SK |
93 | |
94 | int cpu_eth_init(bd_t *bis) | |
95 | { | |
96 | #ifdef CONFIG_SOC_AU1X00 | |
97 | au1x00_enet_initialize(bis); | |
98 | #endif | |
99 | return 0; | |
100 | } |