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Commit | Line | Data |
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32afad78 ZZ |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
32afad78 ZZ |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <command.h> | |
10 | #include <netdev.h> | |
11 | #include <asm/mipsregs.h> | |
12 | #include <asm/cacheops.h> | |
13 | #include <asm/reboot.h> | |
14 | ||
15 | #define cache_op(op, addr) \ | |
16 | __asm__ __volatile__( \ | |
17 | " .set push\n" \ | |
18 | " .set noreorder\n" \ | |
19 | " .set mips64\n" \ | |
20 | " cache %0, %1\n" \ | |
21 | " .set pop\n" \ | |
22 | : \ | |
23 | : "i" (op), "R" (*(unsigned char *)(addr))) | |
24 | ||
25 | void __attribute__((weak)) _machine_restart(void) | |
26 | { | |
27 | fprintf(stderr, "*** reset failed ***\n"); | |
28 | ||
29 | while (1) | |
30 | /* NOP */; | |
31 | } | |
32 | ||
33 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) | |
34 | { | |
35 | _machine_restart(); | |
36 | ||
37 | return 0; | |
38 | } | |
39 | ||
40 | void flush_cache(ulong start_addr, ulong size) | |
41 | { | |
42 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; | |
43 | unsigned long addr = start_addr & ~(lsize - 1); | |
44 | unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); | |
45 | ||
46 | /* aend will be miscalculated when size is zero, so we return here */ | |
47 | if (size == 0) | |
48 | return; | |
49 | ||
50 | while (1) { | |
51 | cache_op(HIT_WRITEBACK_INV_D, addr); | |
52 | cache_op(HIT_INVALIDATE_I, addr); | |
53 | if (addr == aend) | |
54 | break; | |
55 | addr += lsize; | |
56 | } | |
57 | } | |
58 | ||
59 | void flush_dcache_range(ulong start_addr, ulong stop) | |
60 | { | |
61 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; | |
62 | unsigned long addr = start_addr & ~(lsize - 1); | |
63 | unsigned long aend = (stop - 1) & ~(lsize - 1); | |
64 | ||
65 | while (1) { | |
66 | cache_op(HIT_WRITEBACK_INV_D, addr); | |
67 | if (addr == aend) | |
68 | break; | |
69 | addr += lsize; | |
70 | } | |
71 | } | |
72 | ||
73 | void invalidate_dcache_range(ulong start_addr, ulong stop) | |
74 | { | |
75 | unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE; | |
76 | unsigned long addr = start_addr & ~(lsize - 1); | |
77 | unsigned long aend = (stop - 1) & ~(lsize - 1); | |
78 | ||
79 | while (1) { | |
80 | cache_op(HIT_INVALIDATE_D, addr); | |
81 | if (addr == aend) | |
82 | break; | |
83 | addr += lsize; | |
84 | } | |
85 | } | |
86 | ||
87 | void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) | |
88 | { | |
89 | write_c0_entrylo0(low0); | |
90 | write_c0_pagemask(pagemask); | |
91 | write_c0_entrylo1(low1); | |
92 | write_c0_entryhi(hi); | |
93 | write_c0_index(index); | |
94 | tlb_write_indexed(); | |
95 | } |