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445a886d ML |
1 | /* |
2 | * Copyright (C) 2011 Andes Technology Corporation | |
3 | * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> | |
4 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
445a886d ML |
7 | */ |
8 | ||
9 | #ifndef __AG101_H | |
10 | #define __AG101_H | |
11 | ||
12 | /* Hardware register bases */ | |
13 | ||
14 | /* AHB Controller */ | |
15 | #define CONFIG_FTAHBC020S_BASE 0x90100000 | |
16 | /* Static Memory Controller (SRAM) */ | |
17 | #define CONFIG_FTSMC020_BASE 0x90200000 | |
18 | /* FTSDMC021 SDRAM Controller */ | |
19 | #define CONFIG_FTSDMC021_BASE 0x90300000 | |
20 | /* DMA Controller */ | |
21 | #define CONFIG_FTDMAC020_BASE 0x90400000 | |
22 | /* AHB-to-APB Bridge */ | |
23 | #define CONFIG_FTAPBBRG020S_01_BASE 0x90500000 | |
24 | /* LCD Controller */ | |
25 | #define CONFIG_FTLCDC100_BASE 0x90600000 | |
26 | /* Reserved */ | |
27 | #define CONFIG_RESERVED_01_BASE 0x90700000 | |
28 | /* Reserved */ | |
29 | #define CONFIG_RESERVED_02_BASE 0x90800000 | |
30 | /* Ethernet */ | |
31 | #define CONFIG_FTMAC100_BASE 0x90900000 | |
32 | /* External USB host */ | |
33 | #define CONFIG_EXT_USB_HOST_BASE 0x90A00000 | |
34 | /* USB Device */ | |
35 | #define CONFIG_USB_DEV_BASE 0x90B00000 | |
36 | /* External AHB-to-PCI Bridge (FTPCI100 not exist in ag101) */ | |
37 | #define CONFIG_EXT_AHBPCIBRG_BASE 0x90C00000 | |
38 | /* Reserved */ | |
39 | #define CONFIG_RESERVED_03_BASE 0x90D00000 | |
40 | /* External AHB-to-APB Bridger (FTAPBBRG020S_02) */ | |
41 | #define CONFIG_EXT_AHBAPBBRG_BASE 0x90E00000 | |
42 | /* External AHB slave1 (LCD) */ | |
43 | #define CONFIG_EXT_AHBSLAVE01_BASE 0x90F00000 | |
44 | /* External AHB slave2 (FUSBH200) */ | |
45 | #define CONFIG_EXT_AHBSLAVE02_BASE 0x92000000 | |
46 | ||
47 | /* DEBUG LED */ | |
48 | #define CONFIG_DEBUG_LED 0x902FFFFC | |
49 | ||
50 | /* APB Device definitions */ | |
51 | ||
52 | /* Power Management Unit */ | |
53 | #define CONFIG_FTPMU010_BASE 0x98100000 | |
54 | /* BT UART 2/IrDA (UART 01 in Linux) */ | |
55 | #define CONFIG_FTUART010_01_BASE 0x98300000 | |
56 | /* Counter/Timers */ | |
57 | #define CONFIG_FTTMR010_BASE 0x98400000 | |
58 | /* Watchdog Timer */ | |
59 | #define CONFIG_FTWDT010_BASE 0x98500000 | |
60 | /* Real Time Clock */ | |
61 | #define CONFIG_FTRTC010_BASE 0x98600000 | |
62 | /* GPIO */ | |
63 | #define CONFIG_FTGPIO010_BASE 0x98700000 | |
64 | /* Interrupt Controller */ | |
65 | #define CONFIG_FTINTC010_BASE 0x98800000 | |
66 | /* I2C */ | |
67 | #define CONFIG_FTIIC010_BASE 0x98A00000 | |
68 | /* Reserved */ | |
69 | #define CONFIG_RESERVED_04_BASE 0x98C00000 | |
70 | /* Compat Flash Controller */ | |
71 | #define CONFIG_FTCFC010_BASE 0x98D00000 | |
72 | /* SD Controller */ | |
73 | #define CONFIG_FTSDC010_BASE 0x98E00000 | |
74 | ||
75 | /* Synchronous Serial Port Controller (SSP) I2S/AC97 */ | |
76 | #define CONFIG_FTSSP010_02_BASE 0x99400000 | |
77 | /* ST UART ? SSP 02 (UART 02 in Linux) */ | |
78 | #define CONFIG_FTUART010_02_BASE 0x99600000 | |
79 | ||
80 | /* The following address was not defined in Linux */ | |
81 | ||
82 | /* FF UART 3 */ | |
83 | #define CONFIG_FTUART010_03_BASE 0x98200000 | |
84 | /* Synchronous Serial Port Controller (SSP) 01 */ | |
85 | #define CONFIG_FTSSP010_01_BASE 0x98B00000 | |
86 | /* IrDA */ | |
87 | #define CONFIG_IRDA_BASE 0x98900000 | |
88 | /* PWM - Pulse Width Modulator Controller */ | |
89 | #define CONFIG_PMW_BASE 0x99100000 | |
90 | ||
91 | #endif /* __AG101_H */ |