projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 1e52fea3 ML |
1 | /* |
| 2 | * Copyright (C) 2011 Andes Technology Corporation | |
| 3 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> | |
| 4 | * | |
| 1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 1e52fea3 ML |
6 | */ |
| 7 | ||
| 8 | #ifndef __AG102_H | |
| 9 | #define __AG102_H | |
| 10 | ||
| 11 | /* | |
| 12 | * Hardware register bases | |
| 13 | */ | |
| 14 | ||
| 15 | /* PCI Controller */ | |
| 16 | #define CONFIG_FTPCI100_BASE 0x90000000 | |
| 17 | /* LPC Controller */ | |
| 18 | #define CONFIG_LPC_IO_BASE 0x90100000 | |
| 19 | /* LPC Controller */ | |
| 20 | #define CONFIG_LPC_BASE 0x90200000 | |
| 21 | ||
| 22 | /* NDS32 Data Local Memory 01 */ | |
| 23 | #define CONFIG_NDS_DLM1_BASE 0x90300000 | |
| 24 | /* NDS32 Data Local Memory 02 */ | |
| 25 | #define CONFIG_NDS_DLM2_BASE 0x90400000 | |
| 26 | ||
| 27 | /* Synopsys DWC DDR2/1 Controller */ | |
| 28 | #define CONFIG_DWCDDR21MCTL_BASE 0x90500000 | |
| 29 | /* DMA Controller */ | |
| 30 | #define CONFIG_FTDMAC020_BASE 0x90600000 | |
| 31 | /* FTIDE020_S IDE (ATA) Controller */ | |
| 32 | #define CONFIG_FTIDE020S_BASE 0x90700000 | |
| 33 | /* USB OTG Controller */ | |
| 34 | #define CONFIG_FZOTG266HD0A_BASE 0x90800000 | |
| 35 | /* Andes L2 Cache Controller */ | |
| 36 | #define CONFIG_NCEL2C100_BASE 0x90900000 | |
| 37 | /* XGI XG22 GPU */ | |
| 38 | #define CONFIG_XGI_XG22_BASE 0x90A00000 | |
| 39 | /* GMAC Ethernet Controller */ | |
| 40 | #define CONFIG_FTGMAC100_BASE 0x90B00000 | |
| 41 | /* AHB Controller */ | |
| 42 | #define CONFIG_FTAHBC020S_BASE 0x90C00000 | |
| 43 | /* AHB-to-APB Bridge Controller */ | |
| 44 | #define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000 | |
| 45 | /* External AHB2AHB Controller */ | |
| 46 | #define CONFIG_EXT_AHB2AHB_BASE 0x90E00000 | |
| 47 | /* Andes Multi-core Interrupt Controller */ | |
| 48 | #define CONFIG_NCEMIC100_BASE 0x90F00000 | |
| 49 | ||
| 50 | /* | |
| 51 | * APB Device definitions | |
| 52 | */ | |
| 53 | /* Compat Flash Controller */ | |
| 54 | #define CONFIG_FTCFC010_BASE 0x94000000 | |
| 55 | /* APB - SSP (SPI) (without AC97) Controller */ | |
| 56 | #define CONFIG_FTSSP010_01_BASE 0x94100000 | |
| 57 | /* UART1 - APB STUART Controller (UART0 in Linux) */ | |
| 58 | #define CONFIG_FTUART010_01_BASE 0x94200000 | |
| 59 | /* FTSDC010 SD Controller */ | |
| 60 | #define CONFIG_FTSDC010_BASE 0x94400000 | |
| 61 | /* APB - SSP with HDA/AC97 Controller */ | |
| 62 | #define CONFIG_FTSSP010_02_BASE 0x94500000 | |
| 63 | /* UART2 - APB STUART Controller (UART1 in Linux) */ | |
| 64 | #define CONFIG_FTUART010_02_BASE 0x94600000 | |
| 65 | /* PCU Controller */ | |
| 66 | #define CONFIG_ANDES_PCU_BASE 0x94800000 | |
| 67 | /* FTTMR010 Timer */ | |
| 68 | #define CONFIG_FTTMR010_BASE 0x94900000 | |
| 69 | /* Watch Dog Controller */ | |
| 70 | #define CONFIG_FTWDT010_BASE 0x94A00000 | |
| 71 | /* FTRTC010 Real Time Clock */ | |
| 72 | #define CONFIG_FTRTC010_BASE 0x98B00000 | |
| 73 | /* GPIO Controller */ | |
| 74 | #define CONFIG_FTGPIO010_BASE 0x94C00000 | |
| 75 | /* I2C Controller */ | |
| 76 | #define CONFIG_FTIIC010_BASE 0x94E00000 | |
| 77 | /* PWM - Pulse Width Modulator Controller */ | |
| 78 | #define CONFIG_FTPWM010_BASE 0x94F00000 | |
| 79 | ||
| 80 | /* Debug LED */ | |
| 81 | #define CONFIG_DEBUG_LED 0x902FFFFC | |
| 82 | /* Power Management Unit */ | |
| 83 | #define CONFIG_FTPMU010_BASE 0x98100000 | |
| 84 | ||
| 85 | #endif /* __AG102_H */ |