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00f892fc ML |
1 | /* |
2 | * Copyright (C) 2011 Andes Technology Corporation | |
3 | * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> | |
4 | * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> | |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
00f892fc ML |
7 | */ |
8 | ||
9 | #ifndef _ASM_CACHE_H | |
10 | #define _ASM_CACHE_H | |
11 | ||
12 | /* cache */ | |
13 | int icache_status(void); | |
14 | void icache_enable(void); | |
15 | void icache_disable(void); | |
16 | int dcache_status(void); | |
17 | void dcache_enable(void); | |
18 | void dcache_disable(void); | |
19 | ||
20 | #define DEFINE_GET_SYS_REG(reg) \ | |
21 | static inline unsigned long GET_##reg(void) \ | |
22 | { \ | |
23 | unsigned long val; \ | |
24 | __asm__ volatile ( \ | |
25 | "mfsr %0, $"#reg : "=&r" (val) : : "memory" \ | |
26 | ); \ | |
27 | return val; \ | |
28 | } | |
29 | ||
30 | enum cache_t {ICACHE, DCACHE}; | |
31 | DEFINE_GET_SYS_REG(ICM_CFG); | |
32 | DEFINE_GET_SYS_REG(DCM_CFG); | |
33 | #define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ | |
34 | #define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) | |
35 | #define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ | |
36 | #define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) | |
37 | ||
466e73b1 ML |
38 | /* |
39 | * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. | |
40 | * We use that value for aligning DMA buffers unless the board config has | |
41 | * specified an alternate cache line size. | |
42 | */ | |
43 | #ifdef CONFIG_SYS_CACHELINE_SIZE | |
44 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE | |
45 | #else | |
46 | #define ARCH_DMA_MINALIGN 32 | |
47 | #endif | |
48 | ||
00f892fc | 49 | #endif /* _ASM_CACHE_H */ |