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Commit | Line | Data |
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5c952cf0 WD |
1 | /* |
2 | * (C) Copyright 2004, Psyent Corporation <www.psyent.com> | |
3 | * Scott McNutt <smcnutt@psyent.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5c952cf0 WD |
6 | */ |
7 | ||
8 | #include <config.h> | |
9 | ||
10 | .text | |
11 | ||
12 | .global flush_dcache | |
13 | ||
14 | flush_dcache: | |
15 | add r5, r5, r4 | |
6d0f6bcf JCPV |
16 | movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE) |
17 | ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE) | |
5c952cf0 WD |
18 | 0: flushd 0(r4) |
19 | add r4, r4, r8 | |
20 | bltu r4, r5, 0b | |
21 | ret | |
22 | ||
23 | ||
24 | .global flush_icache | |
25 | ||
26 | flush_icache: | |
27 | add r5, r5, r4 | |
6d0f6bcf JCPV |
28 | movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE) |
29 | ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE) | |
5c952cf0 WD |
30 | 1: flushi r4 |
31 | add r4, r4, r8 | |
32 | bltu r4, r5, 1b | |
33 | ret | |
34 | ||
8875833a SK |
35 | .global flush_dcache_range |
36 | ||
37 | flush_dcache_range: | |
38 | movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE) | |
39 | ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE) | |
40 | 0: flushd 0(r4) | |
41 | add r4, r4, r8 | |
42 | bltu r4, r5, 0b | |
43 | ret | |
44 | ||
5c952cf0 WD |
45 | .global flush_cache |
46 | ||
47 | flush_cache: | |
48 | add r5, r5, r4 | |
49 | mov r9, r4 | |
50 | mov r10, r5 | |
51 | ||
6d0f6bcf JCPV |
52 | movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE) |
53 | ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE) | |
5c952cf0 WD |
54 | 0: flushd 0(r4) |
55 | add r4, r4, r8 | |
56 | bltu r4, r5, 0b | |
57 | ||
58 | mov r4, r9 | |
59 | mov r5, r10 | |
6d0f6bcf JCPV |
60 | movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE) |
61 | ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE) | |
5c952cf0 WD |
62 | 1: flushi r4 |
63 | add r4, r4, r8 | |
64 | bltu r4, r5, 1b | |
65 | ||
66 | sync | |
67 | flushp | |
68 | ret |