[people/ms/u-boot.git] / arch / openrisc / include / asm / cache.h

/*
 * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __ASM_OPENRISC_CACHE_H_
#define __ASM_OPENRISC_CACHE_H_

/*
 * Valid L1 data cache line sizes for the OpenRISC architecture are
 * 16 and 32 bytes.
 * If the board configuration has not specified one we default to the
 * largest of these values for alignment of DMA buffers.
 */
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN       CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN       32
#endif

#endif /* __ASM_OPENRISC_CACHE_H_ */
Commit	Line	Data
ca9d3ab5 SK	1	/*
	2	* (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
ca9d3ab5 SK	5	*/
	6
	7	#ifndef __ASM_OPENRISC_CACHE_H_
	8	#define __ASM_OPENRISC_CACHE_H_
	9
	10	/*
	11	* Valid L1 data cache line sizes for the OpenRISC architecture are
	12	* 16 and 32 bytes.
	13	* If the board configuration has not specified one we default to the
	14	* largest of these values for alignment of DMA buffers.
	15	*/
	16	#ifdef CONFIG_SYS_CACHELINE_SIZE
	17	#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
	18	#else
	19	#define ARCH_DMA_MINALIGN 32
	20	#endif
	21
	22	#endif /* __ASM_OPENRISC_CACHE_H_ */