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8993e54b RJ |
1 | /* |
2 | * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. | |
843efb11 | 3 | * Copyright (C) 2007-2009 DENX Software Engineering |
8993e54b | 4 | * |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
8993e54b RJ |
6 | * |
7 | * Derived from the MPC83xx code. | |
8993e54b RJ |
8 | */ |
9 | ||
10 | #include <common.h> | |
843efb11 | 11 | #include <asm/io.h> |
b84d6d27 | 12 | #include <asm/mpc512x.h> |
843efb11 | 13 | #include <asm/processor.h> |
8993e54b RJ |
14 | |
15 | DECLARE_GLOBAL_DATA_PTR; | |
16 | ||
17 | /* | |
18 | * Set up the memory map, initialize registers, | |
19 | */ | |
20 | void cpu_init_f (volatile immap_t * im) | |
21 | { | |
22 | u32 ips_div; | |
23 | ||
24 | /* Pointer is writable since we allocated a register for it */ | |
6d0f6bcf | 25 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
8993e54b RJ |
26 | |
27 | /* Clear initial global data */ | |
28 | memset ((void *) gd, 0, sizeof (gd_t)); | |
29 | ||
b84d6d27 AG |
30 | /* Local Window and chip select configuration */ |
31 | #if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) | |
32 | out_be32(&im->sysconf.lpcs0aw, | |
33 | CSAW_START(CONFIG_SYS_CS0_START) | | |
34 | CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE)); | |
35 | sync_law(&im->sysconf.lpcs0aw); | |
36 | #endif | |
37 | #if defined(CONFIG_SYS_CS0_CFG) | |
38 | out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); | |
39 | #endif | |
40 | ||
41 | #if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) | |
42 | out_be32(&im->sysconf.lpcs1aw, | |
43 | CSAW_START(CONFIG_SYS_CS1_START) | | |
44 | CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE)); | |
45 | sync_law(&im->sysconf.lpcs1aw); | |
46 | #endif | |
47 | #if defined(CONFIG_SYS_CS1_CFG) | |
48 | out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); | |
49 | #endif | |
50 | ||
51 | #if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE) | |
52 | out_be32(&im->sysconf.lpcs2aw, | |
53 | CSAW_START(CONFIG_SYS_CS2_START) | | |
54 | CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE)); | |
55 | sync_law(&im->sysconf.lpcs2aw); | |
56 | #endif | |
57 | #if defined(CONFIG_SYS_CS2_CFG) | |
58 | out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); | |
59 | #endif | |
60 | ||
61 | #if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) | |
62 | out_be32(&im->sysconf.lpcs3aw, | |
63 | CSAW_START(CONFIG_SYS_CS3_START) | | |
64 | CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE)); | |
65 | sync_law(&im->sysconf.lpcs3aw); | |
66 | #endif | |
67 | #if defined(CONFIG_SYS_CS3_CFG) | |
68 | out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG); | |
69 | #endif | |
70 | ||
71 | #if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) | |
72 | out_be32(&im->sysconf.lpcs4aw, | |
73 | CSAW_START(CONFIG_SYS_CS4_START) | | |
74 | CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE)); | |
75 | sync_law(&im->sysconf.lpcs4aw); | |
76 | #endif | |
77 | #if defined(CONFIG_SYS_CS4_CFG) | |
78 | out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG); | |
79 | #endif | |
80 | ||
81 | #if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) | |
82 | out_be32(&im->sysconf.lpcs5aw, | |
83 | CSAW_START(CONFIG_SYS_CS5_START) | | |
84 | CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE)); | |
85 | sync_law(&im->sysconf.lpcs5aw); | |
86 | #endif | |
87 | #if defined(CONFIG_SYS_CS5_CFG) | |
88 | out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG); | |
89 | #endif | |
90 | ||
91 | #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) | |
92 | out_be32(&im->sysconf.lpcs6aw, | |
93 | CSAW_START(CONFIG_SYS_CS6_START) | | |
94 | CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE)); | |
95 | sync_law(&im->sysconf.lpcs6aw); | |
96 | #endif | |
97 | #if defined(CONFIG_SYS_CS6_CFG) | |
98 | out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG); | |
99 | #endif | |
100 | ||
101 | #if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) | |
102 | out_be32(&im->sysconf.lpcs7aw, | |
103 | CSAW_START(CONFIG_SYS_CS7_START) | | |
104 | CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE)); | |
105 | sync_law(&im->sysconf.lpcs7aw); | |
106 | #endif | |
107 | #if defined(CONFIG_SYS_CS7_CFG) | |
108 | out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG); | |
109 | #endif | |
110 | ||
111 | #if defined CONFIG_SYS_CS_ALETIMING | |
112 | if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2) | |
113 | out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); | |
114 | #endif | |
115 | #if defined CONFIG_SYS_CS_BURST | |
116 | out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST); | |
117 | #endif | |
118 | #if defined CONFIG_SYS_CS_DEADCYCLE | |
119 | out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE); | |
120 | #endif | |
121 | #if defined CONFIG_SYS_CS_HOLDCYCLE | |
122 | out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE); | |
123 | #endif | |
124 | ||
8993e54b RJ |
125 | /* system performance tweaking */ |
126 | ||
6d0f6bcf | 127 | #ifdef CONFIG_SYS_ACR_PIPE_DEP |
8993e54b | 128 | /* Arbiter pipeline depth */ |
843efb11 WD |
129 | out_be32(&im->arbiter.acr, |
130 | (im->arbiter.acr & ~ACR_PIPE_DEP) | | |
131 | (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | |
132 | ); | |
8993e54b RJ |
133 | #endif |
134 | ||
6d0f6bcf | 135 | #ifdef CONFIG_SYS_ACR_RPTCNT |
8993e54b | 136 | /* Arbiter repeat count */ |
843efb11 WD |
137 | out_be32(im->arbiter.acr, |
138 | (im->arbiter.acr & ~(ACR_RPTCNT)) | | |
139 | (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | |
140 | ); | |
8993e54b RJ |
141 | #endif |
142 | ||
143 | /* RSR - Reset Status Register - clear all status */ | |
3c4c308c | 144 | gd->arch.reset_status = im->reset.rsr; |
843efb11 | 145 | out_be32(&im->reset.rsr, ~RSR_RES); |
8993e54b RJ |
146 | |
147 | /* | |
148 | * RMR - Reset Mode Register - enable checkstop reset | |
149 | */ | |
843efb11 | 150 | out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT)); |
8993e54b RJ |
151 | |
152 | /* Set IPS-CSB divider: IPS = 1/2 CSB */ | |
843efb11 | 153 | ips_div = in_be32(&im->clk.scfr[0]); |
8993e54b RJ |
154 | ips_div &= ~(SCFR1_IPS_DIV_MASK); |
155 | ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT; | |
843efb11 | 156 | out_be32(&im->clk.scfr[0], ips_div); |
8993e54b | 157 | |
1d63b8ff AG |
158 | #ifdef SCFR1_LPC_DIV |
159 | clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK, | |
160 | SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT); | |
161 | #endif | |
162 | ||
163 | #ifdef SCFR1_NFC_DIV | |
164 | clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK, | |
165 | SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT); | |
166 | #endif | |
167 | ||
168 | #ifdef SCFR1_DIU_DIV | |
169 | clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK, | |
170 | SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT); | |
171 | #endif | |
172 | ||
8993e54b RJ |
173 | /* |
174 | * Enable Time Base/Decrementer | |
175 | * | |
176 | * NOTICE: TB needs to be enabled as early as possible in order to | |
177 | * have udelay() working; if not enabled, usually leads to a hang, like | |
b1b54e35 | 178 | * during FLASH chip identification etc. |
8993e54b | 179 | */ |
843efb11 | 180 | setbits_be32(&im->sysconf.spcr, SPCR_TBEN); |
e5f53864 AG |
181 | |
182 | /* | |
183 | * Enable clocks | |
184 | */ | |
185 | out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); | |
186 | out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); | |
83306927 | 187 | #if defined(CONFIG_FSL_IIM) || defined(CONFIG_CMD_FUSE) |
e5f53864 AG |
188 | setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); |
189 | #endif | |
8993e54b RJ |
190 | } |
191 | ||
192 | int cpu_init_r (void) | |
193 | { | |
194 | return 0; | |
195 | } |