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8993e54b RJ |
1 | /* |
2 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> | |
3 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> | |
3b74e7ec | 4 | * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de> |
4c2e3da8 | 5 | * Copyright Freescale Semiconductor, Inc. 2004, 2006. |
8993e54b RJ |
6 | * |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | * | |
25 | * Based on the MPC83xx code. | |
26 | */ | |
27 | ||
28 | /* | |
29 | * U-Boot - Startup Code for MPC512x based Embedded Boards | |
30 | */ | |
31 | ||
32 | #include <config.h> | |
561858ee | 33 | #include <timestamp.h> |
8993e54b RJ |
34 | #include <version.h> |
35 | ||
36 | #define CONFIG_521X 1 /* needed for Linux kernel header files*/ | |
37 | ||
3b74e7ec WD |
38 | #include <asm/immap_512x.h> |
39 | #include "asm-offsets.h" | |
40 | ||
8993e54b RJ |
41 | #include <ppc_asm.tmpl> |
42 | #include <ppc_defs.h> | |
43 | ||
44 | #include <asm/cache.h> | |
45 | #include <asm/mmu.h> | |
46 | ||
47 | #ifndef CONFIG_IDENT_STRING | |
48 | #define CONFIG_IDENT_STRING "MPC512X" | |
49 | #endif | |
50 | ||
51 | /* | |
52 | * Floating Point enable, Machine Check and Recoverable Interr. | |
53 | */ | |
54 | #undef MSR_KERNEL | |
55 | #ifdef DEBUG | |
56 | #define MSR_KERNEL (MSR_FP|MSR_RI) | |
57 | #else | |
58 | #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) | |
59 | #endif | |
60 | ||
61 | /* Macros for manipulating CSx_START/STOP */ | |
62 | #define START_REG(start) ((start) >> 16) | |
63 | #define STOP_REG(start, size) (((start) + (size) - 1) >> 16) | |
64 | ||
65 | /* | |
66 | * Set up GOT: Global Offset Table | |
67 | * | |
0f8aa159 | 68 | * Use r12 to access the GOT |
8993e54b RJ |
69 | */ |
70 | START_GOT | |
71 | GOT_ENTRY(_GOT2_TABLE_) | |
72 | GOT_ENTRY(_FIXUP_TABLE_) | |
73 | ||
74 | GOT_ENTRY(_start) | |
75 | GOT_ENTRY(_start_of_vectors) | |
76 | GOT_ENTRY(_end_of_vectors) | |
77 | GOT_ENTRY(transfer_to_handler) | |
78 | ||
79 | GOT_ENTRY(__init_end) | |
80 | GOT_ENTRY(_end) | |
81 | GOT_ENTRY(__bss_start) | |
82 | END_GOT | |
83 | ||
84 | /* | |
85 | * Magic number and version string | |
86 | */ | |
87 | .long 0x27051956 /* U-Boot Magic Number */ | |
88 | .globl version_string | |
89 | version_string: | |
90 | .ascii U_BOOT_VERSION | |
561858ee | 91 | .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" |
8993e54b RJ |
92 | .ascii " ", CONFIG_IDENT_STRING, "\0" |
93 | ||
94 | /* | |
95 | * Vector Table | |
96 | */ | |
97 | .text | |
98 | . = EXC_OFF_SYS_RESET | |
99 | ||
100 | .globl _start | |
101 | /* Start from here after reset/power on */ | |
102 | _start: | |
8993e54b RJ |
103 | b boot_cold |
104 | ||
105 | .globl _start_of_vectors | |
106 | _start_of_vectors: | |
107 | ||
108 | /* Machine check */ | |
109 | STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) | |
110 | ||
111 | /* Data Storage exception. */ | |
112 | STD_EXCEPTION(0x300, DataStorage, UnknownException) | |
113 | ||
114 | /* Instruction Storage exception. */ | |
115 | STD_EXCEPTION(0x400, InstStorage, UnknownException) | |
116 | ||
117 | /* External Interrupt exception. */ | |
118 | STD_EXCEPTION(0x500, ExtInterrupt, UnknownException) | |
119 | ||
120 | /* Alignment exception. */ | |
121 | . = 0x600 | |
122 | Alignment: | |
123 | EXCEPTION_PROLOG(SRR0, SRR1) | |
124 | mfspr r4,DAR | |
125 | stw r4,_DAR(r21) | |
126 | mfspr r5,DSISR | |
127 | stw r5,_DSISR(r21) | |
128 | addi r3,r1,STACK_FRAME_OVERHEAD | |
fc4e1887 | 129 | EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) |
8993e54b RJ |
130 | |
131 | /* Program check exception */ | |
132 | . = 0x700 | |
133 | ProgramCheck: | |
134 | EXCEPTION_PROLOG(SRR0, SRR1) | |
135 | addi r3,r1,STACK_FRAME_OVERHEAD | |
fc4e1887 JT |
136 | EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, |
137 | MSR_KERNEL, COPY_EE) | |
8993e54b RJ |
138 | |
139 | /* Floating Point Unit unavailable exception */ | |
140 | STD_EXCEPTION(0x800, FPUnavailable, UnknownException) | |
141 | ||
142 | /* Decrementer */ | |
143 | STD_EXCEPTION(0x900, Decrementer, timer_interrupt) | |
144 | ||
145 | /* Critical interrupt */ | |
146 | STD_EXCEPTION(0xa00, Critical, UnknownException) | |
147 | ||
148 | /* System Call */ | |
149 | STD_EXCEPTION(0xc00, SystemCall, UnknownException) | |
150 | ||
151 | /* Trace interrupt */ | |
152 | STD_EXCEPTION(0xd00, Trace, UnknownException) | |
153 | ||
154 | /* Performance Monitor interrupt */ | |
155 | STD_EXCEPTION(0xf00, PerfMon, UnknownException) | |
156 | ||
157 | /* Intruction Translation Miss */ | |
158 | STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) | |
159 | ||
160 | /* Data Load Translation Miss */ | |
161 | STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) | |
162 | ||
163 | /* Data Store Translation Miss */ | |
164 | STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) | |
165 | ||
166 | /* Instruction Address Breakpoint */ | |
167 | STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException) | |
168 | ||
169 | /* System Management interrupt */ | |
170 | STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException) | |
171 | ||
172 | .globl _end_of_vectors | |
173 | _end_of_vectors: | |
174 | ||
175 | . = 0x3000 | |
176 | boot_cold: | |
177 | /* Save msr contents */ | |
178 | mfmsr r5 | |
179 | ||
180 | /* Set IMMR area to our preferred location */ | |
181 | lis r4, CONFIG_DEFAULT_IMMR@h | |
6d0f6bcf JCPV |
182 | lis r3, CONFIG_SYS_IMMR@h |
183 | ori r3, r3, CONFIG_SYS_IMMR@l | |
8993e54b RJ |
184 | stw r3, IMMRBAR(r4) |
185 | mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ | |
186 | ||
187 | /* Initialise the machine */ | |
188 | bl cpu_early_init | |
189 | ||
190 | /* | |
191 | * Set up Local Access Windows: | |
192 | * | |
193 | * 1) Boot/CS0 (boot FLASH) | |
194 | * 2) On-chip SRAM (initial stack purposes) | |
195 | */ | |
196 | ||
197 | /* Boot CS/CS0 window range */ | |
6d0f6bcf JCPV |
198 | lis r3, CONFIG_SYS_IMMR@h |
199 | ori r3, r3, CONFIG_SYS_IMMR@l | |
8993e54b | 200 | |
6d0f6bcf JCPV |
201 | lis r4, START_REG(CONFIG_SYS_FLASH_BASE) |
202 | ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE) | |
8993e54b RJ |
203 | stw r4, LPCS0AW(r3) |
204 | ||
205 | /* | |
206 | * The SRAM window has a fixed size (256K), so only the start address | |
207 | * is necessary | |
208 | */ | |
6d0f6bcf | 209 | lis r4, START_REG(CONFIG_SYS_SRAM_BASE) & 0xff00 |
8993e54b RJ |
210 | stw r4, SRAMBAR(r3) |
211 | ||
b1b54e35 | 212 | /* |
8993e54b | 213 | * According to MPC5121e RM, configuring local access windows should |
b1b54e35 | 214 | * be followed by a dummy read of the config register that was |
8993e54b | 215 | * modified last and an isync |
b1b54e35 | 216 | */ |
8993e54b RJ |
217 | lwz r4, SRAMBAR(r3) |
218 | isync | |
219 | ||
220 | /* | |
221 | * Set configuration of the Boot/CS0, the SRAM window does not have a | |
222 | * config register so no params can be set for it | |
223 | */ | |
6d0f6bcf JCPV |
224 | lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h |
225 | ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l | |
8993e54b | 226 | |
6d0f6bcf JCPV |
227 | lis r4, CONFIG_SYS_CS0_CFG@h |
228 | ori r4, r4, CONFIG_SYS_CS0_CFG@l | |
b1b54e35 | 229 | stw r4, CS0_CONFIG(r3) |
8993e54b RJ |
230 | |
231 | /* Master enable all CS's */ | |
232 | lis r4, CS_CTRL_ME@h | |
233 | ori r4, r4, CS_CTRL_ME@l | |
234 | stw r4, CS_CTRL(r3) | |
235 | ||
6d0f6bcf JCPV |
236 | lis r4, (CONFIG_SYS_MONITOR_BASE)@h |
237 | ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l | |
8993e54b RJ |
238 | addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET |
239 | mtlr r5 | |
240 | blr | |
241 | ||
242 | in_flash: | |
6d0f6bcf JCPV |
243 | lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h |
244 | ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l | |
8993e54b RJ |
245 | |
246 | li r0, 0 /* Make room for stack frame header and */ | |
247 | stwu r0, -4(r1) /* clear final stack frame so that */ | |
248 | stwu r0, -4(r1) /* stack backtraces terminate cleanly */ | |
249 | ||
250 | /* let the C-code set up the rest */ | |
251 | /* */ | |
252 | /* Be careful to keep code relocatable & stack humble */ | |
253 | /*------------------------------------------------------*/ | |
254 | ||
255 | GET_GOT /* initialize GOT access */ | |
256 | ||
257 | /* r3: IMMR */ | |
6d0f6bcf | 258 | lis r3, CONFIG_SYS_IMMR@h |
8993e54b RJ |
259 | /* run low-level CPU init code (in Flash) */ |
260 | bl cpu_init_f | |
261 | ||
8993e54b RJ |
262 | /* run 1st part of board init code (in Flash) */ |
263 | bl board_init_f | |
264 | ||
265 | /* NOTREACHED - board_init_f() does not return */ | |
266 | ||
267 | /* | |
268 | * This code finishes saving the registers to the exception frame | |
269 | * and jumps to the appropriate handler for the exception. | |
270 | * Register r21 is pointer into trap frame, r1 has new stack pointer. | |
271 | */ | |
272 | .globl transfer_to_handler | |
273 | transfer_to_handler: | |
274 | stw r22,_NIP(r21) | |
275 | lis r22,MSR_POW@h | |
276 | andc r23,r23,r22 | |
277 | stw r23,_MSR(r21) | |
278 | SAVE_GPR(7, r21) | |
279 | SAVE_4GPRS(8, r21) | |
280 | SAVE_8GPRS(12, r21) | |
281 | SAVE_8GPRS(24, r21) | |
282 | mflr r23 | |
283 | andi. r24,r23,0x3f00 /* get vector offset */ | |
284 | stw r24,TRAP(r21) | |
285 | li r22,0 | |
286 | stw r22,RESULT(r21) | |
287 | lwz r24,0(r23) /* virtual address of handler */ | |
288 | lwz r23,4(r23) /* where to go when done */ | |
289 | mtspr SRR0,r24 | |
290 | mtspr SRR1,r20 | |
291 | mtlr r23 | |
292 | SYNC | |
293 | rfi /* jump to handler, enable MMU */ | |
294 | ||
295 | int_return: | |
296 | mfmsr r28 /* Disable interrupts */ | |
297 | li r4,0 | |
298 | ori r4,r4,MSR_EE | |
299 | andc r28,r28,r4 | |
300 | SYNC /* Some chip revs need this... */ | |
301 | mtmsr r28 | |
302 | SYNC | |
303 | lwz r2,_CTR(r1) | |
304 | lwz r0,_LINK(r1) | |
305 | mtctr r2 | |
306 | mtlr r0 | |
307 | lwz r2,_XER(r1) | |
308 | lwz r0,_CCR(r1) | |
309 | mtspr XER,r2 | |
310 | mtcrf 0xFF,r0 | |
311 | REST_10GPRS(3, r1) | |
312 | REST_10GPRS(13, r1) | |
313 | REST_8GPRS(23, r1) | |
314 | REST_GPR(31, r1) | |
315 | lwz r2,_NIP(r1) /* Restore environment */ | |
316 | lwz r0,_MSR(r1) | |
317 | mtspr SRR0,r2 | |
318 | mtspr SRR1,r0 | |
319 | lwz r0,GPR0(r1) | |
320 | lwz r2,GPR2(r1) | |
321 | lwz r1,GPR1(r1) | |
322 | SYNC | |
323 | rfi | |
324 | ||
325 | /* | |
326 | * This code initialises the machine, it expects original MSR contents to be in r5. | |
327 | */ | |
328 | cpu_early_init: | |
329 | /* Initialize machine status; enable machine check interrupt */ | |
330 | /*-----------------------------------------------------------*/ | |
331 | ||
332 | li r3, MSR_KERNEL /* Set ME and RI flags */ | |
333 | rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */ | |
334 | #ifdef DEBUG | |
335 | rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */ | |
336 | #endif | |
337 | mtmsr r3 | |
338 | SYNC | |
339 | mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */ | |
340 | ||
6d0f6bcf | 341 | lis r3, CONFIG_SYS_IMMR@h |
8993e54b RJ |
342 | |
343 | #if defined(CONFIG_WATCHDOG) | |
344 | /* Initialise the watchdog and reset it */ | |
345 | /*--------------------------------------*/ | |
6d0f6bcf | 346 | lis r4, CONFIG_SYS_WATCHDOG_VALUE |
8993e54b RJ |
347 | ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) |
348 | stw r4, SWCRR(r3) | |
349 | ||
350 | /* reset */ | |
351 | li r4, 0x556C | |
352 | sth r4, SWSRR@l(r3) | |
353 | li r4, 0x0 | |
354 | ori r4, r4, 0xAA39 | |
355 | sth r4, SWSRR@l(r3) | |
356 | #else | |
357 | /* Disable the watchdog */ | |
358 | /*----------------------*/ | |
359 | lwz r4, SWCRR(r3) | |
360 | /* | |
361 | * Check to see if it's enabled for disabling: once disabled by s/w | |
362 | * it's not possible to re-enable it | |
363 | */ | |
364 | andi. r4, r4, 0x4 | |
365 | beq 1f | |
366 | xor r4, r4, r4 | |
367 | stw r4, SWCRR(r3) | |
368 | 1: | |
369 | #endif /* CONFIG_WATCHDOG */ | |
370 | ||
371 | /* Initialize the Hardware Implementation-dependent Registers */ | |
372 | /* HID0 also contains cache control */ | |
373 | /*------------------------------------------------------*/ | |
6d0f6bcf JCPV |
374 | lis r3, CONFIG_SYS_HID0_INIT@h |
375 | ori r3, r3, CONFIG_SYS_HID0_INIT@l | |
8993e54b RJ |
376 | SYNC |
377 | mtspr HID0, r3 | |
378 | ||
6d0f6bcf JCPV |
379 | lis r3, CONFIG_SYS_HID0_FINAL@h |
380 | ori r3, r3, CONFIG_SYS_HID0_FINAL@l | |
8993e54b RJ |
381 | SYNC |
382 | mtspr HID0, r3 | |
383 | ||
6d0f6bcf JCPV |
384 | lis r3, CONFIG_SYS_HID2@h |
385 | ori r3, r3, CONFIG_SYS_HID2@l | |
8993e54b RJ |
386 | SYNC |
387 | mtspr HID2, r3 | |
388 | sync | |
389 | blr | |
390 | ||
391 | ||
392 | /* Cache functions. | |
393 | * | |
394 | * Note: requires that all cache bits in | |
395 | * HID0 are in the low half word. | |
396 | */ | |
397 | .globl icache_enable | |
398 | icache_enable: | |
399 | mfspr r3, HID0 | |
400 | ori r3, r3, HID0_ICE | |
401 | lis r4, 0 | |
402 | ori r4, r4, HID0_ILOCK | |
403 | andc r3, r3, r4 | |
404 | ori r4, r3, HID0_ICFI | |
405 | isync | |
406 | mtspr HID0, r4 /* sets enable and invalidate, clears lock */ | |
407 | isync | |
408 | mtspr HID0, r3 /* clears invalidate */ | |
409 | blr | |
410 | ||
411 | .globl icache_disable | |
412 | icache_disable: | |
413 | mfspr r3, HID0 | |
414 | lis r4, 0 | |
415 | ori r4, r4, HID0_ICE|HID0_ILOCK | |
416 | andc r3, r3, r4 | |
417 | ori r4, r3, HID0_ICFI | |
418 | isync | |
419 | mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ | |
420 | isync | |
421 | mtspr HID0, r3 /* clears invalidate */ | |
422 | blr | |
423 | ||
424 | .globl icache_status | |
425 | icache_status: | |
426 | mfspr r3, HID0 | |
427 | rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 | |
428 | blr | |
429 | ||
430 | .globl dcache_enable | |
431 | dcache_enable: | |
432 | mfspr r3, HID0 | |
433 | li r5, HID0_DCFI|HID0_DLOCK | |
434 | andc r3, r3, r5 | |
435 | mtspr HID0, r3 /* no invalidate, unlock */ | |
436 | ori r3, r3, HID0_DCE | |
437 | ori r5, r3, HID0_DCFI | |
438 | mtspr HID0, r5 /* enable + invalidate */ | |
439 | mtspr HID0, r3 /* enable */ | |
440 | sync | |
441 | blr | |
442 | ||
443 | .globl dcache_disable | |
444 | dcache_disable: | |
445 | mfspr r3, HID0 | |
446 | lis r4, 0 | |
447 | ori r4, r4, HID0_DCE|HID0_DLOCK | |
448 | andc r3, r3, r4 | |
449 | ori r4, r3, HID0_DCI | |
450 | sync | |
451 | mtspr HID0, r4 /* sets invalidate, clears enable and lock */ | |
452 | sync | |
453 | mtspr HID0, r3 /* clears invalidate */ | |
454 | blr | |
455 | ||
456 | .globl dcache_status | |
457 | dcache_status: | |
458 | mfspr r3, HID0 | |
459 | rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 | |
460 | blr | |
461 | ||
462 | .globl get_pvr | |
463 | get_pvr: | |
464 | mfspr r3, PVR | |
465 | blr | |
466 | ||
8993e54b RJ |
467 | /*-------------------------------------------------------------------*/ |
468 | ||
469 | /* | |
470 | * void relocate_code (addr_sp, gd, addr_moni) | |
471 | * | |
472 | * This "function" does not return, instead it continues in RAM | |
473 | * after relocating the monitor code. | |
474 | * | |
475 | * r3 = dest | |
476 | * r4 = src | |
477 | * r5 = length in bytes | |
478 | * r6 = cachelinesize | |
479 | */ | |
480 | .globl relocate_code | |
481 | relocate_code: | |
482 | mr r1, r3 /* Set new stack pointer */ | |
483 | mr r9, r4 /* Save copy of Global Data pointer */ | |
484 | mr r10, r5 /* Save copy of Destination Address */ | |
485 | ||
0f8aa159 | 486 | GET_GOT |
8993e54b | 487 | mr r3, r5 /* Destination Address */ |
6d0f6bcf JCPV |
488 | lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ |
489 | ori r4, r4, CONFIG_SYS_MONITOR_BASE@l | |
8993e54b RJ |
490 | lwz r5, GOT(__init_end) |
491 | sub r5, r5, r4 | |
6d0f6bcf | 492 | li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ |
8993e54b RJ |
493 | |
494 | /* | |
495 | * Fix GOT pointer: | |
496 | * | |
6d0f6bcf | 497 | * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) |
8993e54b RJ |
498 | * + Destination Address |
499 | * | |
500 | * Offset: | |
501 | */ | |
502 | sub r15, r10, r4 | |
503 | ||
504 | /* First our own GOT */ | |
0f8aa159 | 505 | add r12, r12, r15 |
8993e54b RJ |
506 | /* then the one used by the C code */ |
507 | add r30, r30, r15 | |
508 | ||
509 | /* | |
510 | * Now relocate code | |
511 | */ | |
512 | cmplw cr1,r3,r4 | |
513 | addi r0,r5,3 | |
514 | srwi. r0,r0,2 | |
515 | beq cr1,4f /* In place copy is not necessary */ | |
516 | beq 7f /* Protect against 0 count */ | |
517 | mtctr r0 | |
518 | bge cr1,2f | |
519 | la r8,-4(r4) | |
520 | la r7,-4(r3) | |
521 | ||
522 | /* copy */ | |
523 | 1: lwzu r0,4(r8) | |
524 | stwu r0,4(r7) | |
525 | bdnz 1b | |
526 | ||
527 | addi r0,r5,3 | |
528 | srwi. r0,r0,2 | |
529 | mtctr r0 | |
530 | la r8,-4(r4) | |
531 | la r7,-4(r3) | |
532 | ||
533 | /* and compare */ | |
534 | 20: lwzu r20,4(r8) | |
535 | lwzu r21,4(r7) | |
536 | xor. r22, r20, r21 | |
537 | bne 30f | |
538 | bdnz 20b | |
539 | b 4f | |
540 | ||
541 | /* compare failed */ | |
542 | 30: li r3, 0 | |
543 | blr | |
544 | ||
545 | 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ | |
546 | add r8,r4,r0 | |
547 | add r7,r3,r0 | |
548 | 3: lwzu r0,-4(r8) | |
549 | stwu r0,-4(r7) | |
550 | bdnz 3b | |
551 | ||
552 | /* | |
553 | * Now flush the cache: note that we must start from a cache aligned | |
554 | * address. Otherwise we might miss one cache line. | |
555 | */ | |
556 | 4: cmpwi r6,0 | |
557 | add r5,r3,r5 | |
558 | beq 7f /* Always flush prefetch queue in any case */ | |
559 | subi r0,r6,1 | |
560 | andc r3,r3,r0 | |
561 | mr r4,r3 | |
562 | 5: dcbst 0,r4 | |
563 | add r4,r4,r6 | |
564 | cmplw r4,r5 | |
565 | blt 5b | |
566 | sync /* Wait for all dcbst to complete on bus */ | |
567 | mr r4,r3 | |
568 | 6: icbi 0,r4 | |
569 | add r4,r4,r6 | |
570 | cmplw r4,r5 | |
571 | blt 6b | |
572 | 7: sync /* Wait for all icbi to complete on bus */ | |
573 | isync | |
574 | ||
575 | /* | |
576 | * We are done. Do not return, instead branch to second part of board | |
577 | * initialization, now running from RAM. | |
578 | */ | |
579 | addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET | |
580 | mtlr r0 | |
581 | blr | |
582 | ||
583 | in_ram: | |
584 | /* | |
0f8aa159 | 585 | * Relocation Function, r12 point to got2+0x8000 |
8993e54b RJ |
586 | * |
587 | * Adjust got2 pointers, no need to check for 0, this code | |
588 | * already puts a few entries in the table. | |
589 | */ | |
590 | li r0,__got2_entries@sectoff@l | |
591 | la r3,GOT(_GOT2_TABLE_) | |
592 | lwz r11,GOT(_GOT2_TABLE_) | |
593 | mtctr r0 | |
594 | sub r11,r3,r11 | |
595 | addi r3,r3,-4 | |
596 | 1: lwzu r0,4(r3) | |
afc3ba0f JT |
597 | cmpwi r0,0 |
598 | beq- 2f | |
8993e54b RJ |
599 | add r0,r0,r11 |
600 | stw r0,0(r3) | |
afc3ba0f | 601 | 2: bdnz 1b |
8993e54b RJ |
602 | |
603 | /* | |
604 | * Now adjust the fixups and the pointers to the fixups | |
605 | * in case we need to move ourselves again. | |
606 | */ | |
afc3ba0f | 607 | li r0,__fixup_entries@sectoff@l |
8993e54b RJ |
608 | lwz r3,GOT(_FIXUP_TABLE_) |
609 | cmpwi r0,0 | |
610 | mtctr r0 | |
611 | addi r3,r3,-4 | |
612 | beq 4f | |
613 | 3: lwzu r4,4(r3) | |
614 | lwzux r0,r4,r11 | |
615 | add r0,r0,r11 | |
616 | stw r10,0(r3) | |
617 | stw r0,0(r4) | |
618 | bdnz 3b | |
619 | 4: | |
620 | clear_bss: | |
621 | /* | |
622 | * Now clear BSS segment | |
623 | */ | |
624 | lwz r3,GOT(__bss_start) | |
625 | lwz r4,GOT(_end) | |
626 | ||
627 | cmplw 0, r3, r4 | |
628 | beq 6f | |
629 | ||
630 | li r0, 0 | |
631 | 5: | |
632 | stw r0, 0(r3) | |
633 | addi r3, r3, 4 | |
634 | cmplw 0, r3, r4 | |
635 | bne 5b | |
636 | 6: | |
637 | mr r3, r9 /* Global Data pointer */ | |
638 | mr r4, r10 /* Destination Address */ | |
639 | bl board_init_r | |
640 | ||
641 | /* | |
642 | * Copy exception vector code to low memory | |
643 | * | |
644 | * r3: dest_addr | |
645 | * r7: source address, r8: end address, r9: target address | |
646 | */ | |
647 | .globl trap_init | |
648 | trap_init: | |
0f8aa159 JT |
649 | mflr r4 /* save link register */ |
650 | GET_GOT | |
8993e54b RJ |
651 | lwz r7, GOT(_start) |
652 | lwz r8, GOT(_end_of_vectors) | |
653 | ||
654 | li r9, 0x100 /* reset vector at 0x100 */ | |
655 | ||
656 | cmplw 0, r7, r8 | |
657 | bgelr /* return if r7>=r8 - just in case */ | |
8993e54b RJ |
658 | 1: |
659 | lwz r0, 0(r7) | |
660 | stw r0, 0(r9) | |
661 | addi r7, r7, 4 | |
662 | addi r9, r9, 4 | |
663 | cmplw 0, r7, r8 | |
664 | bne 1b | |
665 | ||
666 | /* | |
667 | * relocate `hdlr' and `int_return' entries | |
668 | */ | |
669 | li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET | |
670 | li r8, Alignment - _start + EXC_OFF_SYS_RESET | |
671 | 2: | |
672 | bl trap_reloc | |
673 | addi r7, r7, 0x100 /* next exception vector */ | |
674 | cmplw 0, r7, r8 | |
675 | blt 2b | |
676 | ||
677 | li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET | |
678 | bl trap_reloc | |
679 | ||
680 | li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET | |
681 | bl trap_reloc | |
682 | ||
683 | li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET | |
684 | li r8, SystemCall - _start + EXC_OFF_SYS_RESET | |
685 | 3: | |
686 | bl trap_reloc | |
687 | addi r7, r7, 0x100 /* next exception vector */ | |
688 | cmplw 0, r7, r8 | |
689 | blt 3b | |
690 | ||
691 | li r7, .L_Trace - _start + EXC_OFF_SYS_RESET | |
692 | li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET | |
693 | 4: | |
694 | bl trap_reloc | |
695 | addi r7, r7, 0x100 /* next exception vector */ | |
696 | cmplw 0, r7, r8 | |
697 | blt 4b | |
698 | ||
699 | mfmsr r3 /* now that the vectors have */ | |
700 | lis r7, MSR_IP@h /* relocated into low memory */ | |
701 | ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ | |
702 | andc r3, r3, r7 /* (if it was on) */ | |
703 | SYNC /* Some chip revs need this... */ | |
704 | mtmsr r3 | |
705 | SYNC | |
706 | ||
707 | mtlr r4 /* restore link register */ | |
708 | blr |