[people/ms/u-boot.git] / arch / powerpc / cpu / mpc5xxx / pci_mpc5200.c

/*
 * (C) Copyright 2000-2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

#if defined(CONFIG_PCI)

#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>
#include <mpc5xxx.h>

/* System RAM mapped over PCI */
#define CONFIG_PCI_MEMORY_BUS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_MEMORY_PHYS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_MEMORY_SIZE	(1024 * 1024 * 1024)

/* PCIIWCR bit fields */
#define IWCR_MEM	(0 << 3)
#define IWCR_IO		(1 << 3)
#define IWCR_READ	(0 << 1)
#define IWCR_READLINE	(1 << 1)
#define IWCR_READMULT	(2 << 1)
#define IWCR_EN		(1 << 0)

static int mpc5200_read_config_dword(struct pci_controller *hose,
			      pci_dev_t dev, int offset, u32* value)
{
	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
	eieio();
	udelay(10);
#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
	if (dev & 0x00ff0000) {
		u32 val;
		val  = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
		udelay(10);
		val = val << 16;
		val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
		*value = val;
	} else {
		*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
	}
	udelay(10);
#else
	*value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
#endif
	eieio();
	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
	udelay(10);
	return 0;
}

static int mpc5200_write_config_dword(struct pci_controller *hose,
			      pci_dev_t dev, int offset, u32 value)
{
	*(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
	eieio();
	udelay(10);
	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
	eieio();
	*(volatile u32 *)MPC5XXX_PCI_CAR = 0;
	udelay(10);
	return 0;
}

void pci_mpc5xxx_init (struct pci_controller *hose)
{
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* System space */
	pci_set_region(hose->regions + 0,
		       CONFIG_PCI_MEMORY_BUS,
		       CONFIG_PCI_MEMORY_PHYS,
		       CONFIG_PCI_MEMORY_SIZE,
		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);

	/* PCI memory space */
	pci_set_region(hose->regions + 1,
		       CONFIG_PCI_MEM_BUS,
		       CONFIG_PCI_MEM_PHYS,
		       CONFIG_PCI_MEM_SIZE,
		       PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose->regions + 2,
		       CONFIG_PCI_IO_BUS,
		       CONFIG_PCI_IO_PHYS,
		       CONFIG_PCI_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 3;

	pci_register_hose(hose);

	/* GPIO Multiplexing - enable PCI */
	*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);

	/* Set host bridge as pci master and enable memory decoding */
	*(vu_long *)MPC5XXX_PCI_CMD |=
		PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;

	/* Set maximum latency timer */
	*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);

	/* Set cache line size */
	*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
		(CONFIG_SYS_CACHELINE_SIZE / 4);

	/* Map MBAR to PCI space */
	*(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
	*(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;

	/* Map RAM to PCI space */
	*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
	*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;

	/* Park XLB on PCI */
	*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
	*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);

	/* Disable interrupts from PCI controller */
	*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
	*(vu_long *)MPC5XXX_PCI_ICR  &= ~(7 << 24);

	/* Set PCI retry counter to 0 = infinite retry. */
	/* The default of 255 is too short for slow devices. */
	*(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00;

	/* Disable initiator windows */
	*(vu_long *)MPC5XXX_PCI_IWCR = 0;

	/* Map PCI memory to physical space */
	*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
		(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
		(CONFIG_PCI_MEM_BUS >> 16);
	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;

	/* Map PCI I/O to physical space */
	*(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
		(((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
		(CONFIG_PCI_IO_BUS >> 16);
	*(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;

	/* Reset the PCI bus */
	*(vu_long *)MPC5XXX_PCI_GSCR |= 1;
	udelay(1000);
	*(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
	udelay(1000);

	pci_set_ops(hose,
		pci_hose_read_config_byte_via_dword,
		pci_hose_read_config_word_via_dword,
		mpc5200_read_config_dword,
		pci_hose_write_config_byte_via_dword,
		pci_hose_write_config_word_via_dword,
		mpc5200_write_config_dword);

	udelay(1000);

#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif

	hose->last_busno = pci_hose_scan(hose);
}
#endif /* CONFIG_PCI */
Commit	Line	Data
96e48cf6 WD	1	/*
	2	* (C) Copyright 2000-2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
96e48cf6 WD	6	*/
	7
	8	#include <common.h>
	9
fd428c05	10	#if defined(CONFIG_PCI)
96e48cf6 WD	11
	12	#include <asm/processor.h>
	13	#include <asm/io.h>
	14	#include <pci.h>
	15	#include <mpc5xxx.h>
	16
	17	/* System RAM mapped over PCI */
6d0f6bcf JCPV	18	#define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
6d0f6bcf JCPV	19	#define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
96e48cf6 WD	20	#define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
	21
	22	/* PCIIWCR bit fields */
	23	#define IWCR_MEM (0 << 3)
	24	#define IWCR_IO (1 << 3)
	25	#define IWCR_READ (0 << 1)
	26	#define IWCR_READLINE (1 << 1)
	27	#define IWCR_READMULT (2 << 1)
	28	#define IWCR_EN (1 << 0)
	29
	30	static int mpc5200_read_config_dword(struct pci_controller *hose,
	31	pci_dev_t dev, int offset, u32* value)
	32	{
	33	(volatile u32 )MPC5XXX_PCI_CAR = (1 << 31) \| dev \| offset;
	34	eieio();
35656de7	35	udelay(10);
5e4b3361 SR	36	#if (defined CONFIG_PF5200 \|\| defined CONFIG_CPCI5200)
	37	if (dev & 0x00ff0000) {
	38	u32 val;
	39	val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
	40	udelay(10);
	41	val = val << 16;
	42	val \|= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
	43	*value = val;
	44	} else {
	45	value = in_le32((volatile u32 )CONFIG_PCI_IO_PHYS);
	46	}
	47	udelay(10);
	48	#else
96e48cf6	49	value = in_le32((volatile u32 )CONFIG_PCI_IO_PHYS);
5e4b3361	50	#endif
96e48cf6 WD	51	eieio();
96e48cf6 WD	52	(volatile u32 )MPC5XXX_PCI_CAR = 0;
35656de7	53	udelay(10);
96e48cf6 WD	54	return 0;
	55	}
	56
	57	static int mpc5200_write_config_dword(struct pci_controller *hose,
	58	pci_dev_t dev, int offset, u32 value)
	59	{
	60	(volatile u32 )MPC5XXX_PCI_CAR = (1 << 31) \| dev \| offset;
	61	eieio();
35656de7	62	udelay(10);
96e48cf6 WD	63	out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
	64	eieio();
	65	(volatile u32 )MPC5XXX_PCI_CAR = 0;
35656de7	66	udelay(10);
96e48cf6 WD	67	return 0;
	68	}
	69
	70	void pci_mpc5xxx_init (struct pci_controller *hose)
	71	{
	72	hose->first_busno = 0;
	73	hose->last_busno = 0xff;
	74
	75	/* System space */
	76	pci_set_region(hose->regions + 0,
	77	CONFIG_PCI_MEMORY_BUS,
	78	CONFIG_PCI_MEMORY_PHYS,
	79	CONFIG_PCI_MEMORY_SIZE,
ff4e66e9	80	PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY);
96e48cf6 WD	81
	82	/* PCI memory space */
	83	pci_set_region(hose->regions + 1,
	84	CONFIG_PCI_MEM_BUS,
	85	CONFIG_PCI_MEM_PHYS,
	86	CONFIG_PCI_MEM_SIZE,
	87	PCI_REGION_MEM);
	88
	89	/* PCI IO space */
	90	pci_set_region(hose->regions + 2,
	91	CONFIG_PCI_IO_BUS,
	92	CONFIG_PCI_IO_PHYS,
	93	CONFIG_PCI_IO_SIZE,
	94	PCI_REGION_IO);
	95
	96	hose->region_count = 3;
	97
	98	pci_register_hose(hose);
	99
	100	/* GPIO Multiplexing - enable PCI */
	101	(vu_long )MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
42d1f039	102
96e48cf6 WD	103	/* Set host bridge as pci master and enable memory decoding */
	104	(vu_long )MPC5XXX_PCI_CMD \|=
	105	PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
42d1f039	106
96e48cf6 WD	107	/* Set maximum latency timer */
	108	(vu_long )MPC5XXX_PCI_CFG \|= (0xf800);
	109
	110	/* Set cache line size */
	111	(vu_long )MPC5XXX_PCI_CFG = ((vu_long )MPC5XXX_PCI_CFG & ~0xff) \|
6d0f6bcf	112	(CONFIG_SYS_CACHELINE_SIZE / 4);
42d1f039	113
96e48cf6	114	/* Map MBAR to PCI space */
6d0f6bcf JCPV	115	(vu_long )MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
6d0f6bcf JCPV	116	(vu_long )MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR \| 1;
42d1f039	117
96e48cf6 WD	118	/* Map RAM to PCI space */
	119	(vu_long )MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS \| (1 << 3);
	120	(vu_long )MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS \| 1;
	121
96e48cf6 WD	122	/* Park XLB on PCI */
	123	(vu_long )(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) \| (3 << 5));
	124	(vu_long )(MPC5XXX_XLBARB + 0x40) \|= (3 << 8) \| (3 << 5);
	125
96e48cf6 WD	126	/* Disable interrupts from PCI controller */
96e48cf6 WD	127	(vu_long )MPC5XXX_PCI_GSCR &= ~(7 << 12);
a9e642e2 WD	128	(vu_long )MPC5XXX_PCI_ICR &= ~(7 << 24);
	129
	130	/* Set PCI retry counter to 0 = infinite retry. */
	131	/* The default of 255 is too short for slow devices. */
	132	(vu_long )MPC5XXX_PCI_ICR &= 0xFFFFFF00;
42d1f039	133
96e48cf6 WD	134	/* Disable initiator windows */
96e48cf6 WD	135	(vu_long )MPC5XXX_PCI_IWCR = 0;
42d1f039	136
96e48cf6 WD	137	/* Map PCI memory to physical space */
	138	(vu_long )MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS \|
	139	(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) \|
	140	(CONFIG_PCI_MEM_BUS >> 16);
	141	(vu_long )MPC5XXX_PCI_IWCR \|= (IWCR_MEM \| IWCR_READ \| IWCR_EN) << 24;
	142
	143	/* Map PCI I/O to physical space */
	144	(vu_long )MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS \|
	145	(((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) \|
	146	(CONFIG_PCI_IO_BUS >> 16);
	147	(vu_long )MPC5XXX_PCI_IWCR \|= (IWCR_IO \| IWCR_READ \| IWCR_EN) << 16;
	148
	149	/* Reset the PCI bus */
	150	(vu_long )MPC5XXX_PCI_GSCR \|= 1;
	151	udelay(1000);
	152	(vu_long )MPC5XXX_PCI_GSCR &= ~1;
	153	udelay(1000);
	154
	155	pci_set_ops(hose,
	156	pci_hose_read_config_byte_via_dword,
	157	pci_hose_read_config_word_via_dword,
	158	mpc5200_read_config_dword,
	159	pci_hose_write_config_byte_via_dword,
	160	pci_hose_write_config_word_via_dword,
	161	mpc5200_write_config_dword);
42d1f039	162
96e48cf6 WD	163	udelay(1000);
	164
	165	#ifdef CONFIG_PCI_SCAN_SHOW
	166	printf("PCI: Bus Dev VenId DevId Class Int\n");
	167	#endif
	168
	169	hose->last_busno = pci_hose_scan(hose);
	170	}
fd428c05	171	#endif /* CONFIG_PCI */