[people/ms/u-boot.git] / arch / powerpc / cpu / mpc824x / cpu_init.c

/*
 * (C) Copyright 2000
 * Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <mpc824x.h>

#ifndef CONFIG_SYS_BANK0_ROW
#define CONFIG_SYS_BANK0_ROW 0
#endif
#ifndef CONFIG_SYS_BANK1_ROW
#define CONFIG_SYS_BANK1_ROW 0
#endif
#ifndef CONFIG_SYS_BANK2_ROW
#define CONFIG_SYS_BANK2_ROW 0
#endif
#ifndef CONFIG_SYS_BANK3_ROW
#define CONFIG_SYS_BANK3_ROW 0
#endif
#ifndef CONFIG_SYS_BANK4_ROW
#define CONFIG_SYS_BANK4_ROW 0
#endif
#ifndef CONFIG_SYS_BANK5_ROW
#define CONFIG_SYS_BANK5_ROW 0
#endif
#ifndef CONFIG_SYS_BANK6_ROW
#define CONFIG_SYS_BANK6_ROW 0
#endif
#ifndef CONFIG_SYS_BANK7_ROW
#define CONFIG_SYS_BANK7_ROW 0
#endif
#ifndef CONFIG_SYS_DBUS_SIZE2
#define CONFIG_SYS_DBUS_SIZE2 0
#endif

/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 */
void
cpu_init_f (void)
{
    register unsigned long val;
    CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/

#if defined(CONFIG_MUSENKI)
/* Why is this here, you ask?  Try, just try setting 0x8000
 * in PCIACR with CONFIG_WRITE_HALFWORD()
 * this one was a stumper, and we are annoyed
 */

#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
	__asm__ __volatile__("		\
		stw  %2,0(%0)\n		\
		sync\n			\
		sth  %3,2(%1)\n		\
		sync\n			\
		"			\
		: /* no output */	\
		: "r" (CONFIG_ADDR), "r" (CONFIG_DATA),			\
		"r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16))	\
	);

	M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
#endif

	CONFIG_WRITE_BYTE(PCLSR, 0x8);	/* set PCI cache line size */
	CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
	/*
	* Note that although this bit is cleared after a hard reset, it
	* must be explicitly set and then cleared by software during
	* initialization in order to guarantee correct operation of the
	* DLL and the SDRAM_CLK[0:3] signals (if they are used).
	*/
	CONFIG_READ_BYTE (AMBOR, val);
	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
	CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
#ifdef CONFIG_MPC8245
	/* silicon bug 28 MPC8245 */
	CONFIG_READ_BYTE(AMBOR,val);
	CONFIG_WRITE_BYTE(AMBOR,val|0x1);

#if 0
	/*
	 * The following bug only affects older (XPC8245) processors.
	 * DMA transfers initiated by external devices get corrupted due
	 * to a hardware scheduling problem.
	 *
	 * The effect is:
	 * when transferring X words, the first 32 words are transferred
	 * OK, the next 3 x 32 words are 'old' data (from previous DMA)
	 * while the rest of the X words is xferred fine.
	 *
	 * Disabling 3 of the 4 32 word hardware buffers solves the problem
	 * with no significant performance loss.
	 */

	CONFIG_READ_BYTE(PCMBCR,val);
	/* in order not to corrupt data which is being read over the PCI bus
	* with the PPC as slave, we need to reduce the number of PCMRBs to 1,
	* 4.11 in the  processor user manual
	* */

#if 1
	CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
#else
	CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
	CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
	/* default, 4 PCMRBs are used */
#endif
#endif
#endif

	CONFIG_READ_WORD(PICR1, val);
#if defined(CONFIG_MPC8240)
	CONFIG_WRITE_WORD( PICR1,
		(val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
		       PIRC1_MSK | PICR1_PROC_TYPE_603E |
		       PICR1_FLASH_WR_EN | PICR1_MCP_EN |
		       PICR1_CF_DPARK | PICR1_EN_PCS |
		       PICR1_CF_APARK );
#elif defined(CONFIG_MPC8245)
	CONFIG_WRITE_WORD( PICR1,
		(val & (PICR1_RCS0)) |
		       PICR1_PROC_TYPE_603E |
		       PICR1_FLASH_WR_EN | PICR1_MCP_EN |
		       PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
		       PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

	CONFIG_READ_WORD(PICR2, val);
	val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
	val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
	CONFIG_WRITE_WORD(PICR2, val);

	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
#ifndef CONFIG_SYS_RAMBOOT
	CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
				 (CONFIG_SYS_BANK0_ROW) |
				 (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
				 (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
				 (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
				 (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
				 (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
				 (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
				 (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
				 (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
#endif

#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
				 CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
				 CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
#else
	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
#endif

#if defined(CONFIG_MPC8240)
	CONFIG_WRITE_WORD(MCCR3,
		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT));
#elif defined(CONFIG_MPC8245)
	CONFIG_WRITE_WORD(MCCR3,
		(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

/* this is gross.  We think these should all be the same, and various boards
 *  should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
 *  its not set, we define it to zero in this file
 */
#if defined(CONFIG_CU824)
	CONFIG_WRITE_WORD(MCCR4,
	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
	MCCR4_BIT21 |
	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
		  CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
#elif defined(CONFIG_MPC8240)
	CONFIG_WRITE_WORD(MCCR4,
	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
	MCCR4_BIT21 |
	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
		  (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#elif defined(CONFIG_MPC8245)
	CONFIG_READ_WORD(MCCR1, val);
	val &= MCCR1_DBUS_SIZE0;    /* test for 64-bit mem bus */

	CONFIG_WRITE_WORD(MCCR4,
		(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
		(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
		(CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
		(CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
		(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
		((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
		(CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
		(((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
		      (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT)  |
		(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
		(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif

	CONFIG_WRITE_WORD(MSAR1,
		( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMSAR1,
		( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(MSAR2,
		( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMSAR2,
		( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(MEAR1,
		( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMEAR1,
		( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(MEAR2,
		( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
	CONFIG_WRITE_WORD(EMEAR2,
		( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));

	CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
#ifdef CONFIG_SYS_DLL_MAX_DELAY
	CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY);	/* needed to make DLL lock */
#endif
#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
	CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
#endif
#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
	CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD);	/* change memory input */
#endif /* setup & hold time */

	CONFIG_WRITE_BYTE(MBER,
		 CONFIG_SYS_BANK0_ENABLE |
		(CONFIG_SYS_BANK1_ENABLE << 1) |
		(CONFIG_SYS_BANK2_ENABLE << 2) |
		(CONFIG_SYS_BANK3_ENABLE << 3) |
		(CONFIG_SYS_BANK4_ENABLE << 4) |
		(CONFIG_SYS_BANK5_ENABLE << 5) |
		(CONFIG_SYS_BANK6_ENABLE << 6) |
		(CONFIG_SYS_BANK7_ENABLE << 7));

#ifdef CONFIG_SYS_PGMAX
	CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
#endif

	/* ! Wait 200us before initialize other registers */
	/*FIXME: write a decent udelay wait */
	__asm__ __volatile__(
		" mtctr	%0 \n \
		0: bdnz	 0b\n"
		:
		: "r" (0x10000));

	CONFIG_READ_WORD(MCCR1, val);
	CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
	__asm__ __volatile__("eieio");
}

/*
 * initialize higher level parts of CPU like time base and timers
 */
int cpu_init_r (void)
{
	return (0);
}
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000
	3	* Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	#include <common.h>
	9	#include <asm/processor.h>
	10	#include <mpc824x.h>
	11
6d0f6bcf JCPV	12	#ifndef CONFIG_SYS_BANK0_ROW
6d0f6bcf JCPV	13	#define CONFIG_SYS_BANK0_ROW 0
c609719b	14	#endif
6d0f6bcf JCPV	15	#ifndef CONFIG_SYS_BANK1_ROW
6d0f6bcf JCPV	16	#define CONFIG_SYS_BANK1_ROW 0
c609719b	17	#endif
6d0f6bcf JCPV	18	#ifndef CONFIG_SYS_BANK2_ROW
6d0f6bcf JCPV	19	#define CONFIG_SYS_BANK2_ROW 0
c609719b	20	#endif
6d0f6bcf JCPV	21	#ifndef CONFIG_SYS_BANK3_ROW
6d0f6bcf JCPV	22	#define CONFIG_SYS_BANK3_ROW 0
c609719b	23	#endif
6d0f6bcf JCPV	24	#ifndef CONFIG_SYS_BANK4_ROW
6d0f6bcf JCPV	25	#define CONFIG_SYS_BANK4_ROW 0
c609719b	26	#endif
6d0f6bcf JCPV	27	#ifndef CONFIG_SYS_BANK5_ROW
6d0f6bcf JCPV	28	#define CONFIG_SYS_BANK5_ROW 0
c609719b	29	#endif
6d0f6bcf JCPV	30	#ifndef CONFIG_SYS_BANK6_ROW
6d0f6bcf JCPV	31	#define CONFIG_SYS_BANK6_ROW 0
c609719b	32	#endif
6d0f6bcf JCPV	33	#ifndef CONFIG_SYS_BANK7_ROW
6d0f6bcf JCPV	34	#define CONFIG_SYS_BANK7_ROW 0
c609719b	35	#endif
6d0f6bcf JCPV	36	#ifndef CONFIG_SYS_DBUS_SIZE2
6d0f6bcf JCPV	37	#define CONFIG_SYS_DBUS_SIZE2 0
c609719b WD	38	#endif
	39
	40	/*
	41	* Breath some life into the CPU...
	42	*
	43	* Set up the memory map,
	44	* initialize a bunch of registers,
	45	*/
	46	void
	47	cpu_init_f (void)
	48	{
c609719b WD	49	register unsigned long val;
	50	CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
	51	/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); / /reset PCISR*/
	52
649acfe1	53	#if defined(CONFIG_MUSENKI)
c609719b WD	54	/* Why is this here, you ask? Try, just try setting 0x8000
	55	* in PCIACR with CONFIG_WRITE_HALFWORD()
	56	* this one was a stumper, and we are annoyed
	57	*/
	58
	59	#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
39539887 WD	60	__asm__ __volatile__(" \
	61	stw %2,0(%0)\n \
	62	sync\n \
	63	sth %3,2(%1)\n \
	64	sync\n \
	65	" \
	66	: /* no output */ \
	67	: "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
	68	"r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
	69	);
c609719b	70
39539887	71	M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
c609719b WD	72	#endif
c609719b WD	73
39539887	74	CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */
30ce5ab0	75	CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
39539887 WD	76	/*
	77	* Note that although this bit is cleared after a hard reset, it
	78	* must be explicitly set and then cleared by software during
	79	* initialization in order to guarantee correct operation of the
	80	* DLL and the SDRAM_CLK[0:3] signals (if they are used).
	81	*/
	82	CONFIG_READ_BYTE (AMBOR, val);
	83	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
	84	CONFIG_WRITE_BYTE(AMBOR, val \| 0x20);
	85	CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
	86	#ifdef CONFIG_MPC8245
	87	/* silicon bug 28 MPC8245 */
	88	CONFIG_READ_BYTE(AMBOR,val);
	89	CONFIG_WRITE_BYTE(AMBOR,val\|0x1);
	90
8b0bfc68 WD	91	#if 0
	92	/*
	93	* The following bug only affects older (XPC8245) processors.
	94	* DMA transfers initiated by external devices get corrupted due
	95	* to a hardware scheduling problem.
	96	*
	97	* The effect is:
	98	* when transferring X words, the first 32 words are transferred
	99	* OK, the next 3 x 32 words are 'old' data (from previous DMA)
	100	* while the rest of the X words is xferred fine.
	101	*
	102	* Disabling 3 of the 4 32 word hardware buffers solves the problem
	103	* with no significant performance loss.
	104	*/
	105
39539887 WD	106	CONFIG_READ_BYTE(PCMBCR,val);
39539887 WD	107	/* in order not to corrupt data which is being read over the PCI bus
281e00a3	108	* with the PPC as slave, we need to reduce the number of PCMRBs to 1,
39539887 WD	109	* 4.11 in the processor user manual
39539887 WD	110	* */
c609719b	111
39539887 WD	112	#if 1
	113	CONFIG_WRITE_BYTE(PCMBCR,(val\|0xC0)); /* 1 PCMRB */
	114	#else
	115	CONFIG_WRITE_BYTE(PCMBCR,(val\|0x80)); /* 2 PCMRBs */
	116	CONFIG_WRITE_BYTE(PCMBCR,(val\|0x40)); /* 3 PCMRBs */
8b0bfc68 WD	117	/* default, 4 PCMRBs are used */
8b0bfc68 WD	118	#endif
39539887 WD	119	#endif
	120	#endif
	121
	122	CONFIG_READ_WORD(PICR1, val);
c609719b	123	#if defined(CONFIG_MPC8240)
39539887 WD	124	CONFIG_WRITE_WORD( PICR1,
	125	(val & (PICR1_ADDRESS_MAP \| PICR1_RCS0)) \|
	126	PIRC1_MSK \| PICR1_PROC_TYPE_603E \|
	127	PICR1_FLASH_WR_EN \| PICR1_MCP_EN \|
	128	PICR1_CF_DPARK \| PICR1_EN_PCS \|
	129	PICR1_CF_APARK );
c609719b	130	#elif defined(CONFIG_MPC8245)
39539887 WD	131	CONFIG_WRITE_WORD( PICR1,
	132	(val & (PICR1_RCS0)) \|
	133	PICR1_PROC_TYPE_603E \|
	134	PICR1_FLASH_WR_EN \| PICR1_MCP_EN \|
	135	PICR1_CF_DPARK \| PICR1_NO_BUSW_CK \|
	136	PICR1_DEC\| PICR1_CF_APARK \| 0x10); /* 8245 UM says bit 4 must be set */
c609719b WD	137	#else
	138	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	139	#endif
	140
39539887 WD	141	CONFIG_READ_WORD(PICR2, val);
39539887 WD	142	val= val & ~ (PICR2_CF_SNOOP_WS_MASK \| PICR2_CF_APHASE_WS_MASK); /mask off waitstate bits/
39539887	143	val \|= PICR2_CF_SNOOP_WS_1WS \| PICR2_CF_APHASE_WS_1WS; /1 wait state/
39539887	144	CONFIG_WRITE_WORD(PICR2, val);
c609719b	145
6d0f6bcf JCPV	146	CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
	147	#ifndef CONFIG_SYS_RAMBOOT
	148	CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) \|
	149	(CONFIG_SYS_BANK0_ROW) \|
	150	(CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) \|
	151	(CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) \|
	152	(CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) \|
	153	(CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) \|
	154	(CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) \|
	155	(CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) \|
	156	(CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) \|
	157	(CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
c609719b WD	158	#endif
c609719b WD	159
6d0f6bcf JCPV	160	#if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
	161	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT \|
	162	CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT \|
	163	CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
c609719b	164	#else
6d0f6bcf	165	CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
c609719b WD	166	#endif
	167
	168	#if defined(CONFIG_MPC8240)
39539887	169	CONFIG_WRITE_WORD(MCCR3,
6d0f6bcf JCPV	170	(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) \|
	171	(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) \|
	172	(CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT));
c609719b	173	#elif defined(CONFIG_MPC8245)
39539887	174	CONFIG_WRITE_WORD(MCCR3,
6d0f6bcf JCPV	175	(((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) \|
6d0f6bcf JCPV	176	(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
c609719b WD	177	#else
	178	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	179	#endif
	180
	181	/* this is gross. We think these should all be the same, and various boards
6d0f6bcf	182	* should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
c609719b WD	183	* its not set, we define it to zero in this file
c609719b WD	184	*/
649acfe1	185	#if defined(CONFIG_CU824)
c609719b	186	CONFIG_WRITE_WORD(MCCR4,
6d0f6bcf JCPV	187	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \|
6d0f6bcf JCPV	188	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \|
c609719b	189	MCCR4_BIT21 \|
6d0f6bcf JCPV	190	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) \|
	191	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) \|
	192	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) \| (CONFIG_SYS_SDMODE_WRAP <<3) \|
	193	CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) \|
	194	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) \|
	195	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
c609719b WD	196	#elif defined(CONFIG_MPC8240)
c609719b WD	197	CONFIG_WRITE_WORD(MCCR4,
6d0f6bcf JCPV	198	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \|
6d0f6bcf JCPV	199	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \|
c609719b	200	MCCR4_BIT21 \|
6d0f6bcf JCPV	201	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) \|
	202	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) \|
	203	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) \| (CONFIG_SYS_SDMODE_WRAP <<3) \|
	204	(CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) \|
	205	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
c609719b	206	#elif defined(CONFIG_MPC8245)
39539887 WD	207	CONFIG_READ_WORD(MCCR1, val);
39539887 WD	208	val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
c609719b	209
39539887	210	CONFIG_WRITE_WORD(MCCR4,
6d0f6bcf JCPV	211	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) \|
	212	(CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) \|
	213	(CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) \|
	214	(CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) \|
	215	(CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) \|
	216	((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) \|
	217	(CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) \|
	218	(((CONFIG_SYS_SDMODE_CAS_LAT <<4) \| (CONFIG_SYS_SDMODE_WRAP <<3) \|
39539887	219	(val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) \|
6d0f6bcf JCPV	220	(CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) \|
6d0f6bcf JCPV	221	(((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
c609719b WD	222	#else
	223	#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
	224	#endif
	225
39539887	226	CONFIG_WRITE_WORD(MSAR1,
6d0f6bcf JCPV	227	( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	228	(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	229	(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	230	(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	231	CONFIG_WRITE_WORD(EMSAR1,
6d0f6bcf JCPV	232	( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	233	(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	234	(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	235	(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
39539887	236	CONFIG_WRITE_WORD(MSAR2,
6d0f6bcf JCPV	237	( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	238	(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	239	(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	240	(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	241	CONFIG_WRITE_WORD(EMSAR2,
6d0f6bcf JCPV	242	( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	243	(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	244	(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	245	(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
39539887	246	CONFIG_WRITE_WORD(MEAR1,
6d0f6bcf JCPV	247	( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	248	(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	249	(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	250	(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	251	CONFIG_WRITE_WORD(EMEAR1,
6d0f6bcf JCPV	252	( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	253	(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	254	(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	255	(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
39539887	256	CONFIG_WRITE_WORD(MEAR2,
6d0f6bcf JCPV	257	( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) \|
	258	(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) \|
	259	(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) \|
	260	(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
39539887	261	CONFIG_WRITE_WORD(EMEAR2,
6d0f6bcf JCPV	262	( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) \|
	263	(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) \|
	264	(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) \|
	265	(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
c609719b	266
6d0f6bcf JCPV	267	CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
	268	#ifdef CONFIG_SYS_DLL_MAX_DELAY
	269	CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */
c609719b	270	#endif
6d0f6bcf JCPV	271	#if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
6d0f6bcf JCPV	272	CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND \| CONFIG_SYS_PCI_HOLD_DEL);
c609719b	273	#endif
6d0f6bcf JCPV	274	#if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
6d0f6bcf JCPV	275	CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */
c609719b WD	276	#endif /* setup & hold time */
c609719b WD	277
39539887	278	CONFIG_WRITE_BYTE(MBER,
6d0f6bcf JCPV	279	CONFIG_SYS_BANK0_ENABLE \|
	280	(CONFIG_SYS_BANK1_ENABLE << 1) \|
	281	(CONFIG_SYS_BANK2_ENABLE << 2) \|
	282	(CONFIG_SYS_BANK3_ENABLE << 3) \|
	283	(CONFIG_SYS_BANK4_ENABLE << 4) \|
	284	(CONFIG_SYS_BANK5_ENABLE << 5) \|
	285	(CONFIG_SYS_BANK6_ENABLE << 6) \|
	286	(CONFIG_SYS_BANK7_ENABLE << 7));
c609719b	287
6d0f6bcf JCPV	288	#ifdef CONFIG_SYS_PGMAX
6d0f6bcf JCPV	289	CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
c609719b WD	290	#endif
c609719b WD	291
39539887 WD	292	/* ! Wait 200us before initialize other registers */
	293	/FIXME: write a decent udelay wait /
	294	__asm__ __volatile__(
	295	" mtctr %0 \n \
	296	0: bdnz 0b\n"
	297	:
	298	: "r" (0x10000));
c609719b	299
39539887 WD	300	CONFIG_READ_WORD(MCCR1, val);
	301	CONFIG_WRITE_WORD(MCCR1, val \| MCCR1_MEMGO); /* set memory access going */
	302	__asm__ __volatile__("eieio");
c609719b WD	303	}
c609719b WD	304
c609719b WD	305	/*
	306	* initialize higher level parts of CPU like time base and timers
	307	*/
	308	int cpu_init_r (void)
	309	{
c609719b WD	310	return (0);
c609719b WD	311	}