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1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2002 | |
6 | * Gregory E. Allen, gallen@arlut.utexas.edu | |
7 | * Applied Research Laboratories, The University of Texas at Austin | |
8 | * | |
1a459660 | 9 | * SPDX-License-Identifier: GPL-2.0+ |
2f001a3c WD |
10 | */ |
11 | ||
12 | #include <common.h> | |
13 | #include <mpc824x.h> | |
14 | #include <asm/processor.h> | |
15 | ||
d87080b7 WD |
16 | DECLARE_GLOBAL_DATA_PTR; |
17 | ||
2f001a3c WD |
18 | /* ------------------------------------------------------------------------- */ |
19 | /* NOTE: This describes the proper use of this file. | |
20 | * | |
21 | * CONFIG_SYS_CLK_FREQ should be defined as the input frequency on | |
22 | * PCI_SYNC_IN . | |
23 | * | |
24 | * CONFIG_PLL_PCI_TO_MEM_MULTIPLIER is only required on MPC8240 | |
25 | * boards. It should be defined as the PCI to Memory Multiplier as | |
26 | * documented in the MPC8240 Hardware Specs. | |
27 | * | |
28 | * Other mpc824x boards don't need CONFIG_PLL_PCI_TO_MEM_MULTIPLIER | |
29 | * because they can determine it from the PCR. | |
30 | * | |
31 | * Gary Milliorn <gary.milliorn@motorola.com> (who should know since | |
32 | * he designed the Sandpoint) told us that the PCR is not in all revs | |
33 | * of the MPC8240 CPU, so it's not guaranteeable and we cannot do | |
34 | * away with CONFIG_PLL_PCI_TO_MEM_MULTIPLIER altogether. | |
35 | */ | |
36 | /* ------------------------------------------------------------------------- */ | |
37 | ||
38 | /* This gives the PCI to Memory multiplier times 10 */ | |
39 | /* The index is the value of PLL_CFG[0:4] */ | |
40 | /* This is documented in the MPC8240/5 Hardware Specs */ | |
41 | ||
42 | short pll_pci_to_mem_multiplier[] = { | |
43 | #if defined(CONFIG_MPC8240) | |
44 | 30, 30, 10, 10, 20, 10, 0, 10, | |
45 | 10, 0, 20, 0, 20, 0, 20, 0, | |
46 | 30, 0, 15, 0, 20, 0, 20, 0, | |
47 | 25, 0, 10, 0, 15, 15, 0, 0, | |
48 | #elif defined(CONFIG_MPC8245) | |
49 | 30, 30, 10, 10, 20, 10, 10, 10, | |
fc3e2165 WD |
50 | 10, 20, 20, 15, 20, 15, 20, 30, |
51 | 30, 40, 15, 40, 20, 25, 20, 40, | |
2f001a3c WD |
52 | 25, 20, 10, 20, 15, 15, 15, 0, |
53 | #else | |
54 | #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240) | |
55 | #endif | |
56 | }; | |
57 | ||
58 | #define CU824_PLL_STATE_REG 0xFE80002F | |
59 | #define PCR 0x800000E2 | |
60 | ||
61 | /* ------------------------------------------------------------------------- */ | |
62 | ||
63 | /* compute the memory bus clock frequency */ | |
64 | ulong get_bus_freq (ulong dummy) | |
65 | { | |
66 | unsigned char pll_cfg; | |
67 | #if defined(CONFIG_MPC8240) && !defined(CONFIG_CU824) | |
68 | return (CONFIG_SYS_CLK_FREQ) * (CONFIG_PLL_PCI_TO_MEM_MULTIPLIER); | |
69 | #elif defined(CONFIG_CU824) | |
70 | pll_cfg = *(volatile unsigned char *) (CU824_PLL_STATE_REG); | |
71 | pll_cfg &= 0x1f; | |
72 | #else | |
73 | CONFIG_READ_BYTE(PCR, pll_cfg); | |
74 | pll_cfg = (pll_cfg >> 3) & 0x1f; | |
75 | #endif | |
76 | return ((CONFIG_SYS_CLK_FREQ) * pll_pci_to_mem_multiplier[pll_cfg] + 5) / 10; | |
77 | } | |
78 | ||
79 | ||
80 | /* ------------------------------------------------------------------------- */ | |
81 | ||
82 | /* This gives the Memory to CPU Core multiplier times 10 */ | |
83 | /* The index is the value of PLLRATIO in HID1 */ | |
84 | /* This is documented in the MPC8240 Hardware Specs */ | |
85 | /* This is not documented for MPC8245 ? FIXME */ | |
86 | short pllratio_to_factor[] = { | |
87 | 0, 0, 0, 10, 20, 20, 25, 45, | |
88 | 30, 0, 0, 0, 0, 0, 0, 0, | |
89 | 0, 0, 0, 10, 0, 0, 0, 45, | |
90 | 30, 0, 40, 0, 0, 0, 35, 0, | |
91 | }; | |
92 | ||
93 | /* compute the CPU and memory bus clock frequencies */ | |
94 | int get_clocks (void) | |
95 | { | |
2f001a3c WD |
96 | uint hid1 = mfspr(HID1); |
97 | hid1 = (hid1 >> (32-5)) & 0x1f; | |
98 | gd->cpu_clk = (pllratio_to_factor[hid1] * get_bus_freq(0) + 5) | |
99 | / 10; | |
100 | gd->bus_clk = get_bus_freq(0); | |
101 | return (0); | |
102 | } |