[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8260 / cpu_init.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc8260.h>
#include <asm/cpm_8260.h>
#include <ioports.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
extern unsigned long board_get_cpu_clk_f (void);
#endif

static void config_8260_ioports (volatile immap_t * immr)
{
	int portnum;

	for (portnum = 0; portnum < 4; portnum++) {
		uint pmsk = 0,
		     ppar = 0,
		     psor = 0,
		     pdir = 0,
		     podr = 0,
		     pdat = 0;
		iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
		iop_conf_t *eiopc = iopc + 32;
		uint msk = 1;

		/*
		 * NOTE:
		 * index 0 refers to pin 31,
		 * index 31 refers to pin 0
		 */
		while (iopc < eiopc) {
			if (iopc->conf) {
				pmsk |= msk;
				if (iopc->ppar)
					ppar |= msk;
				if (iopc->psor)
					psor |= msk;
				if (iopc->pdir)
					pdir |= msk;
				if (iopc->podr)
					podr |= msk;
				if (iopc->pdat)
					pdat |= msk;
			}

			msk <<= 1;
			iopc++;
		}

		if (pmsk != 0) {
			volatile ioport_t *iop = ioport_addr (immr, portnum);
			uint tpmsk = ~pmsk;

			/*
			 * the (somewhat confused) paragraph at the
			 * bottom of page 35-5 warns that there might
			 * be "unknown behaviour" when programming
			 * PSORx and PDIRx, if PPARx = 1, so I
			 * decided this meant I had to disable the
			 * dedicated function first, and enable it
			 * last.
			 */
			iop->ppar &= tpmsk;
			iop->psor = (iop->psor & tpmsk) | psor;
			iop->podr = (iop->podr & tpmsk) | podr;
			iop->pdat = (iop->pdat & tpmsk) | pdat;
			iop->pdir = (iop->pdir & tpmsk) | pdir;
			iop->ppar |= ppar;
		}
	}
}

#define SET_VAL_MASK(a, b, mask) ((a & mask) | (b & ~mask))
/*
 * Breath some life into the CPU...
 *
 * Set up the memory map,
 * initialize a bunch of registers,
 * initialize the UPM's
 */
void cpu_init_f (volatile immap_t * immr)
{
#if !defined(CONFIG_COGENT)		/* done in start.S for the cogent */
	uint sccr;
#endif
#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
	unsigned long cpu_clk;
#endif
	volatile memctl8260_t *memctl = &immr->im_memctl;
	extern void m8260_cpm_reset (void);

	/* Pointer is writable since we allocated a register for it */
	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);

	/* Clear initial global data */
	memset ((void *) gd, 0, sizeof (gd_t));

	/* RSR - Reset Status Register - clear all status (5-4) */
	gd->reset_status = immr->im_clkrst.car_rsr;
	immr->im_clkrst.car_rsr = RSR_ALLBITS;

	/* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
	immr->im_clkrst.car_rmr = CONFIG_SYS_RMR;

	/* BCR - Bus Configuration Register (4-25) */
#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE)
	if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
		immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010);
	} else {
		immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010);
	}
#else
	immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR;
#endif

	/* SIUMCR - contains debug pin configuration (4-31) */
#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH)
	cpu_clk = board_get_cpu_clk_f ();
	if (cpu_clk >= 100000000) {
		immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000);
	} else {
		immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000);
	}
#else
	immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
#endif

	config_8260_ioports (immr);

	/* initialize time counter status and control register (4-40) */
	immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC;

	/* initialize the PIT (4-42) */
	immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;

#if !defined(CONFIG_COGENT)		/* done in start.S for the cogent */
	/* System clock control register (9-8) */
	sccr = immr->im_clkrst.car_sccr &
		(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK);
	immr->im_clkrst.car_sccr = sccr |
		(CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE | SCCR_PCI_MODCK | SCCR_PCIDF_MSK) );
#endif /* !CONFIG_COGENT */

	/*
	 * Memory Controller:
	 */

	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	 * addresses - these have to be modified later when FLASH size
	 * has been determined
	 */

#if defined(CONFIG_SYS_OR0_REMAP)
	memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
	memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
#endif

	/* now restrict to preliminary range */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <mpc8260.h>
	26	#include <asm/cpm_8260.h>
	27	#include <ioports.h>
	28
d87080b7 WD	29	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	30
fa230445 HS	31	#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
	32	extern unsigned long board_get_cpu_clk_f (void);
	33	#endif
	34
c609719b WD	35	static void config_8260_ioports (volatile immap_t * immr)
	36	{
	37	int portnum;
	38
	39	for (portnum = 0; portnum < 4; portnum++) {
	40	uint pmsk = 0,
	41	ppar = 0,
	42	psor = 0,
	43	pdir = 0,
	44	podr = 0,
	45	pdat = 0;
	46	iop_conf_t iopc = (iop_conf_t ) & iop_conf_tab[portnum][0];
	47	iop_conf_t *eiopc = iopc + 32;
	48	uint msk = 1;
	49
	50	/*
	51	* NOTE:
	52	* index 0 refers to pin 31,
	53	* index 31 refers to pin 0
	54	*/
	55	while (iopc < eiopc) {
	56	if (iopc->conf) {
	57	pmsk \|= msk;
	58	if (iopc->ppar)
	59	ppar \|= msk;
	60	if (iopc->psor)
	61	psor \|= msk;
	62	if (iopc->pdir)
	63	pdir \|= msk;
	64	if (iopc->podr)
	65	podr \|= msk;
	66	if (iopc->pdat)
	67	pdat \|= msk;
	68	}
	69
	70	msk <<= 1;
	71	iopc++;
	72	}
	73
	74	if (pmsk != 0) {
	75	volatile ioport_t *iop = ioport_addr (immr, portnum);
	76	uint tpmsk = ~pmsk;
	77
	78	/*
8bde7f77 WD	79	* the (somewhat confused) paragraph at the
	80	* bottom of page 35-5 warns that there might
	81	* be "unknown behaviour" when programming
	82	* PSORx and PDIRx, if PPARx = 1, so I
	83	* decided this meant I had to disable the
	84	* dedicated function first, and enable it
	85	* last.
c609719b WD	86	*/
	87	iop->ppar &= tpmsk;
	88	iop->psor = (iop->psor & tpmsk) \| psor;
6dd652fa	89	iop->podr = (iop->podr & tpmsk) \| podr;
c609719b WD	90	iop->pdat = (iop->pdat & tpmsk) \| pdat;
c609719b WD	91	iop->pdir = (iop->pdir & tpmsk) \| pdir;
c609719b WD	92	iop->ppar \|= ppar;
	93	}
	94	}
	95	}
	96
fa230445	97	#define SET_VAL_MASK(a, b, mask) ((a & mask) \| (b & ~mask))
c609719b WD	98	/*
	99	* Breath some life into the CPU...
	100	*
	101	* Set up the memory map,
	102	* initialize a bunch of registers,
	103	* initialize the UPM's
	104	*/
	105	void cpu_init_f (volatile immap_t * immr)
	106	{
4b248f3f WD	107	#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
4b248f3f WD	108	uint sccr;
fa230445 HS	109	#endif
	110	#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
	111	unsigned long cpu_clk;
4b248f3f	112	#endif
c609719b WD	113	volatile memctl8260_t *memctl = &immr->im_memctl;
	114	extern void m8260_cpm_reset (void);
	115
	116	/* Pointer is writable since we allocated a register for it */
6d0f6bcf	117	gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
c609719b WD	118
	119	/* Clear initial global data */
	120	memset ((void *) gd, 0, sizeof (gd_t));
	121
	122	/* RSR - Reset Status Register - clear all status (5-4) */
	123	gd->reset_status = immr->im_clkrst.car_rsr;
	124	immr->im_clkrst.car_rsr = RSR_ALLBITS;
	125
	126	/* RMR - Reset Mode Register - contains checkstop reset enable (5-5) */
6d0f6bcf	127	immr->im_clkrst.car_rmr = CONFIG_SYS_RMR;
c609719b WD	128
c609719b WD	129	/* BCR - Bus Configuration Register (4-25) */
6d0f6bcf	130	#if defined(CONFIG_SYS_BCR_60x) && (CONFIG_SYS_BCR_SINGLE)
fa230445	131	if (immr->im_siu_conf.sc_bcr & BCR_EBM) {
6d0f6bcf	132	immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_60x, 0x80000010);
fa230445	133	} else {
6d0f6bcf	134	immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CONFIG_SYS_BCR_SINGLE, 0x80000010);
fa230445 HS	135	}
fa230445 HS	136	#else
6d0f6bcf	137	immr->im_siu_conf.sc_bcr = CONFIG_SYS_BCR;
fa230445	138	#endif
c609719b WD	139
c609719b WD	140	/* SIUMCR - contains debug pin configuration (4-31) */
6d0f6bcf	141	#if defined(CONFIG_SYS_SIUMCR_LOW) && (CONFIG_SYS_SIUMCR_HIGH)
fa230445 HS	142	cpu_clk = board_get_cpu_clk_f ();
fa230445 HS	143	if (cpu_clk >= 100000000) {
6d0f6bcf	144	immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_HIGH, 0x9f3cc000);
fa230445	145	} else {
6d0f6bcf	146	immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR_LOW, 0x9f3cc000);
fa230445 HS	147	}
fa230445 HS	148	#else
6d0f6bcf	149	immr->im_siu_conf.sc_siumcr = CONFIG_SYS_SIUMCR;
fa230445	150	#endif
c609719b WD	151
	152	config_8260_ioports (immr);
	153
	154	/* initialize time counter status and control register (4-40) */
6d0f6bcf	155	immr->im_sit.sit_tmcntsc = CONFIG_SYS_TMCNTSC;
c609719b WD	156
c609719b WD	157	/* initialize the PIT (4-42) */
6d0f6bcf	158	immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
c609719b WD	159
	160	#if !defined(CONFIG_COGENT) /* done in start.S for the cogent */
	161	/* System clock control register (9-8) */
4b248f3f WD	162	sccr = immr->im_clkrst.car_sccr &
	163	(SCCR_PCI_MODE \| SCCR_PCI_MODCK \| SCCR_PCIDF_MSK);
	164	immr->im_clkrst.car_sccr = sccr \|
6d0f6bcf	165	(CONFIG_SYS_SCCR & ~(SCCR_PCI_MODE \| SCCR_PCI_MODCK \| SCCR_PCIDF_MSK) );
c609719b WD	166	#endif /* !CONFIG_COGENT */
	167
	168	/*
	169	* Memory Controller:
	170	*/
	171
	172	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	173	* addresses - these have to be modified later when FLASH size
	174	* has been determined
	175	*/
	176
6d0f6bcf JCPV	177	#if defined(CONFIG_SYS_OR0_REMAP)
6d0f6bcf JCPV	178	memctl->memc_or0 = CONFIG_SYS_OR0_REMAP;
c609719b	179	#endif
6d0f6bcf JCPV	180	#if defined(CONFIG_SYS_OR1_REMAP)
6d0f6bcf JCPV	181	memctl->memc_or1 = CONFIG_SYS_OR1_REMAP;
c609719b WD	182	#endif
	183
	184	/* now restrict to preliminary range */
e4dbe1b2	185