[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8260 / interrupts.c

/*
 * (C) Copyright 2000-2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
 */

#include <common.h>
#include <command.h>
#include <mpc8260.h>
#include <mpc8260_irq.h>
#include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR;

/****************************************************************************/

struct irq_action {
	interrupt_handler_t *handler;
	void *arg;
	ulong count;
};

static struct irq_action irq_handlers[NR_IRQS];

static ulong ppc_cached_irq_mask[NR_MASK_WORDS];

/****************************************************************************/
/* this section was ripped out of arch/powerpc/kernel/ppc8260_pic.c in the	    */
/* Linux/PPC 2.4.x source. There was no copyright notice in that file.	    */

/* The 8260 internal interrupt controller.  It is usually
 * the only interrupt controller.
 * There are two 32-bit registers (high/low) for up to 64
 * possible interrupts.
 *
 * Now, the fun starts.....Interrupt Numbers DO NOT MAP
 * in a simple arithmetic fashion to mask or pending registers.
 * That is, interrupt 4 does not map to bit position 4.
 * We create two tables, indexed by vector number, to indicate
 * which register to use and which bit in the register to use.
 */
static u_char irq_to_siureg[] = {
	1, 1, 1, 1, 1, 1, 1, 1,
	1, 1, 1, 1, 1, 1, 1, 1,
	0, 0, 0, 0, 0, 0, 0, 0,
	0, 0, 0, 0, 0, 0, 0, 0,
	1, 1, 1, 1, 1, 1, 1, 1,
	1, 1, 1, 1, 1, 1, 1, 1,
	0, 0, 0, 0, 0, 0, 0, 0,
	0, 0, 0, 0, 0, 0, 0, 0
};

static u_char irq_to_siubit[] = {
	31, 16, 17, 18, 19, 20, 21, 22,
	23, 24, 25, 26, 27, 28, 29, 30,
	29, 30, 16, 17, 18, 19, 20, 21,
	22, 23, 24, 25, 26, 27, 28, 31,
	0, 1, 2, 3, 4, 5, 6, 7,
	8, 9, 10, 11, 12, 13, 14, 15,
	15, 14, 13, 12, 11, 10, 9, 8,
	7, 6, 5, 4, 3, 2, 1, 0
};

static void m8260_mask_irq (unsigned int irq_nr)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	int bit, word;
	volatile uint *simr;

	bit = irq_to_siubit[irq_nr];
	word = irq_to_siureg[irq_nr];

	simr = &(immr->im_intctl.ic_simrh);
	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
	simr[word] = ppc_cached_irq_mask[word];
}

static void m8260_unmask_irq (unsigned int irq_nr)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	int bit, word;
	volatile uint *simr;

	bit = irq_to_siubit[irq_nr];
	word = irq_to_siureg[irq_nr];

	simr = &(immr->im_intctl.ic_simrh);
	ppc_cached_irq_mask[word] |= (1 << (31 - bit));
	simr[word] = ppc_cached_irq_mask[word];
}

static void m8260_mask_and_ack (unsigned int irq_nr)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	int bit, word;
	volatile uint *simr, *sipnr;

	bit = irq_to_siubit[irq_nr];
	word = irq_to_siureg[irq_nr];

	simr = &(immr->im_intctl.ic_simrh);
	sipnr = &(immr->im_intctl.ic_sipnrh);
	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
	simr[word] = ppc_cached_irq_mask[word];
	sipnr[word] = 1 << (31 - bit);
}

static int m8260_get_irq (struct pt_regs *regs)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	int irq;
	unsigned long bits;

	/* For MPC8260, read the SIVEC register and shift the bits down
	 * to get the irq number.         */
	bits = immr->im_intctl.ic_sivec;
	irq = bits >> 26;
	return irq;
}

/* end of code ripped out of arch/powerpc/kernel/ppc8260_pic.c		    */
/****************************************************************************/

int interrupt_init_cpu (unsigned *decrementer_count)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	*decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ;

	/* Initialize the default interrupt mapping priorities */
	immr->im_intctl.ic_sicr = 0;
	immr->im_intctl.ic_siprr = 0x05309770;
	immr->im_intctl.ic_scprrh = 0x05309770;
	immr->im_intctl.ic_scprrl = 0x05309770;

	/* disable all interrupts and clear all pending bits */
	immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
	immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
	immr->im_intctl.ic_sipnrh = 0xffffffff;
	immr->im_intctl.ic_sipnrl = 0xffffffff;

#ifdef CONFIG_HYMOD
	/*
	 * ensure all external interrupt sources default to trigger on
	 * high-to-low transition (i.e. edge triggered active low)
	 */
	immr->im_intctl.ic_siexr = -1;
#endif

	return (0);
}

/****************************************************************************/

/*
 * Handle external interrupts
 */
void external_interrupt (struct pt_regs *regs)
{
	int irq, unmask = 1;

	irq = m8260_get_irq (regs);

	m8260_mask_and_ack (irq);

	enable_interrupts ();

	if (irq_handlers[irq].handler != NULL)
		(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
	else {
		printf ("\nBogus External Interrupt IRQ %d\n", irq);
		/*
		 * turn off the bogus interrupt, otherwise it
		 * might repeat forever
		 */
		unmask = 0;
	}

	if (unmask)
		m8260_unmask_irq (irq);
}

/****************************************************************************/

/*
 * Install and free an interrupt handler.
 */

void
irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
{
	if (irq < 0 || irq >= NR_IRQS) {
		printf ("irq_install_handler: bad irq number %d\n", irq);
		return;
	}

	if (irq_handlers[irq].handler != NULL)
		printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
				(ulong) handler, (ulong) irq_handlers[irq].handler);

	irq_handlers[irq].handler = handler;
	irq_handlers[irq].arg = arg;

	m8260_unmask_irq (irq);
}

void irq_free_handler (int irq)
{
	if (irq < 0 || irq >= NR_IRQS) {
		printf ("irq_free_handler: bad irq number %d\n", irq);
		return;
	}

	m8260_mask_irq (irq);

	irq_handlers[irq].handler = NULL;
	irq_handlers[irq].arg = NULL;
}

/****************************************************************************/

void timer_interrupt_cpu (struct pt_regs *regs)
{
	/* nothing to do here */
	return;
}

/****************************************************************************/

#if defined(CONFIG_CMD_IRQ)

/* ripped this out of ppc4xx/interrupts.c */

/*******************************************************************************
*
* irqinfo - print information about PCI devices
*
*/
void
do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
{
	int irq, re_enable;

	re_enable = disable_interrupts ();

	puts ("\nInterrupt-Information:\n"
		"Nr  Routine   Arg       Count\n");

	for (irq = 0; irq < 32; irq++)
		if (irq_handlers[irq].handler != NULL)
			printf ("%02d  %08lx  %08lx  %ld\n", irq,
					(ulong) irq_handlers[irq].handler,
					(ulong) irq_handlers[irq].arg,
					irq_handlers[irq].count);

	if (re_enable)
		enable_interrupts ();
}

#endif
Commit	Line	Data
4a9cbbe8 WD	1	/*
	2	* (C) Copyright 2000-2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
4a9cbbe8 WD	6	*
	7	* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
	8	*/
	9
	10	#include <common.h>
4a9cbbe8 WD	11	#include <command.h>
	12	#include <mpc8260.h>
	13	#include <mpc8260_irq.h>
	14	#include <asm/processor.h>
	15
d87080b7 WD	16	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	17
4a9cbbe8 WD	18	/****************************************************************************/
4a9cbbe8 WD	19
4a9cbbe8 WD	20	struct irq_action {
	21	interrupt_handler_t *handler;
	22	void *arg;
	23	ulong count;
	24	};
	25
	26	static struct irq_action irq_handlers[NR_IRQS];
	27
	28	static ulong ppc_cached_irq_mask[NR_MASK_WORDS];
	29
	30	/****************************************************************************/
a47a12be	31	/* this section was ripped out of arch/powerpc/kernel/ppc8260_pic.c in the */
4a9cbbe8 WD	32	/* Linux/PPC 2.4.x source. There was no copyright notice in that file. */
	33
	34	/* The 8260 internal interrupt controller. It is usually
	35	* the only interrupt controller.
	36	* There are two 32-bit registers (high/low) for up to 64
	37	* possible interrupts.
	38	*
	39	* Now, the fun starts.....Interrupt Numbers DO NOT MAP
	40	* in a simple arithmetic fashion to mask or pending registers.
	41	* That is, interrupt 4 does not map to bit position 4.
	42	* We create two tables, indexed by vector number, to indicate
	43	* which register to use and which bit in the register to use.
	44	*/
	45	static u_char irq_to_siureg[] = {
	46	1, 1, 1, 1, 1, 1, 1, 1,
	47	1, 1, 1, 1, 1, 1, 1, 1,
	48	0, 0, 0, 0, 0, 0, 0, 0,
	49	0, 0, 0, 0, 0, 0, 0, 0,
	50	1, 1, 1, 1, 1, 1, 1, 1,
	51	1, 1, 1, 1, 1, 1, 1, 1,
	52	0, 0, 0, 0, 0, 0, 0, 0,
	53	0, 0, 0, 0, 0, 0, 0, 0
	54	};
	55
	56	static u_char irq_to_siubit[] = {
	57	31, 16, 17, 18, 19, 20, 21, 22,
	58	23, 24, 25, 26, 27, 28, 29, 30,
	59	29, 30, 16, 17, 18, 19, 20, 21,
	60	22, 23, 24, 25, 26, 27, 28, 31,
	61	0, 1, 2, 3, 4, 5, 6, 7,
	62	8, 9, 10, 11, 12, 13, 14, 15,
	63	15, 14, 13, 12, 11, 10, 9, 8,
	64	7, 6, 5, 4, 3, 2, 1, 0
	65	};
	66
	67	static void m8260_mask_irq (unsigned int irq_nr)
	68	{
6d0f6bcf	69	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
4a9cbbe8 WD	70	int bit, word;
	71	volatile uint *simr;
	72
	73	bit = irq_to_siubit[irq_nr];
	74	word = irq_to_siureg[irq_nr];
	75
	76	simr = &(immr->im_intctl.ic_simrh);
	77	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
	78	simr[word] = ppc_cached_irq_mask[word];
	79	}
	80
	81	static void m8260_unmask_irq (unsigned int irq_nr)
	82	{
6d0f6bcf	83	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
4a9cbbe8 WD	84	int bit, word;
	85	volatile uint *simr;
	86
	87	bit = irq_to_siubit[irq_nr];
	88	word = irq_to_siureg[irq_nr];
	89
	90	simr = &(immr->im_intctl.ic_simrh);
	91	ppc_cached_irq_mask[word] \|= (1 << (31 - bit));
	92	simr[word] = ppc_cached_irq_mask[word];
	93	}
	94
	95	static void m8260_mask_and_ack (unsigned int irq_nr)
	96	{
6d0f6bcf	97	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
4a9cbbe8 WD	98	int bit, word;
	99	volatile uint simr, sipnr;
	100
	101	bit = irq_to_siubit[irq_nr];
	102	word = irq_to_siureg[irq_nr];
	103
	104	simr = &(immr->im_intctl.ic_simrh);
	105	sipnr = &(immr->im_intctl.ic_sipnrh);
	106	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
	107	simr[word] = ppc_cached_irq_mask[word];
	108	sipnr[word] = 1 << (31 - bit);
	109	}
	110
	111	static int m8260_get_irq (struct pt_regs *regs)
	112	{
6d0f6bcf	113	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
4a9cbbe8 WD	114	int irq;
	115	unsigned long bits;
	116
	117	/* For MPC8260, read the SIVEC register and shift the bits down
	118	* to get the irq number. */
	119	bits = immr->im_intctl.ic_sivec;
	120	irq = bits >> 26;
	121	return irq;
	122	}
	123
a47a12be	124	/* end of code ripped out of arch/powerpc/kernel/ppc8260_pic.c */
4a9cbbe8 WD	125	/****************************************************************************/
4a9cbbe8 WD	126
a8c7c708	127	int interrupt_init_cpu (unsigned *decrementer_count)
4a9cbbe8	128	{
6d0f6bcf	129	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
4a9cbbe8	130
6d0f6bcf	131	*decrementer_count = (gd->bus_clk / 4) / CONFIG_SYS_HZ;
4a9cbbe8 WD	132
	133	/* Initialize the default interrupt mapping priorities */
	134	immr->im_intctl.ic_sicr = 0;
	135	immr->im_intctl.ic_siprr = 0x05309770;
	136	immr->im_intctl.ic_scprrh = 0x05309770;
	137	immr->im_intctl.ic_scprrl = 0x05309770;
	138
	139	/* disable all interrupts and clear all pending bits */
	140	immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
	141	immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
	142	immr->im_intctl.ic_sipnrh = 0xffffffff;
	143	immr->im_intctl.ic_sipnrl = 0xffffffff;
	144
6dd652fa WD	145	#ifdef CONFIG_HYMOD
	146	/*
	147	* ensure all external interrupt sources default to trigger on
	148	* high-to-low transition (i.e. edge triggered active low)
	149	*/
	150	immr->im_intctl.ic_siexr = -1;
	151	#endif
	152
4a9cbbe8 WD	153	return (0);
	154	}
	155
	156	/****************************************************************************/
	157
	158	/*
	159	* Handle external interrupts
	160	*/
	161	void external_interrupt (struct pt_regs *regs)
	162	{
	163	int irq, unmask = 1;
	164
	165	irq = m8260_get_irq (regs);
	166
	167	m8260_mask_and_ack (irq);
	168
a8c7c708	169	enable_interrupts ();
4a9cbbe8 WD	170
	171	if (irq_handlers[irq].handler != NULL)
	172	(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
	173	else {
	174	printf ("\nBogus External Interrupt IRQ %d\n", irq);
	175	/*
	176	* turn off the bogus interrupt, otherwise it
	177	* might repeat forever
	178	*/
	179	unmask = 0;
	180	}
	181
	182	if (unmask)
	183	m8260_unmask_irq (irq);
	184	}
	185
	186	/****************************************************************************/
	187
	188	/*
	189	* Install and free an interrupt handler.
	190	*/
	191
	192	void
	193	irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
	194	{
	195	if (irq < 0 \|\| irq >= NR_IRQS) {
	196	printf ("irq_install_handler: bad irq number %d\n", irq);
	197	return;
	198	}
	199
	200	if (irq_handlers[irq].handler != NULL)
	201	printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
	202	(ulong) handler, (ulong) irq_handlers[irq].handler);
	203
	204	irq_handlers[irq].handler = handler;
	205	irq_handlers[irq].arg = arg;
	206
	207	m8260_unmask_irq (irq);
	208	}
	209
	210	void irq_free_handler (int irq)
	211	{
	212	if (irq < 0 \|\| irq >= NR_IRQS) {
	213	printf ("irq_free_handler: bad irq number %d\n", irq);
	214	return;
	215	}
	216
	217	m8260_mask_irq (irq);
	218
	219	irq_handlers[irq].handler = NULL;
	220	irq_handlers[irq].arg = NULL;
	221	}
	222
	223	/****************************************************************************/
	224
a8c7c708	225	void timer_interrupt_cpu (struct pt_regs *regs)
4a9cbbe8	226	{
a8c7c708 WD	227	/* nothing to do here */
a8c7c708 WD	228	return;
4a9cbbe8 WD	229	}
	230
	231	/****************************************************************************/
	232
4431283c	233	#if defined(CONFIG_CMD_IRQ)
4a9cbbe8 WD	234
	235	/* ripped this out of ppc4xx/interrupts.c */
	236
	237	/*******************************************************************************
	238	*
	239	* irqinfo - print information about PCI devices
	240	*
	241	*/
	242	void
54841ab5	243	do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char * const argv[])
4a9cbbe8 WD	244	{
	245	int irq, re_enable;
	246
	247	re_enable = disable_interrupts ();
	248
4b9206ed WD	249	puts ("\nInterrupt-Information:\n"
4b9206ed WD	250	"Nr Routine Arg Count\n");
4a9cbbe8 WD	251
	252	for (irq = 0; irq < 32; irq++)
	253	if (irq_handlers[irq].handler != NULL)
	254	printf ("%02d %08lx %08lx %ld\n", irq,
	255	(ulong) irq_handlers[irq].handler,
	256	(ulong) irq_handlers[irq].arg,
	257	irq_handlers[irq].count);
	258
	259	if (re_enable)
	260	enable_interrupts ();
	261	}
	262
4431283c	263	#endif