[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8260 / pci.c

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (c) 2005 MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 * Added support for PCI bridge on MPC8272ADS
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <pci.h>
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <asm/io.h>
#ifdef CONFIG_OF_LIBFDT
#include <libfdt.h>
#include <fdt_support.h>
#endif

#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
DECLARE_GLOBAL_DATA_PTR;
#endif

/*
 *   Local->PCI map (from CPU)				   controlled by
 *   MPC826x master window
 *
 *   0x80000000 - 0xBFFFFFFF	CPU2PCI space		   PCIBR0
 *   0xF4000000 - 0xF7FFFFFF	CPU2PCI space		   PCIBR1
 *
 *   0x80000000 - 0x9FFFFFFF	0x80000000 - 0x9FFFFFFF	  (Outbound ATU #1)
 *				PCI Mem with prefetch
 *
 *   0xA0000000 - 0xBFFFFFFF	0xA0000000 - 0xBFFFFFFF	  (Outbound ATU #2)
 *				PCI Mem w/o  prefetch
 *
 *   0xF4000000 - 0xF7FFFFFF	0x00000000 - 0x03FFFFFF	  (Outbound ATU #3)
 *				32-bit PCI IO
 *
 *   PCI->Local map (from PCI)
 *   MPC826x slave window				   controlled by
 *
 *   0x00000000 - 0x1FFFFFFF	0x00000000 - 0x1FFFFFFF	  (Inbound ATU #1)
 *				MPC826x local memory
 */

/*
 * Slave window that allows PCI masters to access MPC826x local memory.
 * This window is set up using the first set of Inbound ATU registers
 */

#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE	/* Local base */
#else
#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
#define PCI_SLV_MEM_BUS 0x00000000	/* PCI base */
#else
#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
#endif

#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
#define PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
				 PICMR_PREFETCH_EN)
#else
#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
#endif

/*
 * These are the windows that allow the CPU to access PCI address space.
 * All three PCI master windows, which allow the CPU to access PCI
 * prefetch, non prefetch, and IO space (see below), must all fit within
 * these windows.
 */

/* PCIBR0 */
#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
#define PCI_MSTR0_LOCAL		0x80000000	/* Local base */
#else
#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
#endif

#ifndef CONFIG_SYS_PCIMSK0_MASK
#define PCIMSK0_MASK		PCIMSK_1GB	/* Size of window */
#else
#define PCIMSK0_MASK	CONFIG_SYS_PCIMSK0_MASK
#endif

/* PCIBR1 */
#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
#define PCI_MSTR1_LOCAL		0xF4000000	/* Local base */
#else
#define PCI_MSTR1_LOCAL		CONFIG_SYS_PCI_MSTR1_LOCAL
#endif

#ifndef CONFIG_SYS_PCIMSK1_MASK
#define	 PCIMSK1_MASK		PCIMSK_64MB	/* Size of window */
#else
#define	 PCIMSK1_MASK		CONFIG_SYS_PCIMSK1_MASK
#endif

/*
 * Master window that allows the CPU to access PCI Memory (prefetch).
 * This window will be setup with the first set of Outbound ATU registers
 * in the bridge.
 */

#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
#define PCI_MSTR_MEM_LOCAL 0x80000000	/* Local base */
#else
#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
#define PCI_MSTR_MEM_BUS 0x80000000	/* PCI base   */
#else
#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
#endif

#ifndef CONFIG_SYS_CPU_PCI_MEM_START
#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
#else
#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
#define PCI_MSTR_MEM_SIZE 0x10000000	/* 256MB */
#else
#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
#endif

#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
#define POCMR0_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
#else
#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
#endif

/*
 * Master window that allows the CPU to access PCI Memory (non-prefetch).
 * This window will be setup with the second set of Outbound ATU registers
 * in the bridge.
 */

#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
#else
#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
#define PCI_MSTR_MEMIO_BUS 0x90000000	/* PCI base   */
#else
#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
#endif

#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
#else
#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
#define PCI_MSTR_MEMIO_SIZE 0x10000000	/* 256 MB */
#else
#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
#endif

#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
#define POCMR1_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE)
#else
#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
#endif

/*
 * Master window that allows the CPU to access PCI IO space.
 * This window will be setup with the third set of Outbound ATU registers
 * in the bridge.
 */

#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
#define PCI_MSTR_IO_LOCAL 0xA0000000	/* Local base */
#else
#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
#define PCI_MSTR_IO_BUS 0xA0000000	/* PCI base   */
#else
#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
#endif

#ifndef CONFIG_SYS_CPU_PCI_IO_START
#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
#else
#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
#endif

#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
#define PCI_MSTR_IO_SIZE 0x10000000	/* 256MB */
#else
#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
#endif

#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
#define POCMR2_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
#else
#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
#endif

/* PCI bus configuration registers.
 */

#define PCI_CLASS_BRIDGE_CTLR	0x06


static inline void pci_outl (u32 addr, u32 data)
{
	*(volatile u32 *) addr = cpu_to_le32 (data);
}

void pci_mpc8250_init (struct pci_controller *hose)
{
	u16 tempShort;

	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	pci_dev_t host_devno = PCI_BDF (0, 0, 0);

	pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
			    CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);

	/*
	 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
	 */
#ifdef CONFIG_MPC8266ADS
	immap->im_siu_conf.sc_siumcr =
		(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
		| SIUMCR_LBPC01;
#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
/* nothing to do for this board here */
#elif defined CONFIG_MPC8272
	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
				  ~SIUMCR_BBD &
				  ~SIUMCR_ESE &
				  ~SIUMCR_PBSE &
				  ~SIUMCR_CDIS &
				  ~SIUMCR_DPPC11 &
				  ~SIUMCR_L2CPC11 &
				  ~SIUMCR_LBPC11 &
				  ~SIUMCR_APPC11 &
				  ~SIUMCR_CS10PC11 &
				  ~SIUMCR_BCTLC11 &
				  ~SIUMCR_MMR11)
				  | SIUMCR_DPPC11
				  | SIUMCR_L2CPC01
				  | SIUMCR_LBPC00
				  | SIUMCR_APPC10
				  | SIUMCR_CS10PC00
				  | SIUMCR_BCTLC00
				  | SIUMCR_MMR11;
#elif defined(CONFIG_TQM8272)
/* nothing to do for this Board here */
#else
	/*
	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
	 * and local bus for PCI (SIUMCR [LBPC]).
	 */
	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
						~SIUMCR_LBPC11 &
						~SIUMCR_CS10PC11 &
						~SIUMCR_LBPC11) |
					SIUMCR_LBPC01 |
					SIUMCR_CS10PC01 |
					SIUMCR_APPC10;
#endif

	/* Make PCI lowest priority */
	/* Each 4 bits is a device bus request	and the MS 4bits
	   is highest priority */
	/* Bus		     4bit value
	   ---		     ----------
	   CPM high	     0b0000
	   CPM middle	     0b0001
	   CPM low	     0b0010
	   PCI reguest	     0b0011
	   Reserved	     0b0100
	   Reserved	     0b0101
	   Internal Core     0b0110
	   External Master 1 0b0111
	   External Master 2 0b1000
	   External Master 3 0b1001
	   The rest are reserved */
	immap->im_siu_conf.sc_ppc_alrh = 0x61207893;

	/* Park bus on core while modifying PCI Bus accesses */
	immap->im_siu_conf.sc_ppc_acr = 0x6;

	/*
	 * Set up master windows that allow the CPU to access PCI space. These
	 * windows are set up using the two SIU PCIBR registers.
	 */
	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;

#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
	immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
	immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
#endif

	/* Release PCI RST (by default the PCI RST signal is held low)	*/
	immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);

	/* give it some time */
	{
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
		/* Give the PCI cards more time to initialize before query
		   This might be good for other boards also
		 */
		int i;

		for (i = 0; i < 1000; ++i)
#endif
			udelay (1000);
	}

	/*
	 * Set up master window that allows the CPU to access PCI Memory (prefetch)
	 * space. This window is set up using the first set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12);	/* PCI base */
	immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
	 * space. This window is set up using the second set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12);	/* PCI base */
	immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up master window that allows the CPU to access PCI IO space. This window
	 * is set up using the third set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
	immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up slave window that allows PCI masters to access MPC826x local memory.
	 * This window is set up using the first set of Inbound ATU registers
	 */
	immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12);	/* PCI base */
	immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);	/* Size & attribute */

	/* See above for description - puts PCI request as highest priority */
#ifdef CONFIG_MPC8272
	immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
#else
	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
#endif

	/* Park the bus on the PCI */
	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;

	/* Host mode - specify the bridge as a host-PCI bridge */

	pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
				    PCI_CLASS_BRIDGE_CTLR);

	/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
	pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
	pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
				    tempShort | PCI_COMMAND_MASTER |
				    PCI_COMMAND_MEMORY);

	/* do some bridge init, should be done on all 8260 based bridges */
	pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
				    0x08);
	pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
				    0xF8);

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* System memory space */
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
	pci_set_region (hose->regions + 0,
			PCI_SLV_MEM_BUS,
			PCI_SLV_MEM_LOCAL,
			gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
#else
	pci_set_region (hose->regions + 0,
			CONFIG_SYS_SDRAM_BASE,
			CONFIG_SYS_SDRAM_BASE,
			0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
#endif

	/* PCI memory space */
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
	pci_set_region (hose->regions + 1,
			PCI_MSTR_MEMIO_BUS,
			PCI_MSTR_MEMIO_LOCAL,
			PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
#else
	pci_set_region (hose->regions + 1,
			PCI_MSTR_MEM_BUS,
			PCI_MSTR_MEM_LOCAL,
			PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
#endif

	/* PCI I/O space */
	pci_set_region (hose->regions + 2,
			PCI_MSTR_IO_BUS,
			PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);

	hose->region_count = 3;

	pci_register_hose (hose);
	/* Mask off master abort machine checks */
	immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
	eieio ();

	hose->last_busno = pci_hose_scan (hose);


	/* clear the error in the error status register */
	immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);

	/* unmask master abort machine checks */
	immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
}

#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{
	do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
		"clock-frequency", gd->pci_clk, 1);
}
#endif

#endif /* CONFIG_PCI */
Commit	Line	Data
4d75a504 WD	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
716c1dcb	5	* Copyright (c) 2005 MontaVista Software, Inc.
1972dc0a WD	6	* Vitaly Bordug <vbordug@ru.mvista.com>
	7	* Added support for PCI bridge on MPC8272ADS
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
4d75a504 WD	10	*/
	11
	12	#include <common.h>
	13
	14	#ifdef CONFIG_PCI
	15
	16	#include <pci.h>
5d232d0e	17	#include <mpc8260.h>
4d75a504	18	#include <asm/m8260_pci.h>
3c74e32a	19	#include <asm/io.h>
0e6989b9 MI	20	#ifdef CONFIG_OF_LIBFDT
	21	#include <libfdt.h>
	22	#include <fdt_support.h>
	23	#endif
d87080b7	24
392c252e	25	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272 \|\| defined CONFIG_PM826
d87080b7 WD	26	DECLARE_GLOBAL_DATA_PTR;
	27	#endif
	28
4d75a504	29	/*
3c74e32a	30	* Local->PCI map (from CPU) controlled by
4d75a504 WD	31	* MPC826x master window
4d75a504 WD	32	*
3c74e32a WD	33	* 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
3c74e32a WD	34	* 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
8bde7f77	35	*
3c74e32a WD	36	* 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
3c74e32a WD	37	* PCI Mem with prefetch
5d232d0e	38	*
3c74e32a WD	39	* 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
3c74e32a WD	40	* PCI Mem w/o prefetch
5d232d0e	41	*
3c74e32a WD	42	* 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
3c74e32a WD	43	* 32-bit PCI IO
8bde7f77	44	*
4d75a504	45	* PCI->Local map (from PCI)
3c74e32a	46	* MPC826x slave window controlled by
4d75a504	47	*
3c74e32a WD	48	* 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
3c74e32a WD	49	* MPC826x local memory
4d75a504 WD	50	*/
4d75a504 WD	51
8bde7f77 WD	52	/*
8bde7f77 WD	53	* Slave window that allows PCI masters to access MPC826x local memory.
4d75a504 WD	54	* This window is set up using the first set of Inbound ATU registers
	55	*/
	56
6d0f6bcf JCPV	57	#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
6d0f6bcf JCPV	58	#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
8bde7f77	59	#else
6d0f6bcf	60	#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
5d232d0e WD	61	#endif
5d232d0e WD	62
6d0f6bcf	63	#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
3c74e32a	64	#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
5d232d0e	65	#else
6d0f6bcf	66	#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
5d232d0e WD	67	#endif
5d232d0e WD	68
6d0f6bcf	69	#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
4d75a504	70	#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB \| PICMR_ENABLE \| \
8bde7f77	71	PICMR_PREFETCH_EN)
5d232d0e	72	#else
6d0f6bcf	73	#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
5d232d0e	74	#endif
4d75a504	75
8bde7f77	76	/*
5d232d0e	77	* These are the windows that allow the CPU to access PCI address space.
8bde7f77 WD	78	* All three PCI master windows, which allow the CPU to access PCI
8bde7f77 WD	79	* prefetch, non prefetch, and IO space (see below), must all fit within
5d232d0e	80	* these windows.
4d75a504 WD	81	*/
4d75a504 WD	82
5d232d0e	83	/* PCIBR0 */
6d0f6bcf	84	#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
3c74e32a	85	#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
8bde7f77	86	#else
6d0f6bcf	87	#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
5d232d0e WD	88	#endif
5d232d0e WD	89
6d0f6bcf	90	#ifndef CONFIG_SYS_PCIMSK0_MASK
3c74e32a	91	#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
5d232d0e	92	#else
6d0f6bcf	93	#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK
5d232d0e WD	94	#endif
	95
	96	/* PCIBR1 */
6d0f6bcf	97	#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
3c74e32a	98	#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
8bde7f77	99	#else
6d0f6bcf	100	#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL
5d232d0e WD	101	#endif
5d232d0e WD	102
6d0f6bcf	103	#ifndef CONFIG_SYS_PCIMSK1_MASK
3c74e32a	104	#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
5d232d0e	105	#else
6d0f6bcf	106	#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK
5d232d0e	107	#endif
4d75a504	108
8bde7f77	109	/*
4d75a504 WD	110	* Master window that allows the CPU to access PCI Memory (prefetch).
	111	* This window will be setup with the first set of Outbound ATU registers
	112	* in the bridge.
	113	*/
	114
6d0f6bcf	115	#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
3c74e32a	116	#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
5d232d0e	117	#else
6d0f6bcf	118	#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
5d232d0e WD	119	#endif
5d232d0e WD	120
6d0f6bcf	121	#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
3c74e32a	122	#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
5d232d0e	123	#else
6d0f6bcf	124	#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
5d232d0e WD	125	#endif
5d232d0e WD	126
6d0f6bcf	127	#ifndef CONFIG_SYS_CPU_PCI_MEM_START
5d232d0e WD	128	#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
5d232d0e WD	129	#else
6d0f6bcf	130	#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
5d232d0e WD	131	#endif
5d232d0e WD	132
6d0f6bcf	133	#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
3c74e32a	134	#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
5d232d0e	135	#else
6d0f6bcf	136	#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
5d232d0e WD	137	#endif
5d232d0e WD	138
6d0f6bcf	139	#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
4d75a504	140	#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB \| POCMR_ENABLE \| POCMR_PREFETCH_EN)
5d232d0e	141	#else
6d0f6bcf	142	#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
5d232d0e	143	#endif
4d75a504	144
8bde7f77	145	/*
4d75a504 WD	146	* Master window that allows the CPU to access PCI Memory (non-prefetch).
	147	* This window will be setup with the second set of Outbound ATU registers
	148	* in the bridge.
	149	*/
	150
6d0f6bcf	151	#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
3c74e32a	152	#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
8bde7f77	153	#else
6d0f6bcf	154	#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
5d232d0e WD	155	#endif
5d232d0e WD	156
6d0f6bcf	157	#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
3c74e32a	158	#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
8bde7f77	159	#else
6d0f6bcf	160	#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
5d232d0e WD	161	#endif
5d232d0e WD	162
6d0f6bcf	163	#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
8bde7f77 WD	164	#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
8bde7f77 WD	165	#else
6d0f6bcf	166	#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
5d232d0e WD	167	#endif
5d232d0e WD	168
6d0f6bcf	169	#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
3c74e32a	170	#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
8bde7f77	171	#else
6d0f6bcf	172	#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
5d232d0e WD	173	#endif
5d232d0e WD	174
6d0f6bcf	175	#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
3c74e32a	176	#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB \| POCMR_ENABLE)
5d232d0e	177	#else
6d0f6bcf	178	#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
5d232d0e	179	#endif
4d75a504	180
8bde7f77	181	/*
4d75a504 WD	182	* Master window that allows the CPU to access PCI IO space.
	183	* This window will be setup with the third set of Outbound ATU registers
	184	* in the bridge.
	185	*/
	186
6d0f6bcf	187	#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
3c74e32a	188	#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
8bde7f77	189	#else
6d0f6bcf	190	#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
5d232d0e WD	191	#endif
5d232d0e WD	192
6d0f6bcf	193	#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
3c74e32a	194	#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
8bde7f77	195	#else
6d0f6bcf	196	#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
5d232d0e WD	197	#endif
5d232d0e WD	198
6d0f6bcf	199	#ifndef CONFIG_SYS_CPU_PCI_IO_START
8bde7f77 WD	200	#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
8bde7f77 WD	201	#else
6d0f6bcf	202	#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
5d232d0e WD	203	#endif
5d232d0e WD	204
6d0f6bcf	205	#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
3c74e32a	206	#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
8bde7f77	207	#else
6d0f6bcf	208	#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
66fd3d1c	209	#endif
5d232d0e	210
6d0f6bcf	211	#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
3c74e32a	212	#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB \| POCMR_ENABLE \| POCMR_PCI_IO)
5d232d0e	213	#else
6d0f6bcf	214	#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
5d232d0e	215	#endif
4d75a504 WD	216
	217	/* PCI bus configuration registers.
	218	*/
	219
	220	#define PCI_CLASS_BRIDGE_CTLR 0x06
	221
	222
3c74e32a	223	static inline void pci_outl (u32 addr, u32 data)
4d75a504	224	{
3c74e32a	225	(volatile u32 ) addr = cpu_to_le32 (data);
4d75a504 WD	226	}
4d75a504 WD	227
3c74e32a	228	void pci_mpc8250_init (struct pci_controller *hose)
4d75a504	229	{
3c74e32a WD	230	u16 tempShort;
3c74e32a WD	231
6d0f6bcf	232	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
3c74e32a	233	pci_dev_t host_devno = PCI_BDF (0, 0, 0);
4d75a504	234
6d0f6bcf JCPV	235	pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
6d0f6bcf JCPV	236	CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);
4d75a504	237
3c74e32a WD	238	/*
	239	* Setting required to enable local bus for PCI (SIUMCR [LBPC]).
	240	*/
5d232d0e	241	#ifdef CONFIG_MPC8266ADS
3c74e32a WD	242	immap->im_siu_conf.sc_siumcr =
	243	(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
	244	\| SIUMCR_LBPC01;
8701ecef SW	245	#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
8701ecef SW	246	/* nothing to do for this board here */
1972dc0a	247	#elif defined CONFIG_MPC8272
716c1dcb WD	248	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
	249	~SIUMCR_BBD &
	250	~SIUMCR_ESE &
	251	~SIUMCR_PBSE &
	252	~SIUMCR_CDIS &
	253	~SIUMCR_DPPC11 &
	254	~SIUMCR_L2CPC11 &
	255	~SIUMCR_LBPC11 &
	256	~SIUMCR_APPC11 &
	257	~SIUMCR_CS10PC11 &
	258	~SIUMCR_BCTLC11 &
	259	~SIUMCR_MMR11)
	260	\| SIUMCR_DPPC11
	261	\| SIUMCR_L2CPC01
	262	\| SIUMCR_LBPC00
	263	\| SIUMCR_APPC10
	264	\| SIUMCR_CS10PC00
	265	\| SIUMCR_BCTLC00
	266	\| SIUMCR_MMR11;
fa230445	267	#elif defined(CONFIG_TQM8272)
07e82cb2	268	/* nothing to do for this Board here */
5d232d0e	269	#else
3c74e32a WD	270	/*
	271	* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
	272	* and local bus for PCI (SIUMCR [LBPC]).
	273	*/
	274	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
	275	~SIUMCR_LBPC11 &
8bde7f77	276	~SIUMCR_CS10PC11 &
3c74e32a WD	277	~SIUMCR_LBPC11) \|
	278	SIUMCR_LBPC01 \|
	279	SIUMCR_CS10PC01 \|
	280	SIUMCR_APPC10;
5d232d0e	281	#endif
4d75a504	282
3c74e32a WD	283	/* Make PCI lowest priority */
	284	/* Each 4 bits is a device bus request and the MS 4bits
	285	is highest priority */
	286	/* Bus 4bit value
	287	--- ----------
	288	CPM high 0b0000
	289	CPM middle 0b0001
	290	CPM low 0b0010
	291	PCI reguest 0b0011
	292	Reserved 0b0100
	293	Reserved 0b0101
	294	Internal Core 0b0110
	295	External Master 1 0b0111
	296	External Master 2 0b1000
	297	External Master 3 0b1001
	298	The rest are reserved */
	299	immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
	300
	301	/* Park bus on core while modifying PCI Bus accesses */
	302	immap->im_siu_conf.sc_ppc_acr = 0x6;
	303
	304	/*
	305	* Set up master windows that allow the CPU to access PCI space. These
	306	* windows are set up using the two SIU PCIBR registers.
	307	*/
	308	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
	309	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL \| PCIBR_ENABLE;
5d232d0e	310
1972dc0a	311	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272
d4326aca WD	312	immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
d4326aca WD	313	immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL \| PCIBR_ENABLE;
8bde7f77	314	#endif
4d75a504	315
3c74e32a WD	316	/* Release PCI RST (by default the PCI RST signal is held low) */
3c74e32a WD	317	immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
4d75a504	318
3c74e32a WD	319	/* give it some time */
3c74e32a WD	320	{
1972dc0a	321	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272
8bde7f77	322	/* Give the PCI cards more time to initialize before query
3c74e32a WD	323	This might be good for other boards also
	324	*/
	325	int i;
	326
	327	for (i = 0; i < 1000; ++i)
5d232d0e	328	#endif
3c74e32a WD	329	udelay (1000);
	330	}
	331
	332	/*
	333	* Set up master window that allows the CPU to access PCI Memory (prefetch)
	334	* space. This window is set up using the first set of Outbound ATU registers.
	335	*/
	336	immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
	337	immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
	338	immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
	339
	340	/*
	341	* Set up master window that allows the CPU to access PCI Memory (non-prefetch)
	342	* space. This window is set up using the second set of Outbound ATU registers.
	343	*/
	344	immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
	345	immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
	346	immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
	347
	348	/*
	349	* Set up master window that allows the CPU to access PCI IO space. This window
	350	* is set up using the third set of Outbound ATU registers.
	351	*/
	352	immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
	353	immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
	354	immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
	355
	356	/*
	357	* Set up slave window that allows PCI masters to access MPC826x local memory.
	358	* This window is set up using the first set of Inbound ATU registers
	359	*/
	360	immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
	361	immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
	362	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
	363
	364	/* See above for description - puts PCI request as highest priority */
1972dc0a WD	365	#ifdef CONFIG_MPC8272
	366	immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
	367	#else
3c74e32a	368	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
1972dc0a	369	#endif
3c74e32a WD	370
	371	/* Park the bus on the PCI */
	372	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
	373
	374	/* Host mode - specify the bridge as a host-PCI bridge */
	375
	376	pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
	377	PCI_CLASS_BRIDGE_CTLR);
	378
	379	/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
	380	pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
	381	pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
	382	tempShort \| PCI_COMMAND_MASTER \|
	383	PCI_COMMAND_MEMORY);
4d75a504	384
7a8e9bed	385	/* do some bridge init, should be done on all 8260 based bridges */
3c74e32a WD	386	pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
	387	0x08);
	388	pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
	389	0xF8);
7a8e9bed	390
3c74e32a WD	391	hose->first_busno = 0;
3c74e32a WD	392	hose->last_busno = 0xff;
4d75a504	393
3c74e32a	394	/* System memory space */
392c252e	395	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272 \|\| defined CONFIG_PM826
3c74e32a WD	396	pci_set_region (hose->regions + 0,
	397	PCI_SLV_MEM_BUS,
	398	PCI_SLV_MEM_LOCAL,
ff4e66e9	399	gd->ram_size, PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY);
5d232d0e	400	#else
3c74e32a	401	pci_set_region (hose->regions + 0,
6d0f6bcf JCPV	402	CONFIG_SYS_SDRAM_BASE,
6d0f6bcf JCPV	403	CONFIG_SYS_SDRAM_BASE,
ff4e66e9	404	0x4000000, PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY);
5d232d0e	405	#endif
4d75a504	406
3c74e32a	407	/* PCI memory space */
716c1dcb	408	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272
3c74e32a WD	409	pci_set_region (hose->regions + 1,
	410	PCI_MSTR_MEMIO_BUS,
	411	PCI_MSTR_MEMIO_LOCAL,
	412	PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
5d232d0e	413	#else
3c74e32a WD	414	pci_set_region (hose->regions + 1,
	415	PCI_MSTR_MEM_BUS,
	416	PCI_MSTR_MEM_LOCAL,
	417	PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
5d232d0e	418	#endif
4d75a504	419
3c74e32a WD	420	/* PCI I/O space */
	421	pci_set_region (hose->regions + 2,
	422	PCI_MSTR_IO_BUS,
	423	PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
	424
	425	hose->region_count = 3;
	426
	427	pci_register_hose (hose);
	428	/* Mask off master abort machine checks */
	429	immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
	430	eieio ();
	431
	432	hose->last_busno = pci_hose_scan (hose);
4d75a504	433
4d75a504	434
3c74e32a WD	435	/* clear the error in the error status register */
3c74e32a WD	436	immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
4d75a504	437
3c74e32a WD	438	/* unmask master abort machine checks */
3c74e32a WD	439	immap->im_pci.pci_emr \|= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
4d75a504 WD	440	}
4d75a504 WD	441
0e6989b9 MI	442	#if defined(CONFIG_OF_LIBFDT)
	443	void ft_pci_setup(void blob, bd_t bd)
	444	{
	445	do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
52b047ae	446	"clock-frequency", gd->pci_clk, 1);
0e6989b9 MI	447	}
	448	#endif
	449
3c74e32a	450	#endif /* CONFIG_PCI */