[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8260 / pci.c

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Copyright (c) 2005 MontaVista Software, Inc.
 * Vitaly Bordug <vbordug@ru.mvista.com>
 * Added support for PCI bridge on MPC8272ADS
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>

#ifdef CONFIG_PCI

#include <pci.h>
#include <mpc8260.h>
#include <asm/m8260_pci.h>
#include <asm/io.h>
#ifdef CONFIG_OF_LIBFDT
#include <libfdt.h>
#include <fdt_support.h>
#endif

#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
DECLARE_GLOBAL_DATA_PTR;
#endif

/*
 *   Local->PCI map (from CPU)				   controlled by
 *   MPC826x master window
 *
 *   0x80000000 - 0xBFFFFFFF	CPU2PCI space		   PCIBR0
 *   0xF4000000 - 0xF7FFFFFF	CPU2PCI space		   PCIBR1
 *
 *   0x80000000 - 0x9FFFFFFF	0x80000000 - 0x9FFFFFFF	  (Outbound ATU #1)
 *				PCI Mem with prefetch
 *
 *   0xA0000000 - 0xBFFFFFFF	0xA0000000 - 0xBFFFFFFF	  (Outbound ATU #2)
 *				PCI Mem w/o  prefetch
 *
 *   0xF4000000 - 0xF7FFFFFF	0x00000000 - 0x03FFFFFF	  (Outbound ATU #3)
 *				32-bit PCI IO
 *
 *   PCI->Local map (from PCI)
 *   MPC826x slave window				   controlled by
 *
 *   0x00000000 - 0x1FFFFFFF	0x00000000 - 0x1FFFFFFF	  (Inbound ATU #1)
 *				MPC826x local memory
 */

/*
 * Slave window that allows PCI masters to access MPC826x local memory.
 * This window is set up using the first set of Inbound ATU registers
 */

#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE	/* Local base */
#else
#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
#define PCI_SLV_MEM_BUS 0x00000000	/* PCI base */
#else
#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
#endif

#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
#define PICMR0_MASK_ATTRIB	(PICMR_MASK_512MB | PICMR_ENABLE | \
				 PICMR_PREFETCH_EN)
#else
#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
#endif

/*
 * These are the windows that allow the CPU to access PCI address space.
 * All three PCI master windows, which allow the CPU to access PCI
 * prefetch, non prefetch, and IO space (see below), must all fit within
 * these windows.
 */

/* PCIBR0 */
#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
#define PCI_MSTR0_LOCAL		0x80000000	/* Local base */
#else
#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
#endif

#ifndef CONFIG_SYS_PCIMSK0_MASK
#define PCIMSK0_MASK		PCIMSK_1GB	/* Size of window */
#else
#define PCIMSK0_MASK	CONFIG_SYS_PCIMSK0_MASK
#endif

/* PCIBR1 */
#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
#define PCI_MSTR1_LOCAL		0xF4000000	/* Local base */
#else
#define PCI_MSTR1_LOCAL		CONFIG_SYS_PCI_MSTR1_LOCAL
#endif

#ifndef CONFIG_SYS_PCIMSK1_MASK
#define	 PCIMSK1_MASK		PCIMSK_64MB	/* Size of window */
#else
#define	 PCIMSK1_MASK		CONFIG_SYS_PCIMSK1_MASK
#endif

/*
 * Master window that allows the CPU to access PCI Memory (prefetch).
 * This window will be setup with the first set of Outbound ATU registers
 * in the bridge.
 */

#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
#define PCI_MSTR_MEM_LOCAL 0x80000000	/* Local base */
#else
#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
#define PCI_MSTR_MEM_BUS 0x80000000	/* PCI base   */
#else
#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
#endif

#ifndef CONFIG_SYS_CPU_PCI_MEM_START
#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
#else
#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
#define PCI_MSTR_MEM_SIZE 0x10000000	/* 256MB */
#else
#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
#endif

#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
#define POCMR0_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
#else
#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
#endif

/*
 * Master window that allows the CPU to access PCI Memory (non-prefetch).
 * This window will be setup with the second set of Outbound ATU registers
 * in the bridge.
 */

#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
#else
#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
#define PCI_MSTR_MEMIO_BUS 0x90000000	/* PCI base   */
#else
#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
#endif

#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
#else
#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
#endif

#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
#define PCI_MSTR_MEMIO_SIZE 0x10000000	/* 256 MB */
#else
#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
#endif

#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
#define POCMR1_MASK_ATTRIB	(POCMR_MASK_512MB | POCMR_ENABLE)
#else
#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
#endif

/*
 * Master window that allows the CPU to access PCI IO space.
 * This window will be setup with the third set of Outbound ATU registers
 * in the bridge.
 */

#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
#define PCI_MSTR_IO_LOCAL 0xA0000000	/* Local base */
#else
#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
#endif

#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
#define PCI_MSTR_IO_BUS 0xA0000000	/* PCI base   */
#else
#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
#endif

#ifndef CONFIG_SYS_CPU_PCI_IO_START
#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
#else
#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
#endif

#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
#define PCI_MSTR_IO_SIZE 0x10000000	/* 256MB */
#else
#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
#endif

#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
#define POCMR2_MASK_ATTRIB	(POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
#else
#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
#endif

/* PCI bus configuration registers.
 */

#define PCI_CLASS_BRIDGE_CTLR	0x06


static inline void pci_outl (u32 addr, u32 data)
{
	*(volatile u32 *) addr = cpu_to_le32 (data);
}

void pci_mpc8250_init (struct pci_controller *hose)
{
	u16 tempShort;

	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	pci_dev_t host_devno = PCI_BDF (0, 0, 0);

	pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
			    CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);

	/*
	 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
	 */
#ifdef CONFIG_MPC8266ADS
	immap->im_siu_conf.sc_siumcr =
		(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
		| SIUMCR_LBPC01;
#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
/* nothing to do for this board here */
#elif defined CONFIG_MPC8272
	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
				  ~SIUMCR_BBD &
				  ~SIUMCR_ESE &
				  ~SIUMCR_PBSE &
				  ~SIUMCR_CDIS &
				  ~SIUMCR_DPPC11 &
				  ~SIUMCR_L2CPC11 &
				  ~SIUMCR_LBPC11 &
				  ~SIUMCR_APPC11 &
				  ~SIUMCR_CS10PC11 &
				  ~SIUMCR_BCTLC11 &
				  ~SIUMCR_MMR11)
				  | SIUMCR_DPPC11
				  | SIUMCR_L2CPC01
				  | SIUMCR_LBPC00
				  | SIUMCR_APPC10
				  | SIUMCR_CS10PC00
				  | SIUMCR_BCTLC00
				  | SIUMCR_MMR11;
#elif defined(CONFIG_TQM8272)
/* nothing to do for this Board here */
#else
	/*
	 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
	 * and local bus for PCI (SIUMCR [LBPC]).
	 */
	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
						~SIUMCR_LBPC11 &
						~SIUMCR_CS10PC11 &
						~SIUMCR_LBPC11) |
					SIUMCR_LBPC01 |
					SIUMCR_CS10PC01 |
					SIUMCR_APPC10;
#endif

	/* Make PCI lowest priority */
	/* Each 4 bits is a device bus request	and the MS 4bits
	   is highest priority */
	/* Bus		     4bit value
	   ---		     ----------
	   CPM high	     0b0000
	   CPM middle	     0b0001
	   CPM low	     0b0010
	   PCI reguest	     0b0011
	   Reserved	     0b0100
	   Reserved	     0b0101
	   Internal Core     0b0110
	   External Master 1 0b0111
	   External Master 2 0b1000
	   External Master 3 0b1001
	   The rest are reserved */
	immap->im_siu_conf.sc_ppc_alrh = 0x61207893;

	/* Park bus on core while modifying PCI Bus accesses */
	immap->im_siu_conf.sc_ppc_acr = 0x6;

	/*
	 * Set up master windows that allow the CPU to access PCI space. These
	 * windows are set up using the two SIU PCIBR registers.
	 */
	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;

#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
	immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
	immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
#endif

	/* Release PCI RST (by default the PCI RST signal is held low)	*/
	immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);

	/* give it some time */
	{
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
		/* Give the PCI cards more time to initialize before query
		   This might be good for other boards also
		 */
		int i;

		for (i = 0; i < 1000; ++i)
#endif
			udelay (1000);
	}

	/*
	 * Set up master window that allows the CPU to access PCI Memory (prefetch)
	 * space. This window is set up using the first set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12);	/* PCI base */
	immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
	 * space. This window is set up using the second set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12);	/* PCI base */
	immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up master window that allows the CPU to access PCI IO space. This window
	 * is set up using the third set of Outbound ATU registers.
	 */
	immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
	immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12);	/* Local base */
	immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB);	/* Size & attribute */

	/*
	 * Set up slave window that allows PCI masters to access MPC826x local memory.
	 * This window is set up using the first set of Inbound ATU registers
	 */
	immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12);	/* PCI base */
	immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB);	/* Size & attribute */

	/* See above for description - puts PCI request as highest priority */
#ifdef CONFIG_MPC8272
	immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
#else
	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
#endif

	/* Park the bus on the PCI */
	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;

	/* Host mode - specify the bridge as a host-PCI bridge */

	pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
				    PCI_CLASS_BRIDGE_CTLR);

	/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
	pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
	pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
				    tempShort | PCI_COMMAND_MASTER |
				    PCI_COMMAND_MEMORY);

	/* do some bridge init, should be done on all 8260 based bridges */
	pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
				    0x08);
	pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
				    0xF8);

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	/* System memory space */
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826
	pci_set_region (hose->regions + 0,
			PCI_SLV_MEM_BUS,
			PCI_SLV_MEM_LOCAL,
			gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
#else
	pci_set_region (hose->regions + 0,
			CONFIG_SYS_SDRAM_BASE,
			CONFIG_SYS_SDRAM_BASE,
			0x4000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
#endif

	/* PCI memory space */
#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
	pci_set_region (hose->regions + 1,
			PCI_MSTR_MEMIO_BUS,
			PCI_MSTR_MEMIO_LOCAL,
			PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
#else
	pci_set_region (hose->regions + 1,
			PCI_MSTR_MEM_BUS,
			PCI_MSTR_MEM_LOCAL,
			PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
#endif

	/* PCI I/O space */
	pci_set_region (hose->regions + 2,
			PCI_MSTR_IO_BUS,
			PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);

	hose->region_count = 3;

	pci_register_hose (hose);
	/* Mask off master abort machine checks */
	immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
	eieio ();

	hose->last_busno = pci_hose_scan (hose);


	/* clear the error in the error status register */
	immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);

	/* unmask master abort machine checks */
	immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
}

#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{
	do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
		"clock-frequency", gd->pci_clk, 1);
}
#endif

#endif /* CONFIG_PCI */
Commit	Line	Data
4d75a504 WD	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
716c1dcb	5	* Copyright (c) 2005 MontaVista Software, Inc.
1972dc0a WD	6	* Vitaly Bordug <vbordug@ru.mvista.com>
	7	* Added support for PCI bridge on MPC8272ADS
	8	*
4d75a504 WD	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <common.h>
	29
	30	#ifdef CONFIG_PCI
	31
	32	#include <pci.h>
5d232d0e	33	#include <mpc8260.h>
4d75a504	34	#include <asm/m8260_pci.h>
3c74e32a	35	#include <asm/io.h>
0e6989b9 MI	36	#ifdef CONFIG_OF_LIBFDT
	37	#include <libfdt.h>
	38	#include <fdt_support.h>
	39	#endif
d87080b7	40
392c252e	41	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272 \|\| defined CONFIG_PM826
d87080b7 WD	42	DECLARE_GLOBAL_DATA_PTR;
	43	#endif
	44
4d75a504	45	/*
3c74e32a	46	* Local->PCI map (from CPU) controlled by
4d75a504 WD	47	* MPC826x master window
4d75a504 WD	48	*
3c74e32a WD	49	* 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
3c74e32a WD	50	* 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
8bde7f77	51	*
3c74e32a WD	52	* 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
3c74e32a WD	53	* PCI Mem with prefetch
5d232d0e	54	*
3c74e32a WD	55	* 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
3c74e32a WD	56	* PCI Mem w/o prefetch
5d232d0e	57	*
3c74e32a WD	58	* 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
3c74e32a WD	59	* 32-bit PCI IO
8bde7f77	60	*
4d75a504	61	* PCI->Local map (from PCI)
3c74e32a	62	* MPC826x slave window controlled by
4d75a504	63	*
3c74e32a WD	64	* 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
3c74e32a WD	65	* MPC826x local memory
4d75a504 WD	66	*/
4d75a504 WD	67
8bde7f77 WD	68	/*
8bde7f77 WD	69	* Slave window that allows PCI masters to access MPC826x local memory.
4d75a504 WD	70	* This window is set up using the first set of Inbound ATU registers
	71	*/
	72
6d0f6bcf JCPV	73	#ifndef CONFIG_SYS_PCI_SLV_MEM_LOCAL
6d0f6bcf JCPV	74	#define PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
8bde7f77	75	#else
6d0f6bcf	76	#define PCI_SLV_MEM_LOCAL CONFIG_SYS_PCI_SLV_MEM_LOCAL
5d232d0e WD	77	#endif
5d232d0e WD	78
6d0f6bcf	79	#ifndef CONFIG_SYS_PCI_SLV_MEM_BUS
3c74e32a	80	#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
5d232d0e	81	#else
6d0f6bcf	82	#define PCI_SLV_MEM_BUS CONFIG_SYS_PCI_SLV_MEM_BUS
5d232d0e WD	83	#endif
5d232d0e WD	84
6d0f6bcf	85	#ifndef CONFIG_SYS_PICMR0_MASK_ATTRIB
4d75a504	86	#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB \| PICMR_ENABLE \| \
8bde7f77	87	PICMR_PREFETCH_EN)
5d232d0e	88	#else
6d0f6bcf	89	#define PICMR0_MASK_ATTRIB CONFIG_SYS_PICMR0_MASK_ATTRIB
5d232d0e	90	#endif
4d75a504	91
8bde7f77	92	/*
5d232d0e	93	* These are the windows that allow the CPU to access PCI address space.
8bde7f77 WD	94	* All three PCI master windows, which allow the CPU to access PCI
8bde7f77 WD	95	* prefetch, non prefetch, and IO space (see below), must all fit within
5d232d0e	96	* these windows.
4d75a504 WD	97	*/
4d75a504 WD	98
5d232d0e	99	/* PCIBR0 */
6d0f6bcf	100	#ifndef CONFIG_SYS_PCI_MSTR0_LOCAL
3c74e32a	101	#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
8bde7f77	102	#else
6d0f6bcf	103	#define PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR0_LOCAL
5d232d0e WD	104	#endif
5d232d0e WD	105
6d0f6bcf	106	#ifndef CONFIG_SYS_PCIMSK0_MASK
3c74e32a	107	#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
5d232d0e	108	#else
6d0f6bcf	109	#define PCIMSK0_MASK CONFIG_SYS_PCIMSK0_MASK
5d232d0e WD	110	#endif
	111
	112	/* PCIBR1 */
6d0f6bcf	113	#ifndef CONFIG_SYS_PCI_MSTR1_LOCAL
3c74e32a	114	#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
8bde7f77	115	#else
6d0f6bcf	116	#define PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR1_LOCAL
5d232d0e WD	117	#endif
5d232d0e WD	118
6d0f6bcf	119	#ifndef CONFIG_SYS_PCIMSK1_MASK
3c74e32a	120	#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
5d232d0e	121	#else
6d0f6bcf	122	#define PCIMSK1_MASK CONFIG_SYS_PCIMSK1_MASK
5d232d0e	123	#endif
4d75a504	124
8bde7f77	125	/*
4d75a504 WD	126	* Master window that allows the CPU to access PCI Memory (prefetch).
	127	* This window will be setup with the first set of Outbound ATU registers
	128	* in the bridge.
	129	*/
	130
6d0f6bcf	131	#ifndef CONFIG_SYS_PCI_MSTR_MEM_LOCAL
3c74e32a	132	#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
5d232d0e	133	#else
6d0f6bcf	134	#define PCI_MSTR_MEM_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
5d232d0e WD	135	#endif
5d232d0e WD	136
6d0f6bcf	137	#ifndef CONFIG_SYS_PCI_MSTR_MEM_BUS
3c74e32a	138	#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
5d232d0e	139	#else
6d0f6bcf	140	#define PCI_MSTR_MEM_BUS CONFIG_SYS_PCI_MSTR_MEM_BUS
5d232d0e WD	141	#endif
5d232d0e WD	142
6d0f6bcf	143	#ifndef CONFIG_SYS_CPU_PCI_MEM_START
5d232d0e WD	144	#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
5d232d0e WD	145	#else
6d0f6bcf	146	#define CPU_PCI_MEM_START CONFIG_SYS_CPU_PCI_MEM_START
5d232d0e WD	147	#endif
5d232d0e WD	148
6d0f6bcf	149	#ifndef CONFIG_SYS_PCI_MSTR_MEM_SIZE
3c74e32a	150	#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
5d232d0e	151	#else
6d0f6bcf	152	#define PCI_MSTR_MEM_SIZE CONFIG_SYS_PCI_MSTR_MEM_SIZE
5d232d0e WD	153	#endif
5d232d0e WD	154
6d0f6bcf	155	#ifndef CONFIG_SYS_POCMR0_MASK_ATTRIB
4d75a504	156	#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB \| POCMR_ENABLE \| POCMR_PREFETCH_EN)
5d232d0e	157	#else
6d0f6bcf	158	#define POCMR0_MASK_ATTRIB CONFIG_SYS_POCMR0_MASK_ATTRIB
5d232d0e	159	#endif
4d75a504	160
8bde7f77	161	/*
4d75a504 WD	162	* Master window that allows the CPU to access PCI Memory (non-prefetch).
	163	* This window will be setup with the second set of Outbound ATU registers
	164	* in the bridge.
	165	*/
	166
6d0f6bcf	167	#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
3c74e32a	168	#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
8bde7f77	169	#else
6d0f6bcf	170	#define PCI_MSTR_MEMIO_LOCAL CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL
5d232d0e WD	171	#endif
5d232d0e WD	172
6d0f6bcf	173	#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_BUS
3c74e32a	174	#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
8bde7f77	175	#else
6d0f6bcf	176	#define PCI_MSTR_MEMIO_BUS CONFIG_SYS_PCI_MSTR_MEMIO_BUS
5d232d0e WD	177	#endif
5d232d0e WD	178
6d0f6bcf	179	#ifndef CONFIG_SYS_CPU_PCI_MEMIO_START
8bde7f77 WD	180	#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
8bde7f77 WD	181	#else
6d0f6bcf	182	#define CPU_PCI_MEMIO_START CONFIG_SYS_CPU_PCI_MEMIO_START
5d232d0e WD	183	#endif
5d232d0e WD	184
6d0f6bcf	185	#ifndef CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
3c74e32a	186	#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
8bde7f77	187	#else
6d0f6bcf	188	#define PCI_MSTR_MEMIO_SIZE CONFIG_SYS_PCI_MSTR_MEMIO_SIZE
5d232d0e WD	189	#endif
5d232d0e WD	190
6d0f6bcf	191	#ifndef CONFIG_SYS_POCMR1_MASK_ATTRIB
3c74e32a	192	#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB \| POCMR_ENABLE)
5d232d0e	193	#else
6d0f6bcf	194	#define POCMR1_MASK_ATTRIB CONFIG_SYS_POCMR1_MASK_ATTRIB
5d232d0e	195	#endif
4d75a504	196
8bde7f77	197	/*
4d75a504 WD	198	* Master window that allows the CPU to access PCI IO space.
	199	* This window will be setup with the third set of Outbound ATU registers
	200	* in the bridge.
	201	*/
	202
6d0f6bcf	203	#ifndef CONFIG_SYS_PCI_MSTR_IO_LOCAL
3c74e32a	204	#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
8bde7f77	205	#else
6d0f6bcf	206	#define PCI_MSTR_IO_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL
5d232d0e WD	207	#endif
5d232d0e WD	208
6d0f6bcf	209	#ifndef CONFIG_SYS_PCI_MSTR_IO_BUS
3c74e32a	210	#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
8bde7f77	211	#else
6d0f6bcf	212	#define PCI_MSTR_IO_BUS CONFIG_SYS_PCI_MSTR_IO_BUS
5d232d0e WD	213	#endif
5d232d0e WD	214
6d0f6bcf	215	#ifndef CONFIG_SYS_CPU_PCI_IO_START
8bde7f77 WD	216	#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
8bde7f77 WD	217	#else
6d0f6bcf	218	#define CPU_PCI_IO_START CONFIG_SYS_CPU_PCI_IO_START
5d232d0e WD	219	#endif
5d232d0e WD	220
6d0f6bcf	221	#ifndef CONFIG_SYS_PCI_MSTR_IO_SIZE
3c74e32a	222	#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
8bde7f77	223	#else
6d0f6bcf	224	#define PCI_MSTR_IO_SIZE CONFIG_SYS_PCI_MSTR_IO_SIZE
66fd3d1c	225	#endif
5d232d0e	226
6d0f6bcf	227	#ifndef CONFIG_SYS_POCMR2_MASK_ATTRIB
3c74e32a	228	#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB \| POCMR_ENABLE \| POCMR_PCI_IO)
5d232d0e	229	#else
6d0f6bcf	230	#define POCMR2_MASK_ATTRIB CONFIG_SYS_POCMR2_MASK_ATTRIB
5d232d0e	231	#endif
4d75a504 WD	232
	233	/* PCI bus configuration registers.
	234	*/
	235
	236	#define PCI_CLASS_BRIDGE_CTLR 0x06
	237
	238
3c74e32a	239	static inline void pci_outl (u32 addr, u32 data)
4d75a504	240	{
3c74e32a	241	(volatile u32 ) addr = cpu_to_le32 (data);
4d75a504 WD	242	}
4d75a504 WD	243
3c74e32a	244	void pci_mpc8250_init (struct pci_controller *hose)
4d75a504	245	{
3c74e32a WD	246	u16 tempShort;
3c74e32a WD	247
6d0f6bcf	248	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
3c74e32a	249	pci_dev_t host_devno = PCI_BDF (0, 0, 0);
4d75a504	250
6d0f6bcf JCPV	251	pci_setup_indirect (hose, CONFIG_SYS_IMMR + PCI_CFG_ADDR_REG,
6d0f6bcf JCPV	252	CONFIG_SYS_IMMR + PCI_CFG_DATA_REG);
4d75a504	253
3c74e32a WD	254	/*
	255	* Setting required to enable local bus for PCI (SIUMCR [LBPC]).
	256	*/
5d232d0e	257	#ifdef CONFIG_MPC8266ADS
3c74e32a WD	258	immap->im_siu_conf.sc_siumcr =
	259	(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
	260	\| SIUMCR_LBPC01;
8701ecef SW	261	#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
8701ecef SW	262	/* nothing to do for this board here */
1972dc0a	263	#elif defined CONFIG_MPC8272
716c1dcb WD	264	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
	265	~SIUMCR_BBD &
	266	~SIUMCR_ESE &
	267	~SIUMCR_PBSE &
	268	~SIUMCR_CDIS &
	269	~SIUMCR_DPPC11 &
	270	~SIUMCR_L2CPC11 &
	271	~SIUMCR_LBPC11 &
	272	~SIUMCR_APPC11 &
	273	~SIUMCR_CS10PC11 &
	274	~SIUMCR_BCTLC11 &
	275	~SIUMCR_MMR11)
	276	\| SIUMCR_DPPC11
	277	\| SIUMCR_L2CPC01
	278	\| SIUMCR_LBPC00
	279	\| SIUMCR_APPC10
	280	\| SIUMCR_CS10PC00
	281	\| SIUMCR_BCTLC00
	282	\| SIUMCR_MMR11;
fa230445	283	#elif defined(CONFIG_TQM8272)
07e82cb2	284	/* nothing to do for this Board here */
5d232d0e	285	#else
3c74e32a WD	286	/*
	287	* Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
	288	* and local bus for PCI (SIUMCR [LBPC]).
	289	*/
	290	immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
	291	~SIUMCR_LBPC11 &
8bde7f77	292	~SIUMCR_CS10PC11 &
3c74e32a WD	293	~SIUMCR_LBPC11) \|
	294	SIUMCR_LBPC01 \|
	295	SIUMCR_CS10PC01 \|
	296	SIUMCR_APPC10;
5d232d0e	297	#endif
4d75a504	298
3c74e32a WD	299	/* Make PCI lowest priority */
	300	/* Each 4 bits is a device bus request and the MS 4bits
	301	is highest priority */
	302	/* Bus 4bit value
	303	--- ----------
	304	CPM high 0b0000
	305	CPM middle 0b0001
	306	CPM low 0b0010
	307	PCI reguest 0b0011
	308	Reserved 0b0100
	309	Reserved 0b0101
	310	Internal Core 0b0110
	311	External Master 1 0b0111
	312	External Master 2 0b1000
	313	External Master 3 0b1001
	314	The rest are reserved */
	315	immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
	316
	317	/* Park bus on core while modifying PCI Bus accesses */
	318	immap->im_siu_conf.sc_ppc_acr = 0x6;
	319
	320	/*
	321	* Set up master windows that allow the CPU to access PCI space. These
	322	* windows are set up using the two SIU PCIBR registers.
	323	*/
	324	immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
	325	immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL \| PCIBR_ENABLE;
5d232d0e	326
1972dc0a	327	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272
d4326aca WD	328	immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
d4326aca WD	329	immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL \| PCIBR_ENABLE;
8bde7f77	330	#endif
4d75a504	331
3c74e32a WD	332	/* Release PCI RST (by default the PCI RST signal is held low) */
3c74e32a WD	333	immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
4d75a504	334
3c74e32a WD	335	/* give it some time */
3c74e32a WD	336	{
1972dc0a	337	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272
8bde7f77	338	/* Give the PCI cards more time to initialize before query
3c74e32a WD	339	This might be good for other boards also
	340	*/
	341	int i;
	342
	343	for (i = 0; i < 1000; ++i)
5d232d0e	344	#endif
3c74e32a WD	345	udelay (1000);
	346	}
	347
	348	/*
	349	* Set up master window that allows the CPU to access PCI Memory (prefetch)
	350	* space. This window is set up using the first set of Outbound ATU registers.
	351	*/
	352	immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
	353	immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
	354	immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
	355
	356	/*
	357	* Set up master window that allows the CPU to access PCI Memory (non-prefetch)
	358	* space. This window is set up using the second set of Outbound ATU registers.
	359	*/
	360	immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
	361	immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
	362	immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
	363
	364	/*
	365	* Set up master window that allows the CPU to access PCI IO space. This window
	366	* is set up using the third set of Outbound ATU registers.
	367	*/
	368	immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
	369	immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
	370	immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
	371
	372	/*
	373	* Set up slave window that allows PCI masters to access MPC826x local memory.
	374	* This window is set up using the first set of Inbound ATU registers
	375	*/
	376	immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
	377	immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
	378	immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
	379
	380	/* See above for description - puts PCI request as highest priority */
1972dc0a WD	381	#ifdef CONFIG_MPC8272
	382	immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
	383	#else
3c74e32a	384	immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
1972dc0a	385	#endif
3c74e32a WD	386
	387	/* Park the bus on the PCI */
	388	immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
	389
	390	/* Host mode - specify the bridge as a host-PCI bridge */
	391
	392	pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
	393	PCI_CLASS_BRIDGE_CTLR);
	394
	395	/* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
	396	pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
	397	pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
	398	tempShort \| PCI_COMMAND_MASTER \|
	399	PCI_COMMAND_MEMORY);
4d75a504	400
7a8e9bed	401	/* do some bridge init, should be done on all 8260 based bridges */
3c74e32a WD	402	pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
	403	0x08);
	404	pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
	405	0xF8);
7a8e9bed	406
3c74e32a WD	407	hose->first_busno = 0;
3c74e32a WD	408	hose->last_busno = 0xff;
4d75a504	409
3c74e32a	410	/* System memory space */
392c252e	411	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272 \|\| defined CONFIG_PM826
3c74e32a WD	412	pci_set_region (hose->regions + 0,
	413	PCI_SLV_MEM_BUS,
	414	PCI_SLV_MEM_LOCAL,
ff4e66e9	415	gd->ram_size, PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY);
5d232d0e	416	#else
3c74e32a	417	pci_set_region (hose->regions + 0,
6d0f6bcf JCPV	418	CONFIG_SYS_SDRAM_BASE,
6d0f6bcf JCPV	419	CONFIG_SYS_SDRAM_BASE,
ff4e66e9	420	0x4000000, PCI_REGION_MEM \| PCI_REGION_SYS_MEMORY);
5d232d0e	421	#endif
4d75a504	422
3c74e32a	423	/* PCI memory space */
716c1dcb	424	#if defined CONFIG_MPC8266ADS \|\| defined CONFIG_MPC8272
3c74e32a WD	425	pci_set_region (hose->regions + 1,
	426	PCI_MSTR_MEMIO_BUS,
	427	PCI_MSTR_MEMIO_LOCAL,
	428	PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
5d232d0e	429	#else
3c74e32a WD	430	pci_set_region (hose->regions + 1,
	431	PCI_MSTR_MEM_BUS,
	432	PCI_MSTR_MEM_LOCAL,
	433	PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
5d232d0e	434	#endif
4d75a504	435
3c74e32a WD	436	/* PCI I/O space */
	437	pci_set_region (hose->regions + 2,
	438	PCI_MSTR_IO_BUS,
	439	PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
	440
	441	hose->region_count = 3;
	442
	443	pci_register_hose (hose);
	444	/* Mask off master abort machine checks */
	445	immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
	446	eieio ();
	447
	448	hose->last_busno = pci_hose_scan (hose);
4d75a504	449
4d75a504	450
3c74e32a WD	451	/* clear the error in the error status register */
3c74e32a WD	452	immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
4d75a504	453
3c74e32a WD	454	/* unmask master abort machine checks */
3c74e32a WD	455	immap->im_pci.pci_emr \|= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
4d75a504 WD	456	}
4d75a504 WD	457
0e6989b9 MI	458	#if defined(CONFIG_OF_LIBFDT)
	459	void ft_pci_setup(void blob, bd_t bd)
	460	{
	461	do_fixup_by_prop_u32(blob, "device_type", "pci", 4,
52b047ae	462	"clock-frequency", gd->pci_clk, 1);
0e6989b9 MI	463	}
	464	#endif
	465
3c74e32a	466	#endif /* CONFIG_PCI */