[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu.c

/*
 * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
 * (C) Copyright 2002, 2003 Motorola Inc.
 * Xianghua Xiao (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <fsl_esdhc.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_ifc.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
#include <post.h>
#include <asm/processor.h>
#include <asm/fsl_ddr_sdram.h>

DECLARE_GLOBAL_DATA_PTR;

int checkcpu (void)
{
	sys_info_t sysinfo;
	uint pvr, svr;
	uint fam;
	uint ver;
	uint major, minor;
	struct cpu_type *cpu;
	char buf1[32], buf2[32];
#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif /* CONFIG_FSL_CORENET */
#ifdef CONFIG_DDR_CLK_FREQ
	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
#ifdef CONFIG_FSL_CORENET
	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
#else
	u32 ddr_ratio = 0;
#endif /* CONFIG_FSL_CORENET */
#endif /* CONFIG_DDR_CLK_FREQ */
	int i;

	svr = get_svr();
	major = SVR_MAJ(svr);
#ifdef CONFIG_MPC8536
	major &= 0x7; /* the msb of this nibble is a mfg code */
#endif
	minor = SVR_MIN(svr);

	if (cpu_numcores() > 1) {
#ifndef CONFIG_MP
		puts("Unicore software on multiprocessor system!!\n"
		     "To enable mutlticore build define CONFIG_MP\n");
#endif
		volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
		printf("CPU%d:  ", pic->whoami);
	} else {
		puts("CPU:   ");
	}

	cpu = gd->cpu;

	puts(cpu->name);
	if (IS_E_PROCESSOR(svr))
		puts("E");

	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);

	pvr = get_pvr();
	fam = PVR_FAM(pvr);
	ver = PVR_VER(pvr);
	major = PVR_MAJ(pvr);
	minor = PVR_MIN(pvr);

	printf("Core:  ");
	if (PVR_FAM(PVR_85xx)) {
		switch(PVR_MEM(pvr)) {
		case 0x1:
		case 0x2:
			puts("E500");
			break;
		case 0x3:
			puts("E500MC");
			break;
		case 0x4:
			puts("E5500");
			break;
		default:
			puts("Unknown");
			break;
		}
	} else {
		puts("Unknown");
	}

	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);

	get_sys_info(&sysinfo);

	puts("Clock Configuration:");
	for (i = 0; i < cpu_numcores(); i++) {
		if (!(i & 3))
			printf ("\n       ");
		printf("CPU%d:%-4s MHz, ",
				i,strmhz(buf1, sysinfo.freqProcessor[i]));
	}
	printf("\n       CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));

#ifdef CONFIG_FSL_CORENET
	if (ddr_sync == 1) {
		printf("       DDR:%-4s MHz (%s MT/s data rate) "
			"(Synchronous), ",
			strmhz(buf1, sysinfo.freqDDRBus/2),
			strmhz(buf2, sysinfo.freqDDRBus));
	} else {
		printf("       DDR:%-4s MHz (%s MT/s data rate) "
			"(Asynchronous), ",
			strmhz(buf1, sysinfo.freqDDRBus/2),
			strmhz(buf2, sysinfo.freqDDRBus));
	}
#else
	switch (ddr_ratio) {
	case 0x0:
		printf("       DDR:%-4s MHz (%s MT/s data rate), ",
			strmhz(buf1, sysinfo.freqDDRBus/2),
			strmhz(buf2, sysinfo.freqDDRBus));
		break;
	case 0x7:
		printf("       DDR:%-4s MHz (%s MT/s data rate) "
			"(Synchronous), ",
			strmhz(buf1, sysinfo.freqDDRBus/2),
			strmhz(buf2, sysinfo.freqDDRBus));
		break;
	default:
		printf("       DDR:%-4s MHz (%s MT/s data rate) "
			"(Asynchronous), ",
			strmhz(buf1, sysinfo.freqDDRBus/2),
			strmhz(buf2, sysinfo.freqDDRBus));
		break;
	}
#endif

#if defined(CONFIG_FSL_LBC)
	if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
		printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
	} else {
		printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
		       sysinfo.freqLocalBus);
	}
#endif

#ifdef CONFIG_CPM2
	printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
#endif

#ifdef CONFIG_QE
	printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
		printf("       FMAN%d: %s MHz\n", i + 1,
			strmhz(buf1, sysinfo.freqFMan[i]));
	}
#endif

#ifdef CONFIG_SYS_DPAA_PME
	printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freqPME));
#endif

	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");

	return 0;
}


/* ------------------------------------------------------------------------- */

int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
/* Everything after the first generation of PQ3 parts has RSTCR */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
    defined(CONFIG_MPC8555) || defined(CONFIG_MPC8560)
	unsigned long val, msr;

	/*
	 * Initiate hard reset in debug control register DBCR0
	 * Make sure MSR[DE] = 1.  This only resets the core.
	 */
	msr = mfmsr ();
	msr |= MSR_DE;
	mtmsr (msr);

	val = mfspr(DBCR0);
	val |= 0x70000000;
	mtspr(DBCR0,val);
#else
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	out_be32(&gur->rstcr, 0x2);	/* HRESET_REQ */
	udelay(100);
#endif

	return 1;
}


/*
 * Get timebase clock frequency
 */
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#define CONFIG_SYS_FSL_TBCLK_DIV 8
#endif
unsigned long get_tbclk (void)
{
	unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;

	return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
}


#if defined(CONFIG_WATCHDOG)
void
watchdog_reset(void)
{
	int re_enable = disable_interrupts();
	reset_85xx_watchdog();
	if (re_enable) enable_interrupts();
}

void
reset_85xx_watchdog(void)
{
	/*
	 * Clear TSR(WIS) bit by writing 1
	 */
	unsigned long val;
	val = mfspr(SPRN_TSR);
	val |= TSR_WIS;
	mtspr(SPRN_TSR, val);
}
#endif	/* CONFIG_WATCHDOG */

/*
 * Initializes on-chip MMC controllers.
 * to override, implement board_mmc_init()
 */
int cpu_mmc_init(bd_t *bis)
{
#ifdef CONFIG_FSL_ESDHC
	return fsl_esdhc_mmc_init(bis);
#else
	return 0;
#endif
}

/*
 * Print out the state of various machine registers.
 * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
 * parameters for IFC and TLBs
 */
void mpc85xx_reginfo(void)
{
	print_tlbcam();
	print_laws();
#if defined(CONFIG_FSL_LBC)
	print_lbc_regs();
#endif
#ifdef CONFIG_FSL_IFC
	print_ifc_regs();
#endif

}

/* Common ddr init for non-corenet fsl 85xx platforms */
#ifndef CONFIG_FSL_CORENET
#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
phys_size_t initdram(int board_type)
{
#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
	return fsl_ddr_sdram_size();
#else
	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
}
#else /* CONFIG_SYS_RAMBOOT */
phys_size_t initdram(int board_type)
{
	phys_size_t dram_size = 0;

#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
	{
		ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
		unsigned int x = 10;
		unsigned int i;

		/*
		 * Work around to stabilize DDR DLL
		 */
		out_be32(&gur->ddrdllcr, 0x81000000);
		asm("sync;isync;msync");
		udelay(200);
		while (in_be32(&gur->ddrdllcr) != 0x81000100) {
			setbits_be32(&gur->devdisr, 0x00010000);
			for (i = 0; i < x; i++)
				;
			clrbits_be32(&gur->devdisr, 0x00010000);
			x++;
		}
	}
#endif

#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
	dram_size = fsl_ddr_sdram();
#else
	dram_size = fixed_sdram();
#endif
	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	dram_size *= 0x100000;

#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	/*
	 * Initialize and enable DDR ECC.
	 */
	ddr_enable_ecc(dram_size);
#endif

#if defined(CONFIG_FSL_LBC)
	/* Some boards also have sdram on the lbc */
	lbc_sdram_init();
#endif

	puts("DDR: ");
	return dram_size;
}
#endif /* CONFIG_SYS_RAMBOOT */
#endif

#if CONFIG_POST & CONFIG_SYS_POST_MEMORY

/* Board-specific functions defined in each board's ddr.c */
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
	unsigned int ctrl_num);
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
		       phys_addr_t *rpn);
unsigned int
	setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);

static void dump_spd_ddr_reg(void)
{
	int i, j, k, m;
	u8 *p_8;
	u32 *p_32;
	ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
	generic_spd_eeprom_t
		spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];

	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
		fsl_ddr_get_spd(spd[i], i);

	puts("SPD data of all dimms (zero vaule is omitted)...\n");
	puts("Byte (hex)  ");
	k = 1;
	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
		for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
			printf("Dimm%d ", k++);
	}
	puts("\n");
	for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
		m = 0;
		printf("%3d (0x%02x)  ", k, k);
		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
				p_8 = (u8 *) &spd[i][j];
				if (p_8[k]) {
					printf("0x%02x  ", p_8[k]);
					m++;
				} else
					puts("      ");
			}
		}
		if (m)
			puts("\n");
		else
			puts("\r");
	}

	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
		switch (i) {
		case 0:
			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
			break;
#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
		case 1:
			ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
			break;
#endif
		default:
			printf("%s unexpected controller number = %u\n",
				__func__, i);
			return;
		}
	}
	printf("DDR registers dump for all controllers "
		"(zero vaule is omitted)...\n");
	puts("Offset (hex)   ");
	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
		printf("     Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
	puts("\n");
	for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
		m = 0;
		printf("%6d (0x%04x)", k * 4, k * 4);
		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
			p_32 = (u32 *) ddr[i];
			if (p_32[k]) {
				printf("        0x%08x", p_32[k]);
				m++;
			} else
				puts("                  ");
		}
		if (m)
			puts("\n");
		else
			puts("\r");
	}
	puts("\n");
}

/* invalid the TLBs for DDR and setup new ones to cover p_addr */
static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
{
	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
	unsigned long epn;
	u32 tsize, valid, ptr;
	phys_addr_t rpn = 0;
	int ddr_esel;

	ptr = vstart;

	while (ptr < (vstart + size)) {
		ddr_esel = find_tlb_idx((void *)ptr, 1);
		if (ddr_esel != -1) {
			read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
			disable_tlb(ddr_esel);
		}
		ptr += TSIZE_TO_BYTES(tsize);
	}

	/* Setup new tlb to cover the physical address */
	setup_ddr_tlbs_phys(p_addr, size>>20);

	ptr = vstart;
	ddr_esel = find_tlb_idx((void *)ptr, 1);
	if (ddr_esel != -1) {
		read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
	} else {
		printf("TLB error in function %s\n", __func__);
		return -1;
	}

	return 0;
}

/*
 * slide the testing window up to test another area
 * for 32_bit system, the maximum testable memory is limited to
 * CONFIG_MAX_MEM_MAPPED
 */
int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
	phys_addr_t test_cap, p_addr;
	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);

#if !defined(CONFIG_PHYS_64BIT) || \
    !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
		test_cap = p_size;
#else
		test_cap = gd->ram_size;
#endif
	p_addr = (*vstart) + (*size) + (*phys_offset);
	if (p_addr < test_cap - 1) {
		p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
		if (reset_tlb(p_addr, p_size, phys_offset) == -1)
			return -1;
		*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
		*size = (u32) p_size;
		printf("Testing 0x%08llx - 0x%08llx\n",
			(u64)(*vstart) + (*phys_offset),
			(u64)(*vstart) + (*phys_offset) + (*size) - 1);
	} else
		return 1;

	return 0;
}

/* initialization for testing area */
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);

	*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
	*size = (u32) p_size;	/* CONFIG_MAX_MEM_MAPPED < 4G */
	*phys_offset = 0;

#if !defined(CONFIG_PHYS_64BIT) || \
    !defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) || \
	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
		if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
			puts("Cannot test more than ");
			print_size(CONFIG_MAX_MEM_MAPPED,
				" without proper 36BIT support.\n");
		}
#endif
	printf("Testing 0x%08llx - 0x%08llx\n",
		(u64)(*vstart) + (*phys_offset),
		(u64)(*vstart) + (*phys_offset) + (*size) - 1);

	return 0;
}

/* invalid TLBs for DDR and remap as normal after testing */
int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
	unsigned long epn;
	u32 tsize, valid, ptr;
	phys_addr_t rpn = 0;
	int ddr_esel;

	/* disable the TLBs for this testing */
	ptr = *vstart;

	while (ptr < (*vstart) + (*size)) {
		ddr_esel = find_tlb_idx((void *)ptr, 1);
		if (ddr_esel != -1) {
			read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
			disable_tlb(ddr_esel);
		}
		ptr += TSIZE_TO_BYTES(tsize);
	}

	puts("Remap DDR ");
	setup_ddr_tlbs(gd->ram_size>>20);
	puts("\n");

	return 0;
}

void arch_memory_failure_handle(void)
{
	dump_spd_ddr_reg();
}
#endif
Commit	Line	Data
42d1f039	1	/*
beba93ed	2	* Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
42d1f039 WD	3	* (C) Copyright 2002, 2003 Motorola Inc.
	4	* Xianghua Xiao (X.Xiao@motorola.com)
	5	*
	6	* (C) Copyright 2000
	7	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
75b9d4ae	28	#include <config.h>
42d1f039 WD	29	#include <common.h>
	30	#include <watchdog.h>
	31	#include <command.h>
80522dc8	32	#include <fsl_esdhc.h>
42d1f039	33	#include <asm/cache.h>
740280e6	34	#include <asm/io.h>
199e262e	35	#include <asm/mmu.h>
d789b5f5	36	#include <asm/fsl_ifc.h>
199e262e	37	#include <asm/fsl_law.h>
38dba0c2	38	#include <asm/fsl_lbc.h>
ebbe11dd YS	39	#include <post.h>
	40	#include <asm/processor.h>
	41	#include <asm/fsl_ddr_sdram.h>
42d1f039	42
591933ca JY	43	DECLARE_GLOBAL_DATA_PTR;
591933ca JY	44
42d1f039 WD	45	int checkcpu (void)
42d1f039 WD	46	{
97d80fc3	47	sys_info_t sysinfo;
97d80fc3	48	uint pvr, svr;
d9b94f28	49	uint fam;
97d80fc3 WD	50	uint ver;
97d80fc3 WD	51	uint major, minor;
4dbdb768	52	struct cpu_type *cpu;
08ef89ec	53	char buf1[32], buf2[32];
9ce3c228	54	#if defined(CONFIG_DDR_CLK_FREQ) \|\| defined(CONFIG_FSL_CORENET)
6d0f6bcf	55	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
9ce3c228	56	#endif /* CONFIG_FSL_CORENET */
ab48ca1a	57	#ifdef CONFIG_DDR_CLK_FREQ
c0391111 JJ	58	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
c0391111 JJ	59	>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
39aaca1f KG	60	#else
39aaca1f KG	61	#ifdef CONFIG_FSL_CORENET
ab48ca1a SS	62	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
ab48ca1a SS	63	>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
ee1e35be KG	64	#else
ee1e35be KG	65	u32 ddr_ratio = 0;
ab48ca1a	66	#endif /* CONFIG_FSL_CORENET */
39aaca1f	67	#endif /* CONFIG_DDR_CLK_FREQ */
2fc7eb0c	68	int i;
97d80fc3	69
97d80fc3	70	svr = get_svr();
97d80fc3	71	major = SVR_MAJ(svr);
ef50d6c0 KG	72	#ifdef CONFIG_MPC8536
	73	major &= 0x7; /* the msb of this nibble is a mfg code */
	74	#endif
97d80fc3	75	minor = SVR_MIN(svr);
42d1f039	76
0e870980	77	if (cpu_numcores() > 1) {
21170c80 PA	78	#ifndef CONFIG_MP
	79	puts("Unicore software on multiprocessor system!!\n"
	80	"To enable mutlticore build define CONFIG_MP\n");
	81	#endif
680c613a	82	volatile ccsr_pic_t pic = (void )(CONFIG_SYS_MPC8xxx_PIC_ADDR);
0e870980 PA	83	printf("CPU%d: ", pic->whoami);
	84	} else {
	85	puts("CPU: ");
	86	}
1ced1216	87
0e870980	88	cpu = gd->cpu;
1ced1216	89
58442dc0 PA	90	puts(cpu->name);
	91	if (IS_E_PROCESSOR(svr))
	92	puts("E");
1ced1216	93
97d80fc3 WD	94	printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
97d80fc3 WD	95
6c9e789e	96	pvr = get_pvr();
d9b94f28	97	fam = PVR_FAM(pvr);
6c9e789e WD	98	ver = PVR_VER(pvr);
	99	major = PVR_MAJ(pvr);
	100	minor = PVR_MIN(pvr);
	101
	102	printf("Core: ");
2a3a96ca KG	103	if (PVR_FAM(PVR_85xx)) {
	104	switch(PVR_MEM(pvr)) {
	105	case 0x1:
	106	case 0x2:
	107	puts("E500");
	108	break;
	109	case 0x3:
	110	puts("E500MC");
	111	break;
	112	case 0x4:
	113	puts("E5500");
	114	break;
	115	default:
	116	puts("Unknown");
	117	break;
	118	}
	119	} else {
	120	puts("Unknown");
6c9e789e	121	}
0f060c3b	122
6c9e789e WD	123	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
6c9e789e WD	124
97d80fc3 WD	125	get_sys_info(&sysinfo);
97d80fc3 WD	126
b29dee3c	127	puts("Clock Configuration:");
0e870980	128	for (i = 0; i < cpu_numcores(); i++) {
1bba30ef WD	129	if (!(i & 3))
1bba30ef WD	130	printf ("\n ");
2fc7eb0c HW	131	printf("CPU%d:%-4s MHz, ",
2fc7eb0c HW	132	i,strmhz(buf1, sysinfo.freqProcessor[i]));
b29dee3c KG	133	}
b29dee3c KG	134	printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
ee1e35be	135
39aaca1f KG	136	#ifdef CONFIG_FSL_CORENET
	137	if (ddr_sync == 1) {
	138	printf(" DDR:%-4s MHz (%s MT/s data rate) "
	139	"(Synchronous), ",
	140	strmhz(buf1, sysinfo.freqDDRBus/2),
	141	strmhz(buf2, sysinfo.freqDDRBus));
	142	} else {
	143	printf(" DDR:%-4s MHz (%s MT/s data rate) "
	144	"(Asynchronous), ",
	145	strmhz(buf1, sysinfo.freqDDRBus/2),
	146	strmhz(buf2, sysinfo.freqDDRBus));
	147	}
	148	#else
d4357932 KG	149	switch (ddr_ratio) {
d4357932 KG	150	case 0x0:
08ef89ec WD	151	printf(" DDR:%-4s MHz (%s MT/s data rate), ",
	152	strmhz(buf1, sysinfo.freqDDRBus/2),
	153	strmhz(buf2, sysinfo.freqDDRBus));
d4357932 KG	154	break;
d4357932 KG	155	case 0x7:
39aaca1f KG	156	printf(" DDR:%-4s MHz (%s MT/s data rate) "
39aaca1f KG	157	"(Synchronous), ",
08ef89ec WD	158	strmhz(buf1, sysinfo.freqDDRBus/2),
08ef89ec WD	159	strmhz(buf2, sysinfo.freqDDRBus));
d4357932 KG	160	break;
d4357932 KG	161	default:
39aaca1f KG	162	printf(" DDR:%-4s MHz (%s MT/s data rate) "
39aaca1f KG	163	"(Asynchronous), ",
08ef89ec WD	164	strmhz(buf1, sysinfo.freqDDRBus/2),
08ef89ec WD	165	strmhz(buf2, sysinfo.freqDDRBus));
d4357932 KG	166	break;
d4357932 KG	167	}
39aaca1f	168	#endif
97d80fc3	169
beba93ed	170	#if defined(CONFIG_FSL_LBC)
39aaca1f	171	if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
ada591d2	172	printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
39aaca1f	173	} else {
ada591d2 TP	174	printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
ada591d2 TP	175	sysinfo.freqLocalBus);
39aaca1f	176	}
beba93ed	177	#endif
42d1f039	178
1ced1216	179	#ifdef CONFIG_CPM2
08ef89ec	180	printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
1ced1216	181	#endif
97d80fc3	182
b3d7f20f HW	183	#ifdef CONFIG_QE
	184	printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
	185	#endif
	186
39aaca1f KG	187	#ifdef CONFIG_SYS_DPAA_FMAN
39aaca1f KG	188	for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
7eda1f8e	189	printf(" FMAN%d: %s MHz\n", i + 1,
39aaca1f KG	190	strmhz(buf1, sysinfo.freqFMan[i]));
	191	}
	192	#endif
	193
	194	#ifdef CONFIG_SYS_DPAA_PME
	195	printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME));
	196	#endif
	197
6c9e789e	198	puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
42d1f039 WD	199
	200	return 0;
	201	}
	202
	203
	204	/* ------------------------------------------------------------------------- */
	205
882b7d72	206	int do_reset (cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
42d1f039	207	{
c348322a KG	208	/* Everything after the first generation of PQ3 parts has RSTCR */
	209	#if defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
	210	defined(CONFIG_MPC8555) \|\| defined(CONFIG_MPC8560)
793670c3 SP	211	unsigned long val, msr;
793670c3 SP	212
42d1f039 WD	213	/*
42d1f039 WD	214	* Initiate hard reset in debug control register DBCR0
c348322a	215	* Make sure MSR[DE] = 1. This only resets the core.
42d1f039	216	*/
793670c3 SP	217	msr = mfmsr ();
	218	msr \|= MSR_DE;
	219	mtmsr (msr);
	220
	221	val = mfspr(DBCR0);
	222	val \|= 0x70000000;
	223	mtspr(DBCR0,val);
c348322a KG	224	#else
	225	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	226	out_be32(&gur->rstcr, 0x2); /* HRESET_REQ */
	227	udelay(100);
	228	#endif
df90968b	229
42d1f039 WD	230	return 1;
	231	}
	232
	233
	234	/*
	235	* Get timebase clock frequency
	236	*/
66412c63 KG	237	#ifndef CONFIG_SYS_FSL_TBCLK_DIV
	238	#define CONFIG_SYS_FSL_TBCLK_DIV 8
	239	#endif
42d1f039 WD	240	unsigned long get_tbclk (void)
42d1f039 WD	241	{
66412c63 KG	242	unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
	243
	244	return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div;
42d1f039 WD	245	}
	246
	247
	248	#if defined(CONFIG_WATCHDOG)
	249	void
	250	watchdog_reset(void)
	251	{
	252	int re_enable = disable_interrupts();
	253	reset_85xx_watchdog();
	254	if (re_enable) enable_interrupts();
	255	}
	256
	257	void
	258	reset_85xx_watchdog(void)
	259	{
	260	/*
	261	* Clear TSR(WIS) bit by writing 1
	262	*/
	263	unsigned long val;
03b81b48 AF	264	val = mfspr(SPRN_TSR);
	265	val \|= TSR_WIS;
	266	mtspr(SPRN_TSR, val);
42d1f039 WD	267	}
	268	#endif /* CONFIG_WATCHDOG */
	269
80522dc8 AF	270	/*
	271	* Initializes on-chip MMC controllers.
	272	* to override, implement board_mmc_init()
	273	*/
	274	int cpu_mmc_init(bd_t *bis)
	275	{
	276	#ifdef CONFIG_FSL_ESDHC
	277	return fsl_esdhc_mmc_init(bis);
	278	#else
	279	return 0;
	280	#endif
	281	}
199e262e BB	282
	283	/*
	284	* Print out the state of various machine registers.
d789b5f5 DD	285	* Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
d789b5f5 DD	286	* parameters for IFC and TLBs
199e262e BB	287	*/
	288	void mpc85xx_reginfo(void)
	289	{
	290	print_tlbcam();
	291	print_laws();
beba93ed	292	#if defined(CONFIG_FSL_LBC)
199e262e	293	print_lbc_regs();
beba93ed	294	#endif
d789b5f5 DD	295	#ifdef CONFIG_FSL_IFC
	296	print_ifc_regs();
	297	#endif
beba93ed	298
199e262e	299	}
ebbe11dd	300
38dba0c2 BB	301	/* Common ddr init for non-corenet fsl 85xx platforms */
38dba0c2 BB	302	#ifndef CONFIG_FSL_CORENET
c1fc2d4f ZC	303	#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_INIT_L2_ADDR)
	304	phys_size_t initdram(int board_type)
	305	{
	306	#if defined(CONFIG_SPD_EEPROM) \|\| defined(CONFIG_DDR_SPD)
	307	return fsl_ddr_sdram_size();
	308	#else
	309	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
	310	#endif
	311	}
	312	#else /* CONFIG_SYS_RAMBOOT */
38dba0c2 BB	313	phys_size_t initdram(int board_type)
	314	{
	315	phys_size_t dram_size = 0;
	316
810c4427	317	#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
38dba0c2 BB	318	{
	319	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	320	unsigned int x = 10;
	321	unsigned int i;
	322
	323	/*
	324	* Work around to stabilize DDR DLL
	325	*/
	326	out_be32(&gur->ddrdllcr, 0x81000000);
	327	asm("sync;isync;msync");
	328	udelay(200);
	329	while (in_be32(&gur->ddrdllcr) != 0x81000100) {
	330	setbits_be32(&gur->devdisr, 0x00010000);
	331	for (i = 0; i < x; i++)
	332	;
	333	clrbits_be32(&gur->devdisr, 0x00010000);
	334	x++;
	335	}
	336	}
	337	#endif
	338
	339	#if defined(CONFIG_SPD_EEPROM) \|\| defined(CONFIG_DDR_SPD)
	340	dram_size = fsl_ddr_sdram();
	341	#else
	342	dram_size = fixed_sdram();
	343	#endif
	344	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
	345	dram_size *= 0x100000;
	346
	347	#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
	348	/*
	349	* Initialize and enable DDR ECC.
	350	*/
	351	ddr_enable_ecc(dram_size);
	352	#endif
	353
beba93ed	354	#if defined(CONFIG_FSL_LBC)
38dba0c2	355	/* Some boards also have sdram on the lbc */
70961ba4	356	lbc_sdram_init();
beba93ed	357	#endif
38dba0c2 BB	358
	359	puts("DDR: ");
	360	return dram_size;
	361	}
c1fc2d4f	362	#endif /* CONFIG_SYS_RAMBOOT */
38dba0c2 BB	363	#endif
38dba0c2 BB	364
ebbe11dd YS	365	#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
	366
	367	/* Board-specific functions defined in each board's ddr.c */
	368	void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
	369	unsigned int ctrl_num);
	370	void read_tlbcam_entry(int idx, u32 valid, u32 tsize, unsigned long *epn,
	371	phys_addr_t *rpn);
	372	unsigned int
	373	setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg);
	374
	375	static void dump_spd_ddr_reg(void)
	376	{
	377	int i, j, k, m;
	378	u8 *p_8;
	379	u32 *p_32;
	380	ccsr_ddr_t *ddr[CONFIG_NUM_DDR_CONTROLLERS];
	381	generic_spd_eeprom_t
	382	spd[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR];
	383
	384	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
	385	fsl_ddr_get_spd(spd[i], i);
	386
	387	puts("SPD data of all dimms (zero vaule is omitted)...\n");
	388	puts("Byte (hex) ");
	389	k = 1;
	390	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
	391	for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++)
	392	printf("Dimm%d ", k++);
	393	}
	394	puts("\n");
	395	for (k = 0; k < sizeof(generic_spd_eeprom_t); k++) {
	396	m = 0;
	397	printf("%3d (0x%02x) ", k, k);
	398	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
	399	for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
	400	p_8 = (u8 *) &spd[i][j];
	401	if (p_8[k]) {
	402	printf("0x%02x ", p_8[k]);
	403	m++;
	404	} else
	405	puts(" ");
	406	}
	407	}
	408	if (m)
	409	puts("\n");
	410	else
	411	puts("\r");
	412	}
	413
	414	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
	415	switch (i) {
	416	case 0:
	417	ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
	418	break;
	419	#ifdef CONFIG_SYS_MPC85xx_DDR2_ADDR
	420	case 1:
	421	ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
	422	break;
	423	#endif
	424	default:
	425	printf("%s unexpected controller number = %u\n",
	426	__func__, i);
	427	return;
	428	}
429	}
430	printf("DDR registers dump for all controllers "
431	"(zero vaule is omitted)...\n");
432	puts("Offset (hex) ");
433	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
434	printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF);
435	puts("\n");
436	for (k = 0; k < sizeof(ccsr_ddr_t)/4; k++) {
437	m = 0;
438	printf("%6d (0x%04x)", k * 4, k * 4);
439	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
440	p_32 = (u32 *) ddr[i];
441	if (p_32[k]) {
442	printf(" 0x%08x", p_32[k]);
443	m++;
444	} else
445	puts(" ");
446	}
447	if (m)
448	puts("\n");
449	else
450	puts("\r");
451	}
452	puts("\n");
453	}
454
455	/* invalid the TLBs for DDR and setup new ones to cover p_addr */
456	static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
457	{
458	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
459	unsigned long epn;
460	u32 tsize, valid, ptr;
461	phys_addr_t rpn = 0;
462	int ddr_esel;
463
464	ptr = vstart;
465
466	while (ptr < (vstart + size)) {
467	ddr_esel = find_tlb_idx((void *)ptr, 1);
468	if (ddr_esel != -1) {
469	read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
470	disable_tlb(ddr_esel);
471	}
472	ptr += TSIZE_TO_BYTES(tsize);
473	}
474
475	/* Setup new tlb to cover the physical address */
476	setup_ddr_tlbs_phys(p_addr, size>>20);
477
478	ptr = vstart;
479	ddr_esel = find_tlb_idx((void *)ptr, 1);
480	if (ddr_esel != -1) {
481	read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, phys_offset);
482	} else {
483	printf("TLB error in function %s\n", __func__);
484	return -1;
485	}
486
487	return 0;
488	}
489
490	/*
491	* slide the testing window up to test another area
492	* for 32_bit system, the maximum testable memory is limited to
493	* CONFIG_MAX_MEM_MAPPED
494	*/
495	int arch_memory_test_advance(u32 vstart, u32 size, phys_addr_t *phys_offset)
496	{
497	phys_addr_t test_cap, p_addr;
498	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
499
500	#if !defined(CONFIG_PHYS_64BIT) \|\| \
501	!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) \|\| \
502	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
503	test_cap = p_size;
504	#else
505	test_cap = gd->ram_size;
506	#endif
507	p_addr = (vstart) + (size) + (*phys_offset);
508	if (p_addr < test_cap - 1) {
509	p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED);
510	if (reset_tlb(p_addr, p_size, phys_offset) == -1)
511	return -1;
512	*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
513	*size = (u32) p_size;
514	printf("Testing 0x%08llx - 0x%08llx\n",
515	(u64)(vstart) + (phys_offset),
516	(u64)(vstart) + (phys_offset) + (*size) - 1);
517	} else
518	return 1;
519
520	return 0;
521	}
522
523	/* initialization for testing area */
524	int arch_memory_test_prepare(u32 vstart, u32 size, phys_addr_t *phys_offset)
525	{
526	phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED);
527
528	*vstart = CONFIG_SYS_DDR_SDRAM_BASE;
529	size = (u32) p_size; / CONFIG_MAX_MEM_MAPPED < 4G */
530	*phys_offset = 0;
531
532	#if !defined(CONFIG_PHYS_64BIT) \|\| \
533	!defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS) \|\| \
534	(CONFIG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
535	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
536	puts("Cannot test more than ");
537	print_size(CONFIG_MAX_MEM_MAPPED,
538	" without proper 36BIT support.\n");
539	}
540	#endif
541	printf("Testing 0x%08llx - 0x%08llx\n",
542	(u64)(vstart) + (phys_offset),
543	(u64)(vstart) + (phys_offset) + (*size) - 1);
544
545	return 0;
546	}
547
548	/* invalid TLBs for DDR and remap as normal after testing */
549	int arch_memory_test_cleanup(u32 vstart, u32 size, phys_addr_t *phys_offset)
550	{
551	unsigned long epn;
552	u32 tsize, valid, ptr;
553	phys_addr_t rpn = 0;
554	int ddr_esel;
555
556	/* disable the TLBs for this testing */
557	ptr = *vstart;
558
559	while (ptr < (vstart) + (size)) {
560	ddr_esel = find_tlb_idx((void *)ptr, 1);
561	if (ddr_esel != -1) {
562	read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
563	disable_tlb(ddr_esel);
564	}
565	ptr += TSIZE_TO_BYTES(tsize);
566	}
567
568	puts("Remap DDR ");
569	setup_ddr_tlbs(gd->ram_size>>20);
570	puts("\n");
571
572	return 0;
573	}
574
575	void arch_memory_failure_handle(void)
576	{
577	dump_spd_ddr_reg();
578	}
579	#endif