[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / cpu_init.c

/*
 * Copyright 2007-2010 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Modified by Xianghua Xiao, X.Xiao@motorola.com
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <watchdog.h>
#include <asm/processor.h>
#include <ioports.h>
#include <sata.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include "mp.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_MPC8536
extern void fsl_serdes_init(void);
#endif

#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
				int open_drain, int assign);
extern void qe_init(uint qe_base);
extern void qe_reset(void);

static void config_qe_ioports(void)
{
	u8      port, pin;
	int     dir, open_drain, assign;
	int     i;

	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
		port		= qe_iop_conf_tab[i].port;
		pin		= qe_iop_conf_tab[i].pin;
		dir		= qe_iop_conf_tab[i].dir;
		open_drain	= qe_iop_conf_tab[i].open_drain;
		assign		= qe_iop_conf_tab[i].assign;
		qe_config_iopin(port, pin, dir, open_drain, assign);
	}
}
#endif

#ifdef CONFIG_CPM2
void config_8560_ioports (volatile ccsr_cpm_t * cpm)
{
	int portnum;

	for (portnum = 0; portnum < 4; portnum++) {
		uint pmsk = 0,
		     ppar = 0,
		     psor = 0,
		     pdir = 0,
		     podr = 0,
		     pdat = 0;
		iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
		iop_conf_t *eiopc = iopc + 32;
		uint msk = 1;

		/*
		 * NOTE:
		 * index 0 refers to pin 31,
		 * index 31 refers to pin 0
		 */
		while (iopc < eiopc) {
			if (iopc->conf) {
				pmsk |= msk;
				if (iopc->ppar)
					ppar |= msk;
				if (iopc->psor)
					psor |= msk;
				if (iopc->pdir)
					pdir |= msk;
				if (iopc->podr)
					podr |= msk;
				if (iopc->pdat)
					pdat |= msk;
			}

			msk <<= 1;
			iopc++;
		}

		if (pmsk != 0) {
			volatile ioport_t *iop = ioport_addr (cpm, portnum);
			uint tpmsk = ~pmsk;

			/*
			 * the (somewhat confused) paragraph at the
			 * bottom of page 35-5 warns that there might
			 * be "unknown behaviour" when programming
			 * PSORx and PDIRx, if PPARx = 1, so I
			 * decided this meant I had to disable the
			 * dedicated function first, and enable it
			 * last.
			 */
			iop->ppar &= tpmsk;
			iop->psor = (iop->psor & tpmsk) | psor;
			iop->podr = (iop->podr & tpmsk) | podr;
			iop->pdat = (iop->pdat & tpmsk) | pdat;
			iop->pdir = (iop->pdir & tpmsk) | pdir;
			iop->ppar |= ppar;
		}
	}
}
#endif

/*
 * Breathe some life into the CPU...
 *
 * Set up the memory map
 * initialize a bunch of registers
 */

#ifdef CONFIG_FSL_CORENET
static void corenet_tb_init(void)
{
	volatile ccsr_rcpm_t *rcpm =
		(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
	volatile ccsr_pic_t *pic =
		(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
	u32 whoami = in_be32(&pic->whoami);

	/* Enable the timebase register for this core */
	out_be32(&rcpm->ctbenrl, (1 << whoami));
}
#endif

void cpu_init_f (void)
{
	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
	extern void m8560_cpm_reset (void);
#ifdef CONFIG_MPC8548
	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
	uint svr = get_svr();

	/*
	 * CPU2 errata workaround: A core hang possible while executing
	 * a msync instruction and a snoopable transaction from an I/O
	 * master tagged to make quick forward progress is present.
	 * Fixed in silicon rev 2.1.
	 */
	if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
		out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
#endif

	disable_tlb(14);
	disable_tlb(15);

#ifdef CONFIG_CPM2
	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
#endif

	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	 * addresses - these have to be modified later when FLASH size
	 * has been determined
	 */
#if defined(CONFIG_SYS_OR0_REMAP)
	out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
	out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
#endif

	/* now restrict to preliminary range */
	/* if cs1 is already set via debugger, leave cs0/cs1 alone */
	if (! memctl->br1 & 1) {
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
		out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
		out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
#endif

#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
		out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
		out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
#endif
	}

#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
	out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
	out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
#endif

#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
	out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
	out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
#endif

#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
	out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
	out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
#endif

#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
	out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
	out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
#endif

#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
	out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
	out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
#endif

#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
	out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
	out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
#endif

#if defined(CONFIG_CPM2)
	m8560_cpm_reset();
#endif
#ifdef CONFIG_QE
	/* Config QE ioports */
	config_qe_ioports();
#endif
#if defined(CONFIG_MPC8536)
	fsl_serdes_init();
#endif
#if defined(CONFIG_FSL_DMA)
	dma_init();
#endif
#ifdef CONFIG_FSL_CORENET
	corenet_tb_init();
#endif
	init_used_tlb_cams();
}


/*
 * Initialize L2 as cache.
 *
 * The newer 8548, etc, parts have twice as much cache, but
 * use the same bit-encoding as the older 8555, etc, parts.
 *
 */

int cpu_init_r(void)
{
#ifdef CONFIG_SYS_LBC_LCRR
	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
#endif

	puts ("L2:    ");

#if defined(CONFIG_L2_CACHE)
	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
	volatile uint cache_ctl;
	uint svr, ver;
	uint l2srbar;
	u32 l2siz_field;

	svr = get_svr();
	ver = SVR_SOC_VER(svr);

	asm("msync;isync");
	cache_ctl = l2cache->l2ctl;

#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	if (cache_ctl & MPC85xx_L2CTL_L2E) {
		/* Clear L2 SRAM memory-mapped base address */
		out_be32(&l2cache->l2srbar0, 0x0);
		out_be32(&l2cache->l2srbar1, 0x0);

		/* set MBECCDIS=0, SBECCDIS=0 */
		clrbits_be32(&l2cache->l2errdis,
				(MPC85xx_L2ERRDIS_MBECC |
				 MPC85xx_L2ERRDIS_SBECC));

		/* set L2E=0, L2SRAM=0 */
		clrbits_be32(&l2cache->l2ctl,
				(MPC85xx_L2CTL_L2E |
				 MPC85xx_L2CTL_L2SRAM_ENTIRE));
	}
#endif

	l2siz_field = (cache_ctl >> 28) & 0x3;

	switch (l2siz_field) {
	case 0x0:
		printf(" unknown size (0x%08x)\n", cache_ctl);
		return -1;
		break;
	case 0x1:
		if (ver == SVR_8540 || ver == SVR_8560   ||
		    ver == SVR_8541 || ver == SVR_8541_E ||
		    ver == SVR_8555 || ver == SVR_8555_E) {
			puts("128 KB ");
			/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
			cache_ctl = 0xc4000000;
		} else {
			puts("256 KB ");
			cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
		}
		break;
	case 0x2:
		if (ver == SVR_8540 || ver == SVR_8560   ||
		    ver == SVR_8541 || ver == SVR_8541_E ||
		    ver == SVR_8555 || ver == SVR_8555_E) {
			puts("256 KB ");
			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
			cache_ctl = 0xc8000000;
		} else {
			puts ("512 KB ");
			/* set L2E=1, L2I=1, & L2SRAM=0 */
			cache_ctl = 0xc0000000;
		}
		break;
	case 0x3:
		puts("1024 KB ");
		/* set L2E=1, L2I=1, & L2SRAM=0 */
		cache_ctl = 0xc0000000;
		break;
	}

	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
		puts("already enabled");
		l2srbar = l2cache->l2srbar0;
#ifdef CONFIG_SYS_INIT_L2_ADDR
		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
			l2cache->l2srbar0 = l2srbar;
			printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
		}
#endif /* CONFIG_SYS_INIT_L2_ADDR */
		puts("\n");
	} else {
		asm("msync;isync");
		l2cache->l2ctl = cache_ctl; /* invalidate & enable */
		asm("msync;isync");
		puts("enabled\n");
	}
#elif defined(CONFIG_BACKSIDE_L2_CACHE)
	u32 l2cfg0 = mfspr(SPRN_L2CFG0);

	/* invalidate the L2 cache */
	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
		;

#ifdef CONFIG_SYS_CACHE_STASHING
	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	mtspr(SPRN_L2CSR1, (32 + 1));
#endif

	/* enable the cache */
	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);

	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
		while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
			;
		printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
	}
#else
	puts("disabled\n");
#endif
#ifdef CONFIG_QE
	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
	qe_init(qe_base);
	qe_reset();
#endif

#if defined(CONFIG_MP)
	setup_mp();
#endif

#ifdef CONFIG_SYS_LBC_LCRR
	/*
	 * Modify the CLKDIV field of LCRR register to improve the writing
	 * speed for NOR flash.
	 */
	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
	__raw_readl(&lbc->lcrr);
	isync();
#endif

	return 0;
}

extern void setup_ivors(void);

void arch_preboot_os(void)
{
	u32 msr;

	/*
	 * We are changing interrupt offsets and are about to boot the OS so
	 * we need to make sure we disable all async interrupts. EE is already
	 * disabled by the time we get called.
	 */
	msr = mfmsr();
	msr &= ~(MSR_ME|MSR_CE|MSR_DE);
	mtmsr(msr);

	setup_ivors();
}

#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
int sata_initialize(void)
{
	if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
		return __sata_initialize();

	return 1;
}
#endif
Commit	Line	Data
42d1f039	1	/*
f54fe87a	2	* Copyright 2007-2010 Freescale Semiconductor, Inc.
29372ff3	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Modified by Xianghua Xiao, X.Xiao@motorola.com
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <common.h>
	30	#include <watchdog.h>
	31	#include <asm/processor.h>
	32	#include <ioports.h>
f54fe87a	33	#include <sata.h>
42d1f039	34	#include <asm/io.h>
87163180	35	#include <asm/mmu.h>
83d40dfd	36	#include <asm/fsl_law.h>
f54fe87a	37	#include <asm/fsl_serdes.h>
ec2b74ff	38	#include "mp.h"
42d1f039	39
d87080b7 WD	40	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	41
ef50d6c0 KG	42	#ifdef CONFIG_MPC8536
	43	extern void fsl_serdes_init(void);
	44	#endif
	45
da9d4610 AF	46	#ifdef CONFIG_QE
	47	extern qe_iop_conf_t qe_iop_conf_tab[];
	48	extern void qe_config_iopin(u8 port, u8 pin, int dir,
	49	int open_drain, int assign);
	50	extern void qe_init(uint qe_base);
	51	extern void qe_reset(void);
	52
	53	static void config_qe_ioports(void)
	54	{
	55	u8 port, pin;
	56	int dir, open_drain, assign;
	57	int i;
	58
	59	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
	60	port = qe_iop_conf_tab[i].port;
	61	pin = qe_iop_conf_tab[i].pin;
	62	dir = qe_iop_conf_tab[i].dir;
	63	open_drain = qe_iop_conf_tab[i].open_drain;
	64	assign = qe_iop_conf_tab[i].assign;
	65	qe_config_iopin(port, pin, dir, open_drain, assign);
	66	}
	67	}
	68	#endif
40d5fa35	69
9c4c5ae3	70	#ifdef CONFIG_CPM2
aafeefbd	71	void config_8560_ioports (volatile ccsr_cpm_t * cpm)
42d1f039 WD	72	{
	73	int portnum;
	74
	75	for (portnum = 0; portnum < 4; portnum++) {
	76	uint pmsk = 0,
	77	ppar = 0,
	78	psor = 0,
	79	pdir = 0,
	80	podr = 0,
	81	pdat = 0;
	82	iop_conf_t iopc = (iop_conf_t ) & iop_conf_tab[portnum][0];
	83	iop_conf_t *eiopc = iopc + 32;
	84	uint msk = 1;
	85
	86	/*
	87	* NOTE:
	88	* index 0 refers to pin 31,
	89	* index 31 refers to pin 0
	90	*/
	91	while (iopc < eiopc) {
	92	if (iopc->conf) {
	93	pmsk \|= msk;
	94	if (iopc->ppar)
	95	ppar \|= msk;
	96	if (iopc->psor)
	97	psor \|= msk;
	98	if (iopc->pdir)
	99	pdir \|= msk;
	100	if (iopc->podr)
	101	podr \|= msk;
	102	if (iopc->pdat)
	103	pdat \|= msk;
	104	}
	105
	106	msk <<= 1;
	107	iopc++;
	108	}
	109
	110	if (pmsk != 0) {
aafeefbd	111	volatile ioport_t *iop = ioport_addr (cpm, portnum);
42d1f039 WD	112	uint tpmsk = ~pmsk;
	113
	114	/*
	115	* the (somewhat confused) paragraph at the
	116	* bottom of page 35-5 warns that there might
	117	* be "unknown behaviour" when programming
	118	* PSORx and PDIRx, if PPARx = 1, so I
	119	* decided this meant I had to disable the
	120	* dedicated function first, and enable it
	121	* last.
	122	*/
	123	iop->ppar &= tpmsk;
	124	iop->psor = (iop->psor & tpmsk) \| psor;
	125	iop->podr = (iop->podr & tpmsk) \| podr;
	126	iop->pdat = (iop->pdat & tpmsk) \| pdat;
	127	iop->pdir = (iop->pdir & tpmsk) \| pdir;
	128	iop->ppar \|= ppar;
	129	}
	130	}
	131	}
	132	#endif
	133
	134	/*
	135	* Breathe some life into the CPU...
	136	*
	137	* Set up the memory map
	138	* initialize a bunch of registers
	139	*/
	140
3c2a67ee KG	141	#ifdef CONFIG_FSL_CORENET
	142	static void corenet_tb_init(void)
	143	{
	144	volatile ccsr_rcpm_t *rcpm =
	145	(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
	146	volatile ccsr_pic_t *pic =
	147	(void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
	148	u32 whoami = in_be32(&pic->whoami);
	149
	150	/* Enable the timebase register for this core */
	151	out_be32(&rcpm->ctbenrl, (1 << whoami));
	152	}
	153	#endif
	154
42d1f039 WD	155	void cpu_init_f (void)
42d1f039 WD	156	{
6d0f6bcf	157	volatile ccsr_lbc_t memctl = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
42d1f039	158	extern void m8560_cpm_reset (void);
a2cd50ed PT	159	#ifdef CONFIG_MPC8548
	160	ccsr_local_ecm_t ecm = (void )(CONFIG_SYS_MPC85xx_ECM_ADDR);
	161	uint svr = get_svr();
	162
	163	/*
	164	* CPU2 errata workaround: A core hang possible while executing
	165	* a msync instruction and a snoopable transaction from an I/O
	166	* master tagged to make quick forward progress is present.
	167	* Fixed in silicon rev 2.1.
	168	*/
	169	if ((SVR_MAJ(svr) == 1) \|\| ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
	170	out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) \| (1 << 16));
	171	#endif
42d1f039	172
87163180 KG	173	disable_tlb(14);
	174	disable_tlb(15);
	175
9c4c5ae3	176	#ifdef CONFIG_CPM2
6d0f6bcf	177	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
42d1f039 WD	178	#endif
	179
	180	/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
	181	* addresses - these have to be modified later when FLASH size
	182	* has been determined
	183	*/
6d0f6bcf	184	#if defined(CONFIG_SYS_OR0_REMAP)
4db9708b	185	out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
42d1f039	186	#endif
6d0f6bcf	187	#if defined(CONFIG_SYS_OR1_REMAP)
4db9708b	188	out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
42d1f039 WD	189	#endif
	190
	191	/* now restrict to preliminary range */
29372ff3 ES	192	/* if cs1 is already set via debugger, leave cs0/cs1 alone */
29372ff3 ES	193	if (! memctl->br1 & 1) {
6d0f6bcf	194	#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
4db9708b KG	195	out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
4db9708b KG	196	out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
42d1f039 WD	197	#endif
42d1f039 WD	198
6d0f6bcf	199	#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
4db9708b KG	200	out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
4db9708b KG	201	out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
42d1f039	202	#endif
29372ff3	203	}
42d1f039	204
6d0f6bcf	205	#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
4db9708b KG	206	out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
4db9708b KG	207	out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
42d1f039	208	#endif
42d1f039	209
6d0f6bcf	210	#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
4db9708b KG	211	out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
4db9708b KG	212	out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
42d1f039 WD	213	#endif
42d1f039 WD	214
6d0f6bcf	215	#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
4db9708b KG	216	out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
4db9708b KG	217	out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
42d1f039 WD	218	#endif
42d1f039 WD	219
6d0f6bcf	220	#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
4db9708b KG	221	out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
4db9708b KG	222	out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
42d1f039 WD	223	#endif
42d1f039 WD	224
6d0f6bcf	225	#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
4db9708b KG	226	out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
4db9708b KG	227	out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
42d1f039 WD	228	#endif
42d1f039 WD	229
6d0f6bcf	230	#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
4db9708b KG	231	out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
4db9708b KG	232	out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
42d1f039 WD	233	#endif
42d1f039 WD	234
9c4c5ae3	235	#if defined(CONFIG_CPM2)
42d1f039 WD	236	m8560_cpm_reset();
42d1f039 WD	237	#endif
da9d4610 AF	238	#ifdef CONFIG_QE
	239	/* Config QE ioports */
	240	config_qe_ioports();
	241	#endif
ef50d6c0 KG	242	#if defined(CONFIG_MPC8536)
	243	fsl_serdes_init();
	244	#endif
79f4333c PT	245	#if defined(CONFIG_FSL_DMA)
	246	dma_init();
	247	#endif
3c2a67ee KG	248	#ifdef CONFIG_FSL_CORENET
	249	corenet_tb_init();
	250	#endif
94e9411b	251	init_used_tlb_cams();
42d1f039 WD	252	}
42d1f039 WD	253
d9b94f28	254
42d1f039	255	/*
d9b94f28 JL	256	* Initialize L2 as cache.
	257	*
	258	* The newer 8548, etc, parts have twice as much cache, but
	259	* use the same bit-encoding as the older 8555, etc, parts.
	260	*
42d1f039	261	*/
d9b94f28 JL	262
d9b94f28 JL	263	int cpu_init_r(void)
42d1f039	264	{
3f0202ed LC	265	#ifdef CONFIG_SYS_LBC_LCRR
	266	volatile ccsr_lbc_t lbc = (void )(CONFIG_SYS_MPC85xx_LBC_ADDR);
	267	#endif
	268
6beecfbb WG	269	puts ("L2: ");
6beecfbb WG	270
42d1f039	271	#if defined(CONFIG_L2_CACHE)
6d0f6bcf	272	volatile ccsr_l2cache_t l2cache = (void )CONFIG_SYS_MPC85xx_L2_ADDR;
d9b94f28 JL	273	volatile uint cache_ctl;
d9b94f28 JL	274	uint svr, ver;
29372ff3	275	uint l2srbar;
73f15a06	276	u32 l2siz_field;
d9b94f28 JL	277
d9b94f28 JL	278	svr = get_svr();
f3e04bdc	279	ver = SVR_SOC_VER(svr);
42d1f039	280
d65cfe89	281	asm("msync;isync");
d9b94f28	282	cache_ctl = l2cache->l2ctl;
7da53351 MH	283
	284	#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
	285	if (cache_ctl & MPC85xx_L2CTL_L2E) {
	286	/* Clear L2 SRAM memory-mapped base address */
	287	out_be32(&l2cache->l2srbar0, 0x0);
	288	out_be32(&l2cache->l2srbar1, 0x0);
	289
	290	/* set MBECCDIS=0, SBECCDIS=0 */
	291	clrbits_be32(&l2cache->l2errdis,
	292	(MPC85xx_L2ERRDIS_MBECC \|
	293	MPC85xx_L2ERRDIS_SBECC));
	294
	295	/* set L2E=0, L2SRAM=0 */
	296	clrbits_be32(&l2cache->l2ctl,
	297	(MPC85xx_L2CTL_L2E \|
	298	MPC85xx_L2CTL_L2SRAM_ENTIRE));
	299	}
	300	#endif
	301
73f15a06	302	l2siz_field = (cache_ctl >> 28) & 0x3;
d9b94f28	303
73f15a06 KG	304	switch (l2siz_field) {
	305	case 0x0:
	306	printf(" unknown size (0x%08x)\n", cache_ctl);
	307	return -1;
	308	break;
	309	case 0x1:
	310	if (ver == SVR_8540 \|\| ver == SVR_8560 \|\|
	311	ver == SVR_8541 \|\| ver == SVR_8541_E \|\|
	312	ver == SVR_8555 \|\| ver == SVR_8555_E) {
	313	puts("128 KB ");
	314	/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 Kbyte) */
	315	cache_ctl = 0xc4000000;
d9b94f28	316	} else {
73f15a06 KG	317	puts("256 KB ");
	318	cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
	319	}
	320	break;
	321	case 0x2:
	322	if (ver == SVR_8540 \|\| ver == SVR_8560 \|\|
	323	ver == SVR_8541 \|\| ver == SVR_8541_E \|\|
	324	ver == SVR_8555 \|\| ver == SVR_8555_E) {
6beecfbb	325	puts("256 KB ");
29372ff3 ES	326	/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
29372ff3 ES	327	cache_ctl = 0xc8000000;
73f15a06 KG	328	} else {
	329	puts ("512 KB ");
	330	/* set L2E=1, L2I=1, & L2SRAM=0 */
	331	cache_ctl = 0xc0000000;
d9b94f28	332	}
d65cfe89	333	break;
73f15a06 KG	334	case 0x3:
	335	puts("1024 KB ");
	336	/* set L2E=1, L2I=1, & L2SRAM=0 */
	337	cache_ctl = 0xc0000000;
29372ff3	338	break;
d65cfe89 JL	339	}
d65cfe89 JL	340
76b474e2	341	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
6beecfbb	342	puts("already enabled");
29372ff3	343	l2srbar = l2cache->l2srbar0;
6d0f6bcf	344	#ifdef CONFIG_SYS_INIT_L2_ADDR
76b474e2 MH	345	if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
76b474e2 MH	346	&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
6d0f6bcf	347	l2srbar = CONFIG_SYS_INIT_L2_ADDR;
29372ff3	348	l2cache->l2srbar0 = l2srbar;
6d0f6bcf	349	printf("moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
29372ff3	350	}
6d0f6bcf	351	#endif /* CONFIG_SYS_INIT_L2_ADDR */
29372ff3 ES	352	puts("\n");
	353	} else {
	354	asm("msync;isync");
	355	l2cache->l2ctl = cache_ctl; /* invalidate & enable */
	356	asm("msync;isync");
6beecfbb	357	puts("enabled\n");
29372ff3	358	}
1b3e4044 KG	359	#elif defined(CONFIG_BACKSIDE_L2_CACHE)
	360	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
	361
	362	/* invalidate the L2 cache */
25bacf7a KG	363	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI\|L2CSR0_L2LFC));
25bacf7a KG	364	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI\|L2CSR0_L2LFC))
1b3e4044 KG	365	;
1b3e4044 KG	366
82fd1f8d KG	367	#ifdef CONFIG_SYS_CACHE_STASHING
	368	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
	369	mtspr(SPRN_L2CSR1, (32 + 1));
	370	#endif
	371
1b3e4044 KG	372	/* enable the cache */
	373	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
	374
654ea1f3 DL	375	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
	376	while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
	377	;
1b3e4044	378	printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64);
654ea1f3	379	}
42d1f039	380	#else
6beecfbb	381	puts("disabled\n");
42d1f039	382	#endif
da9d4610	383	#ifdef CONFIG_QE
6d0f6bcf	384	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
da9d4610 AF	385	qe_init(qe_base);
	386	qe_reset();
	387	#endif
42d1f039	388
ec2b74ff KG	389	#if defined(CONFIG_MP)
	390	setup_mp();
	391	#endif
3f0202ed LC	392
	393	#ifdef CONFIG_SYS_LBC_LCRR
	394	/*
	395	* Modify the CLKDIV field of LCRR register to improve the writing
	396	* speed for NOR flash.
	397	*/
	398	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
	399	__raw_readl(&lbc->lcrr);
	400	isync();
	401	#endif
	402
42d1f039 WD	403	return 0;
42d1f039 WD	404	}
26f4cdba KG	405
	406	extern void setup_ivors(void);
	407
	408	void arch_preboot_os(void)
	409	{
15fba327 KG	410	u32 msr;
	411
	412	/*
	413	* We are changing interrupt offsets and are about to boot the OS so
	414	* we need to make sure we disable all async interrupts. EE is already
	415	* disabled by the time we get called.
	416	*/
	417	msr = mfmsr();
	418	msr &= ~(MSR_ME\|MSR_CE\|MSR_DE);
	419	mtmsr(msr);
	420
26f4cdba KG	421	setup_ivors();
26f4cdba KG	422	}
f54fe87a KG	423
	424	#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
	425	int sata_initialize(void)
	426	{
	427	if (is_serdes_configured(SATA1) \|\| is_serdes_configured(SATA2))
	428	return __sata_initialize();
	429
	430	return 1;
	431	}
	432	#endif