[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / pci.c

/*
 * Copyright 2004 Freescale Semiconductor.
 * Copyright (C) 2003 Motorola Inc.
 * Xianghua Xiao (x.xiao@motorola.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * PCI Configuration space access support for MPC85xx PCI Bridge
 */
#include <common.h>
#include <asm/cpm_85xx.h>
#include <pci.h>

#if !defined(CONFIG_FSL_PCI_INIT)

#ifndef CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
#endif

#ifndef CONFIG_SYS_PCI1_IO_BUS
#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
#endif

#ifndef CONFIG_SYS_PCI2_MEM_BUS
#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
#endif

#ifndef CONFIG_SYS_PCI2_IO_BUS
#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
#endif

static struct pci_controller *pci_hose;

void
pci_mpc85xx_init(struct pci_controller *board_hose)
{
	u16 reg16;
	u32 dev;

	volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
#ifdef CONFIG_MPC85XX_PCI2
	volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
#endif
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	struct pci_controller * hose;

	pci_hose = board_hose;

	hose = &pci_hose[0];

	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_setup_indirect(hose,
			   (CONFIG_SYS_IMMR+0x8000),
			   (CONFIG_SYS_IMMR+0x8004));

	/*
	 * Hose scan.
	 */
	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);

	if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
		/* PCI-X init */
		if (CONFIG_SYS_CLK_FREQ < 66000000)
			printf("PCI-X will only work at 66 MHz\n");

		reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
			| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
		pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
	}

	pcix->potar1   = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
	pcix->potear1  = 0x00000000;
	pcix->powbar1  = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
	pcix->powbear1 = 0x00000000;
	pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
			POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));

	pcix->potar2  = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
	pcix->potear2  = 0x00000000;
	pcix->powbar2  = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
	pcix->powbear2 = 0x00000000;
	pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
			POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));

	pcix->pitar1 = 0x00000000;
	pcix->piwbar1 = 0x00000000;
	pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);

	pcix->powar3 = 0;
	pcix->powar4 = 0;
	pcix->piwar2 = 0;
	pcix->piwar3 = 0;

	pci_set_region(hose->regions + 0,
		       CONFIG_SYS_PCI1_MEM_BUS,
		       CONFIG_SYS_PCI1_MEM_PHYS,
		       CONFIG_SYS_PCI1_MEM_SIZE,
		       PCI_REGION_MEM);

	pci_set_region(hose->regions + 1,
		       CONFIG_SYS_PCI1_IO_BUS,
		       CONFIG_SYS_PCI1_IO_PHYS,
		       CONFIG_SYS_PCI1_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 2;

	pci_register_hose(hose);

#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
	/*
	 * This is a SW workaround for an apparent HW problem
	 * in the PCI controller on the MPC85555/41 CDS boards.
	 * The first config cycle must be to a valid, known
	 * device on the PCI bus in order to trick the PCI
	 * controller state machine into a known valid state.
	 * Without this, the first config cycle has the chance
	 * of hanging the controller permanently, just leaving
	 * it in a semi-working state, or leaving it working.
	 *
	 * Pick on the Tundra, Device 17, to get it right.
	 */
	{
		u8 header_type;

		pci_hose_read_config_byte(hose,
					  PCI_BDF(0,BRIDGE_ID,0),
					  PCI_HEADER_TYPE,
					  &header_type);
	}
#endif

	hose->last_busno = pci_hose_scan(hose);

#ifdef CONFIG_MPC85XX_PCI2
	hose = &pci_hose[1];

	hose->first_busno = pci_hose[0].last_busno + 1;
	hose->last_busno = 0xff;

	pci_setup_indirect(hose,
			   (CONFIG_SYS_IMMR+0x9000),
			   (CONFIG_SYS_IMMR+0x9004));

	dev = PCI_BDF(hose->first_busno, 0, 0);
	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);

	pcix2->potar1   = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
	pcix2->potear1  = 0x00000000;
	pcix2->powbar1  = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
	pcix2->powbear1 = 0x00000000;
	pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
			POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));

	pcix2->potar2  = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
	pcix2->potear2  = 0x00000000;
	pcix2->powbar2  = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
	pcix2->powbear2 = 0x00000000;
	pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
			POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));

	pcix2->pitar1 = 0x00000000;
	pcix2->piwbar1 = 0x00000000;
	pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);

	pcix2->powar3 = 0;
	pcix2->powar4 = 0;
	pcix2->piwar2 = 0;
	pcix2->piwar3 = 0;

	pci_set_region(hose->regions + 0,
		       CONFIG_SYS_PCI2_MEM_BUS,
		       CONFIG_SYS_PCI2_MEM_PHYS,
		       CONFIG_SYS_PCI2_MEM_SIZE,
		       PCI_REGION_MEM);

	pci_set_region(hose->regions + 1,
		       CONFIG_SYS_PCI2_IO_BUS,
		       CONFIG_SYS_PCI2_IO_PHYS,
		       CONFIG_SYS_PCI2_IO_SIZE,
		       PCI_REGION_IO);

	hose->region_count = 2;

	/*
	 * Hose scan.
	 */
	pci_register_hose(hose);

	hose->last_busno = pci_hose_scan(hose);
#endif
}
#endif /* !CONFIG_FSL_PCI_INIT */
Commit	Line	Data
42d1f039	1	/*
0ac6f8b7	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* Copyright (C) 2003 Motorola Inc.
	4	* Xianghua Xiao (x.xiao@motorola.com)
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* PCI Configuration space access support for MPC85xx PCI Bridge
	27	*/
	28	#include <common.h>
	29	#include <asm/cpm_85xx.h>
	30	#include <pci.h>
	31
5052a771	32	#if !defined(CONFIG_FSL_PCI_INIT)
0ac6f8b7	33
10795f42 KG	34	#ifndef CONFIG_SYS_PCI1_MEM_BUS
	35	#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
	36	#endif
	37
5f91ef6a KG	38	#ifndef CONFIG_SYS_PCI1_IO_BUS
	39	#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
	40	#endif
	41
10795f42 KG	42	#ifndef CONFIG_SYS_PCI2_MEM_BUS
	43	#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
	44	#endif
	45
5f91ef6a KG	46	#ifndef CONFIG_SYS_PCI2_IO_BUS
	47	#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
	48	#endif
	49
08745460 MM	50	static struct pci_controller *pci_hose;
08745460 MM	51
9aea9530	52	void
08745460	53	pci_mpc85xx_init(struct pci_controller *board_hose)
0ac6f8b7	54	{
08745460 MM	55	u16 reg16;
	56	u32 dev;
	57
6d0f6bcf	58	volatile ccsr_pcix_t pcix = (void )(CONFIG_SYS_MPC85xx_PCIX_ADDR);
7376eb87	59	#ifdef CONFIG_MPC85XX_PCI2
6d0f6bcf	60	volatile ccsr_pcix_t pcix2 = (void )(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
7376eb87	61	#endif
6d0f6bcf	62	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
08745460	63	struct pci_controller * hose;
0ac6f8b7	64
08745460 MM	65	pci_hose = board_hose;
	66
	67	hose = &pci_hose[0];
0ac6f8b7 WD	68
	69	hose->first_busno = 0;
	70	hose->last_busno = 0xff;
	71
9aea9530	72	pci_setup_indirect(hose,
6d0f6bcf JCPV	73	(CONFIG_SYS_IMMR+0x8000),
6d0f6bcf JCPV	74	(CONFIG_SYS_IMMR+0x8004));
0ac6f8b7	75
08745460 MM	76	/*
	77	* Hose scan.
	78	*/
	79	dev = PCI_BDF(hose->first_busno, 0, 0);
	80	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	81	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	82	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
	83
	84	/*
	85	* Clear non-reserved bits in status register.
	86	*/
	87	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	88
9427ccde	89	if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
08745460	90	/* PCI-X init */
38433ccc MM	91	if (CONFIG_SYS_CLK_FREQ < 66000000)
	92	printf("PCI-X will only work at 66 MHz\n");
	93
08745460 MM	94	reg16 = PCI_X_CMD_MAX_SPLIT \| PCI_X_CMD_MAX_READ
	95	\| PCI_X_CMD_ERO \| PCI_X_CMD_DPERR_E;
	96	pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
	97	}
	98
10795f42	99	pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
9aea9530	100	pcix->potear1 = 0x00000000;
6d0f6bcf	101	pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
0ac6f8b7	102	pcix->powbear1 = 0x00000000;
08745460	103	pcix->powar1 = (POWAR_EN \| POWAR_MEM_READ \|
6d0f6bcf	104	POWAR_MEM_WRITE \| (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
0ac6f8b7	105
5f91ef6a	106	pcix->potar2 = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
9aea9530	107	pcix->potear2 = 0x00000000;
6d0f6bcf	108	pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
0ac6f8b7	109	pcix->powbear2 = 0x00000000;
08745460	110	pcix->powar2 = (POWAR_EN \| POWAR_IO_READ \|
6d0f6bcf	111	POWAR_IO_WRITE \| (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
0ac6f8b7 WD	112
	113	pcix->pitar1 = 0x00000000;
	114	pcix->piwbar1 = 0x00000000;
08745460 MM	115	pcix->piwar1 = (PIWAR_EN \| PIWAR_PF \| PIWAR_LOCAL \|
08745460 MM	116	PIWAR_READ_SNOOP \| PIWAR_WRITE_SNOOP \| PIWAR_MEM_2G);
0ac6f8b7	117
08745460 MM	118	pcix->powar3 = 0;
	119	pcix->powar4 = 0;
	120	pcix->piwar2 = 0;
	121	pcix->piwar3 = 0;
cf33678e	122
08745460	123	pci_set_region(hose->regions + 0,
10795f42	124	CONFIG_SYS_PCI1_MEM_BUS,
6d0f6bcf JCPV	125	CONFIG_SYS_PCI1_MEM_PHYS,
6d0f6bcf JCPV	126	CONFIG_SYS_PCI1_MEM_SIZE,
08745460	127	PCI_REGION_MEM);
527b5a51	128
08745460	129	pci_set_region(hose->regions + 1,
5f91ef6a	130	CONFIG_SYS_PCI1_IO_BUS,
6d0f6bcf JCPV	131	CONFIG_SYS_PCI1_IO_PHYS,
6d0f6bcf JCPV	132	CONFIG_SYS_PCI1_IO_SIZE,
08745460 MM	133	PCI_REGION_IO);
	134
	135	hose->region_count = 2;
	136
	137	pci_register_hose(hose);
527b5a51	138
cf33678e WD	139	#if defined(CONFIG_MPC8555CDS) \|\| defined(CONFIG_MPC8541CDS)
	140	/*
	141	* This is a SW workaround for an apparent HW problem
	142	* in the PCI controller on the MPC85555/41 CDS boards.
	143	* The first config cycle must be to a valid, known
	144	* device on the PCI bus in order to trick the PCI
	145	* controller state machine into a known valid state.
	146	* Without this, the first config cycle has the chance
	147	* of hanging the controller permanently, just leaving
	148	* it in a semi-working state, or leaving it working.
	149	*
	150	* Pick on the Tundra, Device 17, to get it right.
	151	*/
	152	{
	153	u8 header_type;
	154
	155	pci_hose_read_config_byte(hose,
7f3f2bd2	156	PCI_BDF(0,BRIDGE_ID,0),
cf33678e WD	157	PCI_HEADER_TYPE,
	158	&header_type);
	159	}
cf33678e WD	160	#endif
cf33678e WD	161
9aea9530	162	hose->last_busno = pci_hose_scan(hose);
08745460 MM	163
	164	#ifdef CONFIG_MPC85XX_PCI2
	165	hose = &pci_hose[1];
	166
	167	hose->first_busno = pci_hose[0].last_busno + 1;
	168	hose->last_busno = 0xff;
	169
	170	pci_setup_indirect(hose,
6d0f6bcf JCPV	171	(CONFIG_SYS_IMMR+0x9000),
6d0f6bcf JCPV	172	(CONFIG_SYS_IMMR+0x9004));
08745460 MM	173
	174	dev = PCI_BDF(hose->first_busno, 0, 0);
	175	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
	176	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	177	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
	178
	179	/*
	180	* Clear non-reserved bits in status register.
	181	*/
	182	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
	183
10795f42	184	pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
08745460	185	pcix2->potear1 = 0x00000000;
6d0f6bcf	186	pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
08745460 MM	187	pcix2->powbear1 = 0x00000000;
08745460 MM	188	pcix2->powar1 = (POWAR_EN \| POWAR_MEM_READ \|
6d0f6bcf	189	POWAR_MEM_WRITE \| (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
08745460	190
5f91ef6a	191	pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
08745460	192	pcix2->potear2 = 0x00000000;
6d0f6bcf	193	pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
08745460 MM	194	pcix2->powbear2 = 0x00000000;
08745460 MM	195	pcix2->powar2 = (POWAR_EN \| POWAR_IO_READ \|
6d0f6bcf	196	POWAR_IO_WRITE \| (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
08745460 MM	197
	198	pcix2->pitar1 = 0x00000000;
	199	pcix2->piwbar1 = 0x00000000;
	200	pcix2->piwar1 = (PIWAR_EN \| PIWAR_PF \| PIWAR_LOCAL \|
	201	PIWAR_READ_SNOOP \| PIWAR_WRITE_SNOOP \| PIWAR_MEM_2G);
	202
	203	pcix2->powar3 = 0;
	204	pcix2->powar4 = 0;
	205	pcix2->piwar2 = 0;
	206	pcix2->piwar3 = 0;
	207
	208	pci_set_region(hose->regions + 0,
10795f42	209	CONFIG_SYS_PCI2_MEM_BUS,
6d0f6bcf JCPV	210	CONFIG_SYS_PCI2_MEM_PHYS,
6d0f6bcf JCPV	211	CONFIG_SYS_PCI2_MEM_SIZE,
08745460 MM	212	PCI_REGION_MEM);
	213
	214	pci_set_region(hose->regions + 1,
5f91ef6a	215	CONFIG_SYS_PCI2_IO_BUS,
6d0f6bcf JCPV	216	CONFIG_SYS_PCI2_IO_PHYS,
6d0f6bcf JCPV	217	CONFIG_SYS_PCI2_IO_SIZE,
08745460 MM	218	PCI_REGION_IO);
	219
	220	hose->region_count = 2;
	221
	222	/*
	223	* Hose scan.
	224	*/
	225	pci_register_hose(hose);
	226
	227	hose->last_busno = pci_hose_scan(hose);
	228	#endif
42d1f039	229	}
5052a771	230	#endif /* !CONFIG_FSL_PCI_INIT */