[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / speed.c

/*
 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2003 Motorola Inc.
 * Xianghua Xiao, (X.Xiao@motorola.com)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <ppc_asm.tmpl>
#include <linux/compiler.h>
#include <asm/processor.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

/* --------------------------------------------------------------- */

void get_sys_info (sys_info_t * sysInfo)
{
	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_IFC
	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
	u32 ccr;
#endif
#ifdef CONFIG_FSL_CORENET
	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
	unsigned int cpu;

	const u8 core_cplx_PLL[16] = {
		[ 0] = 0,	/* CC1 PPL / 1 */
		[ 1] = 0,	/* CC1 PPL / 2 */
		[ 2] = 0,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 1,	/* CC2 PPL / 2 */
		[ 6] = 1,	/* CC2 PPL / 4 */
		[ 8] = 2,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 2,	/* CC3 PPL / 4 */
		[12] = 3,	/* CC4 PPL / 1 */
		[13] = 3,	/* CC4 PPL / 2 */
		[14] = 3,	/* CC4 PPL / 4 */
	};

	const u8 core_cplx_PLL_div[16] = {
		[ 0] = 1,	/* CC1 PPL / 1 */
		[ 1] = 2,	/* CC1 PPL / 2 */
		[ 2] = 4,	/* CC1 PPL / 4 */
		[ 4] = 1,	/* CC2 PPL / 1 */
		[ 5] = 2,	/* CC2 PPL / 2 */
		[ 6] = 4,	/* CC2 PPL / 4 */
		[ 8] = 1,	/* CC3 PPL / 1 */
		[ 9] = 2,	/* CC3 PPL / 2 */
		[10] = 4,	/* CC3 PPL / 4 */
		[12] = 1,	/* CC4 PPL / 1 */
		[13] = 2,	/* CC4 PPL / 2 */
		[14] = 4,	/* CC4 PPL / 4 */
	};
	uint i, freqCC_PLL[6], rcw_tmp;
	uint ratio[6];
	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
	uint mem_pll_rat;

	sysInfo->freqSystemBus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
	sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
#else
	sysInfo->freqDDRBus = sysclk;
#endif

	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
	if (mem_pll_rat > 2)
		sysInfo->freqDDRBus *= mem_pll_rat;
	else
		sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;

	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
	ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
	ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
	for (i = 0; i < 6; i++) {
		if (ratio[i] > 4)
			freqCC_PLL[i] = sysclk * ratio[i];
		else
			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
	}
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	/*
	 * Each cluster has up to 4 cores, sharing the same PLL selection.
	 * The cluster assignment is fixed per SoC. There is no way identify the
	 * assignment so far, presuming the "first configuration" which is to
	 * fill the lower cluster group first before moving up to next group.
	 * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
	 * and core 4~7 on cluster 2
	 * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
	 * and core 12~15 on cluster 4 if existing
	 */
	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
				& 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
		if (cplx_pll > 3)
			printf("Unsupported architecture configuration"
				" in function %s\n", __func__);
		cplx_pll += (cpu / 8) * 3;

		sysInfo->freqProcessor[cpu] =
			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	}
#define PME_CLK_SEL	0xe0000000
#define PME_CLK_SHIFT	29
#define FM1_CLK_SEL	0x1c000000
#define FM1_CLK_SHIFT	26
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
	case 1:
		sysInfo->freqPME = freqCC_PLL[0];
		break;
	case 2:
		sysInfo->freqPME = freqCC_PLL[0] / 2;
		break;
	case 3:
		sysInfo->freqPME = freqCC_PLL[0] / 3;
		break;
	case 4:
		sysInfo->freqPME = freqCC_PLL[0] / 4;
		break;
	case 6:
		sysInfo->freqPME = freqCC_PLL[1] / 2;
		break;
	case 7:
		sysInfo->freqPME = freqCC_PLL[1] / 3;
		break;
	default:
		printf("Error: Unknown PME clock select!\n");
	case 0:
		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
		break;

	}
#endif

#ifdef CONFIG_SYS_DPAA_QBMAN
	sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
	case 1:
		sysInfo->freqFMan[0] = freqCC_PLL[3];
		break;
	case 2:
		sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
		break;
	case 3:
		sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
		break;
	case 4:
		sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
		break;
	case 6:
		sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
		break;
	case 7:
		sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
		break;
	default:
		printf("Error: Unknown FMan1 clock select!\n");
	case 0:
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
		break;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
#define FM2_CLK_SEL	0x00000038
#define FM2_CLK_SHIFT	3
	rcw_tmp = in_be32(&gur->rcwsr[15]);
	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	case 1:
		sysInfo->freqFMan[1] = freqCC_PLL[4];
		break;
	case 2:
		sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
		break;
	case 3:
		sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
		break;
	case 4:
		sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
		break;
	case 6:
		sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
		break;
	case 7:
		sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
		break;
	default:
		printf("Error: Unknown FMan2 clock select!\n");
	case 0:
		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
		break;
	}
#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
#endif	/* CONFIG_SYS_DPAA_FMAN */

#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
		u32 cplx_pll = core_cplx_PLL[c_pll_sel];

		sysInfo->freqProcessor[cpu] =
			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	}
#define PME_CLK_SEL	0x80000000
#define FM1_CLK_SEL	0x40000000
#define FM2_CLK_SEL	0x20000000
#define HWA_ASYNC_DIV	0x04000000
#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
#define HWA_CC_PLL	1
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
#define HWA_CC_PLL	2
#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
#define HWA_CC_PLL	2
#else
#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
#endif
	rcw_tmp = in_be32(&gur->rcwsr[7]);

#ifdef CONFIG_SYS_DPAA_PME
	if (rcw_tmp & PME_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
	}
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
	if (rcw_tmp & FM1_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
	}
#if (CONFIG_SYS_NUM_FMAN) == 2
	if (rcw_tmp & FM2_CLK_SEL) {
		if (rcw_tmp & HWA_ASYNC_DIV)
			sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
		else
			sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
	} else {
		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
	}
#endif
#endif

#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */

#else /* CONFIG_FSL_CORENET */
	uint plat_ratio, e500_ratio, half_freqSystemBus;
	int i;
#ifdef CONFIG_QE
	__maybe_unused u32 qe_ratio;
#endif

	plat_ratio = (gur->porpllsr) & 0x0000003e;
	plat_ratio >>= 1;
	sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;

	/* Divide before multiply to avoid integer
	 * overflow for processor speeds above 2GHz */
	half_freqSystemBus = sysInfo->freqSystemBus/2;
	for (i = 0; i < cpu_numcores(); i++) {
		e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
		sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
	}

	/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
	sysInfo->freqDDRBus = sysInfo->freqSystemBus;

#ifdef CONFIG_DDR_CLK_FREQ
	{
		u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
			>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
		if (ddr_ratio != 0x7)
			sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	}
#endif

#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
	sysInfo->freqQE =  sysInfo->freqSystemBus;
#else
	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
#endif

#ifdef CONFIG_SYS_DPAA_FMAN
		sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
#endif

#endif /* CONFIG_FSL_CORENET */

#if defined(CONFIG_FSL_LBC)
	uint lcrr_div;
#if defined(CONFIG_SYS_LBC_LCRR)
	/* We will program LCRR to this value later */
	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
#else
	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
#endif
	if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
#if defined(CONFIG_FSL_CORENET)
		/* If this is corenet based SoC, bit-representation
		 * for four times the clock divider values.
		 */
		lcrr_div *= 4;
#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
    !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
		/*
		 * Yes, the entire PQ38 family use the same
		 * bit-representation for twice the clock divider values.
		 */
		lcrr_div *= 2;
#endif
		sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
	} else {
		/* In case anyone cares what the unknown value is */
		sysInfo->freqLocalBus = lcrr_div;
	}
#endif

#if defined(CONFIG_FSL_IFC)
	ccr = in_be32(&ifc_regs->ifc_ccr);
	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;

	sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
#endif
}


int get_clocks (void)
{
	sys_info_t sys_info;
#ifdef CONFIG_MPC8544
	volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
#endif
#if defined(CONFIG_CPM2)
	volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
	uint sccr, dfbrg;

	/* set VCO = 4 * BRG */
	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
	sccr = cpm->im_cpm_intctl.sccr;
	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
#endif
	get_sys_info (&sys_info);
	gd->cpu_clk = sys_info.freqProcessor[0];
	gd->bus_clk = sys_info.freqSystemBus;
	gd->mem_clk = sys_info.freqDDRBus;
	gd->lbc_clk = sys_info.freqLocalBus;

#ifdef CONFIG_QE
	gd->qe_clk = sys_info.freqQE;
	gd->arch.brg_clk = gd->qe_clk / 2;
#endif
	/*
	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
	 * there is no pattern that can be used to determine the frequency, so
	 * the only choice is to look up the actual SOC number and use the value
	 * for that SOC. This information is taken from application note
	 * AN2919.
	 */
#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
	defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
	gd->i2c1_clk = sys_info.freqSystemBus;
#elif defined(CONFIG_MPC8544)
	/*
	 * On the 8544, the I2C clock is the same as the SEC clock.  This can be
	 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	 * 4.4.3.3 of the 8544 RM.  Note that this might actually work for all
	 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	 */
	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
		gd->i2c1_clk = sys_info.freqSystemBus / 3;
	else
		gd->i2c1_clk = sys_info.freqSystemBus / 2;
#else
	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	gd->i2c1_clk = sys_info.freqSystemBus / 2;
#endif
	gd->i2c2_clk = gd->i2c1_clk;

#if defined(CONFIG_FSL_ESDHC)
#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
       defined(CONFIG_P1014)
	gd->sdhc_clk = gd->bus_clk;
#else
	gd->sdhc_clk = gd->bus_clk / 2;
#endif
#endif /* defined(CONFIG_FSL_ESDHC) */

#if defined(CONFIG_CPM2)
	gd->vco_out = 2*sys_info.freqSystemBus;
	gd->cpm_clk = gd->vco_out / 2;
	gd->scc_clk = gd->vco_out / 4;
	gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
#endif

	if(gd->cpu_clk != 0) return (0);
	else return (1);
}


/********************************************
 * get_bus_freq
 * return system bus freq in Hz
 *********************************************/
ulong get_bus_freq (ulong dummy)
{
	return gd->bus_clk;
}

/********************************************
 * get_ddr_freq
 * return ddr bus freq in Hz
 *********************************************/
ulong get_ddr_freq (ulong dummy)
{
	return gd->mem_clk;
}
Commit	Line	Data
42d1f039	1	/*
beba93ed	2	* Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
39aaca1f	3	*
42d1f039 WD	4	* (C) Copyright 2003 Motorola Inc.
	5	* Xianghua Xiao, (X.Xiao@motorola.com)
	6	*
	7	* (C) Copyright 2000
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <common.h>
	30	#include <ppc_asm.tmpl>
a52d2f81	31	#include <linux/compiler.h>
42d1f039	32	#include <asm/processor.h>
ada591d2	33	#include <asm/io.h>
42d1f039	34
d87080b7 WD	35	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	36
42d1f039 WD	37	/* --------------------------------------------------------------- */
42d1f039 WD	38
42d1f039 WD	39	void get_sys_info (sys_info_t * sysInfo)
42d1f039 WD	40	{
6d0f6bcf	41	volatile ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
800c73c4 KG	42	#ifdef CONFIG_FSL_IFC
	43	struct fsl_ifc ifc_regs = (void )CONFIG_SYS_IFC_ADDR;
	44	u32 ccr;
	45	#endif
39aaca1f KG	46	#ifdef CONFIG_FSL_CORENET
39aaca1f KG	47	volatile ccsr_clk_t clk = (void )(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
fbb9ecf7	48	unsigned int cpu;
39aaca1f KG	49
	50	const u8 core_cplx_PLL[16] = {
	51	[ 0] = 0, /* CC1 PPL / 1 */
	52	[ 1] = 0, /* CC1 PPL / 2 */
	53	[ 2] = 0, /* CC1 PPL / 4 */
	54	[ 4] = 1, /* CC2 PPL / 1 */
	55	[ 5] = 1, /* CC2 PPL / 2 */
	56	[ 6] = 1, /* CC2 PPL / 4 */
	57	[ 8] = 2, /* CC3 PPL / 1 */
	58	[ 9] = 2, /* CC3 PPL / 2 */
	59	[10] = 2, /* CC3 PPL / 4 */
	60	[12] = 3, /* CC4 PPL / 1 */
	61	[13] = 3, /* CC4 PPL / 2 */
	62	[14] = 3, /* CC4 PPL / 4 */
	63	};
	64
	65	const u8 core_cplx_PLL_div[16] = {
	66	[ 0] = 1, /* CC1 PPL / 1 */
	67	[ 1] = 2, /* CC1 PPL / 2 */
	68	[ 2] = 4, /* CC1 PPL / 4 */
	69	[ 4] = 1, /* CC2 PPL / 1 */
	70	[ 5] = 2, /* CC2 PPL / 2 */
	71	[ 6] = 4, /* CC2 PPL / 4 */
	72	[ 8] = 1, /* CC3 PPL / 1 */
	73	[ 9] = 2, /* CC3 PPL / 2 */
	74	[10] = 4, /* CC3 PPL / 4 */
	75	[12] = 1, /* CC4 PPL / 1 */
	76	[13] = 2, /* CC4 PPL / 2 */
	77	[14] = 4, /* CC4 PPL / 4 */
	78	};
9a653a98 YS	79	uint i, freqCC_PLL[6], rcw_tmp;
9a653a98 YS	80	uint ratio[6];
39aaca1f	81	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
ab48ca1a	82	uint mem_pll_rat;
39aaca1f KG	83
39aaca1f KG	84	sysInfo->freqSystemBus = sysclk;
98ffa190 YS	85	#ifdef CONFIG_DDR_CLK_FREQ
	86	sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
	87	#else
39aaca1f	88	sysInfo->freqDDRBus = sysclk;
98ffa190	89	#endif
39aaca1f	90
93cedc71	91	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
f77329cf YS	92	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
	93	FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
	94	& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
ab48ca1a SS	95	if (mem_pll_rat > 2)
	96	sysInfo->freqDDRBus *= mem_pll_rat;
	97	else
	98	sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
39aaca1f	99
ab48ca1a SS	100	ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
	101	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
	102	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
	103	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
9a653a98 YS	104	ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
	105	ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
	106	for (i = 0; i < 6; i++) {
ab48ca1a SS	107	if (ratio[i] > 4)
	108	freqCC_PLL[i] = sysclk * ratio[i];
	109	else
	110	freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
	111	}
9a653a98 YS	112	#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
	113	/*
	114	* Each cluster has up to 4 cores, sharing the same PLL selection.
	115	* The cluster assignment is fixed per SoC. There is no way identify the
	116	* assignment so far, presuming the "first configuration" which is to
	117	* fill the lower cluster group first before moving up to next group.
	118	* PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
	119	* and core 4~7 on cluster 2
	120	* PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
	121	* and core 12~15 on cluster 4 if existing
	122	*/
fbb9ecf7	123	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
9a653a98 YS	124	u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
9a653a98 YS	125	& 0xf;
39aaca1f	126	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
9a653a98 YS	127	if (cplx_pll > 3)
	128	printf("Unsupported architecture configuration"
	129	" in function %s\n", __func__);
	130	cplx_pll += (cpu / 8) * 3;
39aaca1f	131
fbb9ecf7	132	sysInfo->freqProcessor[cpu] =
39aaca1f KG	133	freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
39aaca1f KG	134	}
9a653a98 YS	135	#define PME_CLK_SEL 0xe0000000
	136	#define PME_CLK_SHIFT 29
	137	#define FM1_CLK_SEL 0x1c000000
	138	#define FM1_CLK_SHIFT 26
	139	rcw_tmp = in_be32(&gur->rcwsr[7]);
	140
	141	#ifdef CONFIG_SYS_DPAA_PME
	142	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
	143	case 1:
	144	sysInfo->freqPME = freqCC_PLL[0];
	145	break;
	146	case 2:
	147	sysInfo->freqPME = freqCC_PLL[0] / 2;
	148	break;
	149	case 3:
	150	sysInfo->freqPME = freqCC_PLL[0] / 3;
	151	break;
	152	case 4:
	153	sysInfo->freqPME = freqCC_PLL[0] / 4;
	154	break;
	155	case 6:
	156	sysInfo->freqPME = freqCC_PLL[1] / 2;
	157	break;
	158	case 7:
	159	sysInfo->freqPME = freqCC_PLL[1] / 3;
	160	break;
	161	default:
	162	printf("Error: Unknown PME clock select!\n");
	163	case 0:
	164	sysInfo->freqPME = sysInfo->freqSystemBus / 2;
	165	break;
	166
	167	}
	168	#endif
	169
990e1a8c HW	170	#ifdef CONFIG_SYS_DPAA_QBMAN
	171	sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
	172	#endif
	173
9a653a98 YS	174	#ifdef CONFIG_SYS_DPAA_FMAN
	175	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
	176	case 1:
	177	sysInfo->freqFMan[0] = freqCC_PLL[3];
	178	break;
	179	case 2:
	180	sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
	181	break;
	182	case 3:
	183	sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
	184	break;
	185	case 4:
	186	sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
	187	break;
	188	case 6:
	189	sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
	190	break;
	191	case 7:
	192	sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
	193	break;
	194	default:
	195	printf("Error: Unknown FMan1 clock select!\n");
	196	case 0:
	197	sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
	198	break;
	199	}
	200	#if (CONFIG_SYS_NUM_FMAN) == 2
	201	#define FM2_CLK_SEL 0x00000038
	202	#define FM2_CLK_SHIFT 3
	203	rcw_tmp = in_be32(&gur->rcwsr[15]);
	204	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
	205	case 1:
	206	sysInfo->freqFMan[1] = freqCC_PLL[4];
	207	break;
	208	case 2:
	209	sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
	210	break;
	211	case 3:
	212	sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
	213	break;
	214	case 4:
	215	sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
	216	break;
	217	case 6:
	218	sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
	219	break;
	220	case 7:
	221	sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
	222	break;
	223	default:
	224	printf("Error: Unknown FMan2 clock select!\n");
	225	case 0:
	226	sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
	227	break;
	228	}
	229	#endif /* CONFIG_SYS_NUM_FMAN == 2 */
	230	#endif /* CONFIG_SYS_DPAA_FMAN */
39aaca1f	231
9a653a98 YS	232	#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	233
	234	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
	235	u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
	236	u32 cplx_pll = core_cplx_PLL[c_pll_sel];
	237
	238	sysInfo->freqProcessor[cpu] =
	239	freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
	240	}
39aaca1f KG	241	#define PME_CLK_SEL 0x80000000
	242	#define FM1_CLK_SEL 0x40000000
	243	#define FM2_CLK_SEL 0x20000000
b5c8753f KG	244	#define HWA_ASYNC_DIV 0x04000000
	245	#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
	246	#define HWA_CC_PLL 1
4905443f TT	247	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
4905443f TT	248	#define HWA_CC_PLL 2
b5c8753f	249	#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
cd6881b5	250	#define HWA_CC_PLL 2
b5c8753f KG	251	#else
	252	#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
	253	#endif
39aaca1f KG	254	rcw_tmp = in_be32(&gur->rcwsr[7]);
	255
	256	#ifdef CONFIG_SYS_DPAA_PME
b5c8753f KG	257	if (rcw_tmp & PME_CLK_SEL) {
	258	if (rcw_tmp & HWA_ASYNC_DIV)
	259	sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 4;
	260	else
	261	sysInfo->freqPME = freqCC_PLL[HWA_CC_PLL] / 2;
	262	} else {
693416fe	263	sysInfo->freqPME = sysInfo->freqSystemBus / 2;
b5c8753f	264	}
39aaca1f KG	265	#endif
	266
	267	#ifdef CONFIG_SYS_DPAA_FMAN
b5c8753f KG	268	if (rcw_tmp & FM1_CLK_SEL) {
	269	if (rcw_tmp & HWA_ASYNC_DIV)
	270	sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 4;
	271	else
	272	sysInfo->freqFMan[0] = freqCC_PLL[HWA_CC_PLL] / 2;
	273	} else {
693416fe	274	sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
b5c8753f	275	}
39aaca1f	276	#if (CONFIG_SYS_NUM_FMAN) == 2
b5c8753f KG	277	if (rcw_tmp & FM2_CLK_SEL) {
	278	if (rcw_tmp & HWA_ASYNC_DIV)
	279	sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 4;
	280	else
	281	sysInfo->freqFMan[1] = freqCC_PLL[HWA_CC_PLL] / 2;
	282	} else {
693416fe	283	sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
b5c8753f	284	}
39aaca1f KG	285	#endif
	286	#endif
	287
9a653a98 YS	288	#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
	289
	290	#else /* CONFIG_FSL_CORENET */
	291	uint plat_ratio, e500_ratio, half_freqSystemBus;
2fc7eb0c	292	int i;
b3d7f20f	293	#ifdef CONFIG_QE
a52d2f81	294	__maybe_unused u32 qe_ratio;
b3d7f20f	295	#endif
42d1f039 WD	296
	297	plat_ratio = (gur->porpllsr) & 0x0000003e;
	298	plat_ratio >>= 1;
66ed6cca	299	sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
66ed6cca AF	300
	301	/* Divide before multiply to avoid integer
	302	* overflow for processor speeds above 2GHz */
	303	half_freqSystemBus = sysInfo->freqSystemBus/2;
0e870980	304	for (i = 0; i < cpu_numcores(); i++) {
2fc7eb0c HW	305	e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
	306	sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
	307	}
a3e77fa5 JY	308
a3e77fa5 JY	309	/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
d4357932 KG	310	sysInfo->freqDDRBus = sysInfo->freqSystemBus;
	311
	312	#ifdef CONFIG_DDR_CLK_FREQ
	313	{
c0391111 JJ	314	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
c0391111 JJ	315	>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
d4357932 KG	316	if (ddr_ratio != 0x7)
	317	sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
	318	}
	319	#endif
ada591d2	320
b3d7f20f	321	#ifdef CONFIG_QE
be7bebea	322	#if defined(CONFIG_P1012) \|\| defined(CONFIG_P1021) \|\| defined(CONFIG_P1025)
a52d2f81 HW	323	sysInfo->freqQE = sysInfo->freqSystemBus;
a52d2f81 HW	324	#else
b3d7f20f HW	325	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
	326	>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
	327	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
	328	#endif
a52d2f81	329	#endif
b3d7f20f	330
24995d82	331	#ifdef CONFIG_SYS_DPAA_FMAN
939cdcdc	332	sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
24995d82 HW	333	#endif
	334
	335	#endif /* CONFIG_FSL_CORENET */
	336
beba93ed	337	#if defined(CONFIG_FSL_LBC)
9a653a98	338	uint lcrr_div;
ada591d2 TP	339	#if defined(CONFIG_SYS_LBC_LCRR)
	340	/* We will program LCRR to this value later */
	341	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
	342	#else
f51cdaf1	343	lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
ada591d2 TP	344	#endif
ada591d2 TP	345	if (lcrr_div == 2 \|\| lcrr_div == 4 \|\| lcrr_div == 8) {
0fd2fa6c DL	346	#if defined(CONFIG_FSL_CORENET)
	347	/* If this is corenet based SoC, bit-representation
	348	* for four times the clock divider values.
	349	*/
	350	lcrr_div *= 4;
	351	#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
ada591d2 TP	352	!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
	353	/*
	354	* Yes, the entire PQ38 family use the same
	355	* bit-representation for twice the clock divider values.
	356	*/
	357	lcrr_div *= 2;
	358	#endif
	359	sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
	360	} else {
	361	/* In case anyone cares what the unknown value is */
	362	sysInfo->freqLocalBus = lcrr_div;
	363	}
beba93ed	364	#endif
800c73c4 KG	365
	366	#if defined(CONFIG_FSL_IFC)
	367	ccr = in_be32(&ifc_regs->ifc_ccr);
	368	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
	369
	370	sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
	371	#endif
42d1f039 WD	372	}
42d1f039 WD	373
66ed6cca	374
42d1f039 WD	375	int get_clocks (void)
42d1f039 WD	376	{
42d1f039	377	sys_info_t sys_info;
88353a98	378	#ifdef CONFIG_MPC8544
6d0f6bcf	379	volatile ccsr_gur_t gur = (void ) CONFIG_SYS_MPC85xx_GUTS_ADDR;
88353a98	380	#endif
9c4c5ae3	381	#if defined(CONFIG_CPM2)
6d0f6bcf	382	volatile ccsr_cpm_t cpm = (ccsr_cpm_t )CONFIG_SYS_MPC85xx_CPM_ADDR;
42d1f039 WD	383	uint sccr, dfbrg;
	384
	385	/* set VCO = 4 * BRG */
aafeefbd KG	386	cpm->im_cpm_intctl.sccr &= 0xfffffffc;
aafeefbd KG	387	sccr = cpm->im_cpm_intctl.sccr;
42d1f039 WD	388	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
	389	#endif
	390	get_sys_info (&sys_info);
2fc7eb0c	391	gd->cpu_clk = sys_info.freqProcessor[0];
42d1f039	392	gd->bus_clk = sys_info.freqSystemBus;
a3e77fa5	393	gd->mem_clk = sys_info.freqDDRBus;
ada591d2	394	gd->lbc_clk = sys_info.freqLocalBus;
88353a98	395
b3d7f20f HW	396	#ifdef CONFIG_QE
b3d7f20f HW	397	gd->qe_clk = sys_info.freqQE;
1206c184	398	gd->arch.brg_clk = gd->qe_clk / 2;
b3d7f20f	399	#endif
88353a98 TT	400	/*
	401	* The base clock for I2C depends on the actual SOC. Unfortunately,
	402	* there is no pattern that can be used to determine the frequency, so
	403	* the only choice is to look up the actual SOC number and use the value
	404	* for that SOC. This information is taken from application note
	405	* AN2919.
	406	*/
	407	#if defined(CONFIG_MPC8540) \|\| defined(CONFIG_MPC8541) \|\| \
	408	defined(CONFIG_MPC8560) \|\| defined(CONFIG_MPC8555)
943afa22	409	gd->i2c1_clk = sys_info.freqSystemBus;
88353a98 TT	410	#elif defined(CONFIG_MPC8544)
	411	/*
	412	* On the 8544, the I2C clock is the same as the SEC clock. This can be
	413	* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
	414	* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
	415	* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
	416	* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
	417	*/
	418	if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
dffd2446	419	gd->i2c1_clk = sys_info.freqSystemBus / 3;
42653b82 KG	420	else
42653b82 KG	421	gd->i2c1_clk = sys_info.freqSystemBus / 2;
88353a98 TT	422	#else
	423	/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
	424	gd->i2c1_clk = sys_info.freqSystemBus / 2;
	425	#endif
	426	gd->i2c2_clk = gd->i2c1_clk;
943afa22	427
6b9ea08c	428	#if defined(CONFIG_FSL_ESDHC)
7d640e9b PJ	429	#if defined(CONFIG_MPC8569) \|\| defined(CONFIG_P1010) \|\|\
7d640e9b PJ	430	defined(CONFIG_P1014)
7f52ed5e AV	431	gd->sdhc_clk = gd->bus_clk;
7f52ed5e AV	432	#else
ef50d6c0 KG	433	gd->sdhc_clk = gd->bus_clk / 2;
ef50d6c0 KG	434	#endif
7f52ed5e	435	#endif /* defined(CONFIG_FSL_ESDHC) */
ef50d6c0	436
9c4c5ae3	437	#if defined(CONFIG_CPM2)
42d1f039 WD	438	gd->vco_out = 2*sys_info.freqSystemBus;
	439	gd->cpm_clk = gd->vco_out / 2;
	440	gd->scc_clk = gd->vco_out / 4;
1206c184	441	gd->arch.brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
42d1f039 WD	442	#endif
	443
	444	if(gd->cpu_clk != 0) return (0);
	445	else return (1);
	446	}
	447
	448
	449	/********************************************
	450	* get_bus_freq
	451	* return system bus freq in Hz
	452	*********************************************/
	453	ulong get_bus_freq (ulong dummy)
	454	{
a3e77fa5	455	return gd->bus_clk;
42d1f039	456	}
d4357932 KG	457
	458	/********************************************
	459	* get_ddr_freq
	460	* return ddr bus freq in Hz
	461	*********************************************/
	462	ulong get_ddr_freq (ulong dummy)
	463	{
a3e77fa5	464	return gd->mem_clk;
d4357932	465	}