[people/ms/u-boot.git] / arch / powerpc / cpu / mpc85xx / tlb.c

/*
 * Copyright 2008-2011 Freescale Semiconductor, Inc.
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#ifdef CONFIG_ADDR_MAP
#include <addr_map.h>
#endif

DECLARE_GLOBAL_DATA_PTR;

void invalidate_tlb(u8 tlb)
{
	if (tlb == 0)
		mtspr(MMUCSR0, 0x4);
	if (tlb == 1)
		mtspr(MMUCSR0, 0x2);
}

void init_tlbs(void)
{
	int i;

	for (i = 0; i < num_tlb_entries; i++) {
		write_tlb(tlb_table[i].mas0,
			  tlb_table[i].mas1,
			  tlb_table[i].mas2,
			  tlb_table[i].mas3,
			  tlb_table[i].mas7);
	}

	return ;
}

#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
		       phys_addr_t *rpn)
{
	u32 _mas1;

	mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
	asm volatile("tlbre;isync");
	_mas1 = mfspr(MAS1);

	*valid = (_mas1 & MAS1_VALID);
	*tsize = (_mas1 >> 7) & 0x1f;
	*epn = mfspr(MAS2) & MAS2_EPN;
	*rpn = mfspr(MAS3) & MAS3_RPN;
#ifdef CONFIG_ENABLE_36BIT_PHYS
	*rpn |= ((u64)mfspr(MAS7)) << 32;
#endif
}

void print_tlbcam(void)
{
	int i;
	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;

	/* walk all the entries */
	printf("TLBCAM entries\n");
	for (i = 0; i < num_cam; i++) {
		unsigned long epn;
		u32 tsize, valid;
		phys_addr_t rpn;

		read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
		printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
			i, (valid == 0) ? 0 : 1, (unsigned int)epn,
			(unsigned long long)rpn);
		print_size(TSIZE_TO_BYTES(tsize), "\n");
	}
}

static inline void use_tlb_cam(u8 idx)
{
	int i = idx / 32;
	int bit = idx % 32;

	gd->arch.used_tlb_cams[i] |= (1 << bit);
}

static inline void free_tlb_cam(u8 idx)
{
	int i = idx / 32;
	int bit = idx % 32;

	gd->arch.used_tlb_cams[i] &= ~(1 << bit);
}

void init_used_tlb_cams(void)
{
	int i;
	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;

	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
		gd->arch.used_tlb_cams[i] = 0;

	/* walk all the entries */
	for (i = 0; i < num_cam; i++) {
		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
		asm volatile("tlbre;isync");
		if (mfspr(MAS1) & MAS1_VALID)
			use_tlb_cam(i);
	}
}

int find_free_tlbcam(void)
{
	int i;
	u32 idx;

	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
		idx = ffz(gd->arch.used_tlb_cams[i]);

		if (idx != 32)
			break;
	}

	idx += i * 32;

	if (idx >= CONFIG_SYS_NUM_TLBCAMS)
		return -1;

	return idx;
}

void set_tlb(u8 tlb, u32 epn, u64 rpn,
	     u8 perms, u8 wimge,
	     u8 ts, u8 esel, u8 tsize, u8 iprot)
{
	u32 _mas0, _mas1, _mas2, _mas3, _mas7;

	if (tlb == 1)
		use_tlb_cam(esel);

	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
	    tsize & 1) {
		printf("%s: bad tsize %d on entry %d at 0x%08x\n",
			__func__, tsize, tlb, epn);
		return;
	}

	_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
	_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
	_mas2 = FSL_BOOKE_MAS2(epn, wimge);
	_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
	_mas7 = FSL_BOOKE_MAS7(rpn);

	write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);

#ifdef CONFIG_ADDR_MAP
	if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
		addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
#endif
}

void disable_tlb(u8 esel)
{
	u32 _mas0, _mas1, _mas2, _mas3;

	free_tlb_cam(esel);

	_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
	_mas1 = 0;
	_mas2 = 0;
	_mas3 = 0;

	mtspr(MAS0, _mas0);
	mtspr(MAS1, _mas1);
	mtspr(MAS2, _mas2);
	mtspr(MAS3, _mas3);
#ifdef CONFIG_ENABLE_36BIT_PHYS
	mtspr(MAS7, 0);
#endif
	asm volatile("isync;msync;tlbwe;isync");

#ifdef CONFIG_ADDR_MAP
	if (gd->flags & GD_FLG_RELOC)
		addrmap_set_entry(0, 0, 0, esel);
#endif
}

static void tlbsx (const volatile unsigned *addr)
{
	__asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
}

/* return -1 if we didn't find anything */
int find_tlb_idx(void *addr, u8 tlbsel)
{
	u32 _mas0, _mas1;

	/* zero out Search PID, AS */
	mtspr(MAS6, 0);

	tlbsx(addr);

	_mas0 = mfspr(MAS0);
	_mas1 = mfspr(MAS1);

	/* we found something, and its in the TLB we expect */
	if ((MAS1_VALID & _mas1) &&
		(MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
		return ((_mas0 & MAS0_ESEL_MSK) >> 16);
	}

	return -1;
}

#ifdef CONFIG_ADDR_MAP
void init_addr_map(void)
{
	int i;
	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;

	/* walk all the entries */
	for (i = 0; i < num_cam; i++) {
		unsigned long epn;
		u32 tsize, valid;
		phys_addr_t rpn;

		read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
		if (valid & MAS1_VALID)
			addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
	}

	return ;
}
#endif

unsigned int
setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
	int i;
	unsigned int tlb_size;
	unsigned int wimge = MAS2_M;
	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
	unsigned int max_cam, tsize_mask;
	u64 size, memsize = (u64)memsize_in_meg << 20;

#ifdef CONFIG_SYS_PPC_DDR_WIMGE
	wimge = CONFIG_SYS_PPC_DDR_WIMGE;
#endif
	size = min(memsize, CONFIG_MAX_MEM_MAPPED);
	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
		/* Convert (4^max) kB to (2^max) bytes */
		max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
		tsize_mask = ~1U;
	} else {
		/* Convert (2^max) kB to (2^max) bytes */
		max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
		tsize_mask = ~0U;
	}

	for (i = 0; size && i < 8; i++) {
		int ram_tlb_index = find_free_tlbcam();
		u32 camsize = __ilog2_u64(size) & tsize_mask;
		u32 align = __ilog2(ram_tlb_address) & tsize_mask;

		if (ram_tlb_index == -1)
			break;

		if (align == -2) align = max_cam;
		if (camsize > align)
			camsize = align;

		if (camsize > max_cam)
			camsize = max_cam;

		tlb_size = camsize - 10;

		set_tlb(1, ram_tlb_address, p_addr,
			MAS3_SX|MAS3_SW|MAS3_SR, wimge,
			0, ram_tlb_index, tlb_size, 1);

		size -= 1ULL << camsize;
		memsize -= 1ULL << camsize;
		ram_tlb_address += 1UL << camsize;
		p_addr += 1UL << camsize;
	}

	if (memsize)
		print_size(memsize, " left unmapped\n");
	return memsize_in_meg;
}

unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
	return
		setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}

/* Invalidate the DDR TLBs for the requested size */
void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
{
	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
	unsigned long epn;
	u32 tsize, valid, ptr;
	phys_addr_t rpn = 0;
	int ddr_esel;
	u64 memsize = (u64)memsize_in_meg << 20;

	ptr = vstart;

	while (ptr < (vstart + memsize)) {
		ddr_esel = find_tlb_idx((void *)ptr, 1);
		if (ddr_esel != -1) {
			read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
			disable_tlb(ddr_esel);
		}
		ptr += TSIZE_TO_BYTES(tsize);
	}
}

void clear_ddr_tlbs(unsigned int memsize_in_meg)
{
	clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
}


#endif /* not SPL */
Commit	Line	Data
44a23cfd	1	/*
ebc73943	2	* Copyright 2008-2011 Freescale Semiconductor, Inc.
44a23cfd KG	3	*
	4	* (C) Copyright 2000
	5	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
44a23cfd KG	8	*/
	9
	10	#include <common.h>
	11	#include <asm/processor.h>
	12	#include <asm/mmu.h>
ecf5b98c KG	13	#ifdef CONFIG_ADDR_MAP
	14	#include <addr_map.h>
	15	#endif
	16
	17	DECLARE_GLOBAL_DATA_PTR;
44a23cfd	18
b2eec281 KG	19	void invalidate_tlb(u8 tlb)
	20	{
	21	if (tlb == 0)
	22	mtspr(MMUCSR0, 0x4);
	23	if (tlb == 1)
	24	mtspr(MMUCSR0, 0x2);
	25	}
	26
	27	void init_tlbs(void)
	28	{
	29	int i;
	30
	31	for (i = 0; i < num_tlb_entries; i++) {
	32	write_tlb(tlb_table[i].mas0,
	33	tlb_table[i].mas1,
	34	tlb_table[i].mas2,
	35	tlb_table[i].mas3,
	36	tlb_table[i].mas7);
	37	}
	38
	39	return ;
	40	}
	41
c97cd1ba	42	#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
4e63df30 BB	43	void read_tlbcam_entry(int idx, u32 valid, u32 tsize, unsigned long *epn,
	44	phys_addr_t *rpn)
	45	{
	46	u32 _mas1;
	47
	48	mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
	49	asm volatile("tlbre;isync");
	50	_mas1 = mfspr(MAS1);
	51
	52	*valid = (_mas1 & MAS1_VALID);
31d084dd	53	*tsize = (_mas1 >> 7) & 0x1f;
4e63df30 BB	54	*epn = mfspr(MAS2) & MAS2_EPN;
	55	*rpn = mfspr(MAS3) & MAS3_RPN;
	56	#ifdef CONFIG_ENABLE_36BIT_PHYS
	57	*rpn \|= ((u64)mfspr(MAS7)) << 32;
	58	#endif
	59	}
	60
70e02bca BB	61	void print_tlbcam(void)
	62	{
	63	int i;
	64	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
	65
	66	/* walk all the entries */
	67	printf("TLBCAM entries\n");
	68	for (i = 0; i < num_cam; i++) {
	69	unsigned long epn;
	70	u32 tsize, valid;
	71	phys_addr_t rpn;
	72
	73	read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
	74	printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
	75	i, (valid == 0) ? 0 : 1, (unsigned int)epn,
	76	(unsigned long long)rpn);
	77	print_size(TSIZE_TO_BYTES(tsize), "\n");
	78	}
	79	}
	80
94e9411b KG	81	static inline void use_tlb_cam(u8 idx)
	82	{
	83	int i = idx / 32;
	84	int bit = idx % 32;
	85
7c80c6c5	86	gd->arch.used_tlb_cams[i] \|= (1 << bit);
94e9411b KG	87	}
	88
	89	static inline void free_tlb_cam(u8 idx)
	90	{
	91	int i = idx / 32;
	92	int bit = idx % 32;
	93
7c80c6c5	94	gd->arch.used_tlb_cams[i] &= ~(1 << bit);
94e9411b KG	95	}
	96
	97	void init_used_tlb_cams(void)
	98	{
	99	int i;
	100	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
	101
	102	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
7c80c6c5	103	gd->arch.used_tlb_cams[i] = 0;
94e9411b KG	104
	105	/* walk all the entries */
	106	for (i = 0; i < num_cam; i++) {
94e9411b	107	mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
94e9411b	108	asm volatile("tlbre;isync");
4e63df30	109	if (mfspr(MAS1) & MAS1_VALID)
94e9411b KG	110	use_tlb_cam(i);
	111	}
	112	}
	113
	114	int find_free_tlbcam(void)
	115	{
	116	int i;
	117	u32 idx;
	118
	119	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
7c80c6c5	120	idx = ffz(gd->arch.used_tlb_cams[i]);
94e9411b KG	121
	122	if (idx != 32)
	123	break;
	124	}
	125
	126	idx += i * 32;
	127
	128	if (idx >= CONFIG_SYS_NUM_TLBCAMS)
	129	return -1;
	130
	131	return idx;
	132	}
	133
44a23cfd KG	134	void set_tlb(u8 tlb, u32 epn, u64 rpn,
	135	u8 perms, u8 wimge,
	136	u8 ts, u8 esel, u8 tsize, u8 iprot)
	137	{
	138	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
	139
94e9411b KG	140	if (tlb == 1)
	141	use_tlb_cam(esel);
	142
31d084dd SW	143	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
	144	tsize & 1) {
	145	printf("%s: bad tsize %d on entry %d at 0x%08x\n",
	146	__func__, tsize, tlb, epn);
	147	return;
	148	}
	149
44a23cfd KG	150	_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
	151	_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
	152	_mas2 = FSL_BOOKE_MAS2(epn, wimge);
	153	_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
d30f9043	154	_mas7 = FSL_BOOKE_MAS7(rpn);
44a23cfd	155
d30f9043	156	write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
ecf5b98c KG	157
	158	#ifdef CONFIG_ADDR_MAP
	159	if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
4e63df30	160	addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
ecf5b98c	161	#endif
44a23cfd KG	162	}
	163
	164	void disable_tlb(u8 esel)
	165	{
3d6d9c31	166	u32 _mas0, _mas1, _mas2, _mas3;
44a23cfd	167
94e9411b KG	168	free_tlb_cam(esel);
94e9411b KG	169
44a23cfd KG	170	_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
	171	_mas1 = 0;
	172	_mas2 = 0;
	173	_mas3 = 0;
44a23cfd KG	174
	175	mtspr(MAS0, _mas0);
	176	mtspr(MAS1, _mas1);
	177	mtspr(MAS2, _mas2);
	178	mtspr(MAS3, _mas3);
	179	#ifdef CONFIG_ENABLE_36BIT_PHYS
3d6d9c31	180	mtspr(MAS7, 0);
44a23cfd KG	181	#endif
44a23cfd KG	182	asm volatile("isync;msync;tlbwe;isync");
ecf5b98c KG	183
	184	#ifdef CONFIG_ADDR_MAP
	185	if (gd->flags & GD_FLG_RELOC)
	186	addrmap_set_entry(0, 0, 0, esel);
	187	#endif
44a23cfd KG	188	}
44a23cfd KG	189
c2287af1 KG	190	static void tlbsx (const volatile unsigned *addr)
	191	{
	192	__asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
	193	}
	194
	195	/* return -1 if we didn't find anything */
	196	int find_tlb_idx(void *addr, u8 tlbsel)
	197	{
	198	u32 _mas0, _mas1;
	199
	200	/* zero out Search PID, AS */
	201	mtspr(MAS6, 0);
	202
	203	tlbsx(addr);
	204
	205	_mas0 = mfspr(MAS0);
	206	_mas1 = mfspr(MAS1);
	207
	208	/* we found something, and its in the TLB we expect */
	209	if ((MAS1_VALID & _mas1) &&
	210	(MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
	211	return ((_mas0 & MAS0_ESEL_MSK) >> 16);
	212	}
	213
	214	return -1;
	215	}
	216
ecf5b98c KG	217	#ifdef CONFIG_ADDR_MAP
	218	void init_addr_map(void)
	219	{
	220	int i;
cdbdbe65	221	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
ecf5b98c	222
e393e2e9	223	/* walk all the entries */
cdbdbe65	224	for (i = 0; i < num_cam; i++) {
e393e2e9	225	unsigned long epn;
4e63df30	226	u32 tsize, valid;
e393e2e9 KG	227	phys_addr_t rpn;
e393e2e9 KG	228
4e63df30 BB	229	read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
	230	if (valid & MAS1_VALID)
	231	addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
ecf5b98c KG	232	}
	233
	234	return ;
	235	}
	236	#endif
	237
c02ce6e5 YS	238	unsigned int
c02ce6e5 YS	239	setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
6fb1b734	240	{
355f4f85	241	int i;
6fb1b734	242	unsigned int tlb_size;
ffd06e02	243	unsigned int wimge = MAS2_M;
f8523cb0	244	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
31d084dd	245	unsigned int max_cam, tsize_mask;
f8523cb0	246	u64 size, memsize = (u64)memsize_in_meg << 20;
6fb1b734	247
6b1ef2a6 BB	248	#ifdef CONFIG_SYS_PPC_DDR_WIMGE
	249	wimge = CONFIG_SYS_PPC_DDR_WIMGE;
	250	#endif
f8523cb0	251	size = min(memsize, CONFIG_MAX_MEM_MAPPED);
50cf3d17 KG	252	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
	253	/* Convert (4^max) kB to (2^max) bytes */
	254	max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
31d084dd	255	tsize_mask = ~1U;
50cf3d17 KG	256	} else {
	257	/* Convert (2^max) kB to (2^max) bytes */
	258	max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
31d084dd	259	tsize_mask = ~0U;
50cf3d17	260	}
f8523cb0	261
355f4f85 KG	262	for (i = 0; size && i < 8; i++) {
355f4f85 KG	263	int ram_tlb_index = find_free_tlbcam();
31d084dd SW	264	u32 camsize = __ilog2_u64(size) & tsize_mask;
31d084dd SW	265	u32 align = __ilog2(ram_tlb_address) & tsize_mask;
f8523cb0	266
355f4f85 KG	267	if (ram_tlb_index == -1)
	268	break;
	269
f8523cb0 KG	270	if (align == -2) align = max_cam;
	271	if (camsize > align)
	272	camsize = align;
	273
	274	if (camsize > max_cam)
	275	camsize = max_cam;
	276
31d084dd	277	tlb_size = camsize - 10;
6fb1b734	278
c02ce6e5	279	set_tlb(1, ram_tlb_address, p_addr,
6b1ef2a6	280	MAS3_SX\|MAS3_SW\|MAS3_SR, wimge,
6fb1b734 KG	281	0, ram_tlb_index, tlb_size, 1);
6fb1b734 KG	282
f8523cb0 KG	283	size -= 1ULL << camsize;
	284	memsize -= 1ULL << camsize;
	285	ram_tlb_address += 1UL << camsize;
c02ce6e5	286	p_addr += 1UL << camsize;
6fb1b734 KG	287	}
6fb1b734 KG	288
f8523cb0	289	if (memsize)
d4b130dc	290	print_size(memsize, " left unmapped\n");
6fb1b734 KG	291	return memsize_in_meg;
6fb1b734 KG	292	}
c02ce6e5 YS	293
	294	unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
	295	{
	296	return
	297	setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
	298	}
9cdfe281 BB	299
	300	/* Invalidate the DDR TLBs for the requested size */
	301	void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
	302	{
	303	u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
	304	unsigned long epn;
	305	u32 tsize, valid, ptr;
	306	phys_addr_t rpn = 0;
	307	int ddr_esel;
	308	u64 memsize = (u64)memsize_in_meg << 20;
	309
	310	ptr = vstart;
	311
	312	while (ptr < (vstart + memsize)) {
	313	ddr_esel = find_tlb_idx((void *)ptr, 1);
	314	if (ddr_esel != -1) {
	315	read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
	316	disable_tlb(ddr_esel);
	317	}
	318	ptr += TSIZE_TO_BYTES(tsize);
	319	}
	320	}
	321
	322	void clear_ddr_tlbs(unsigned int memsize_in_meg)
	323	{
	324	clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
	325	}
	326
	327
c97cd1ba	328	#endif /* not SPL */