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Commit | Line | Data |
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feb7838f | 1 | /* |
7a577fda | 2 | * Copyright 2007-2009, 2011 Freescale Semiconductor, Inc. |
feb7838f | 3 | * |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
feb7838f SS |
5 | */ |
6 | ||
7a577fda KG |
7 | #include "config.h" /* CONFIG_BOARDDIR */ |
8 | ||
9 | #ifdef CONFIG_RESET_VECTOR_ADDRESS | |
10 | #define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS | |
11 | #else | |
6c97a20d KG |
12 | #define RESET_VECTOR_ADDRESS 0xfffffffc |
13 | #endif | |
14 | ||
feb7838f | 15 | OUTPUT_ARCH(powerpc) |
fbe53f59 | 16 | |
feb7838f SS |
17 | PHDRS |
18 | { | |
19 | text PT_LOAD; | |
20 | bss PT_LOAD; | |
21 | } | |
22 | ||
23 | SECTIONS | |
24 | { | |
25 | /* Read-only sections, merged into text segment: */ | |
26 | . = + SIZEOF_HEADERS; | |
27 | .interp : { *(.interp) } | |
feb7838f SS |
28 | .text : |
29 | { | |
fbe53f59 | 30 | *(.text*) |
feb7838f SS |
31 | } :text |
32 | _etext = .; | |
33 | PROVIDE (etext = .); | |
34 | .rodata : | |
35 | { | |
feb7838f SS |
36 | *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) |
37 | } :text | |
feb7838f SS |
38 | |
39 | /* Read-write section, merged into data segment: */ | |
40 | . = (. + 0x00FF) & 0xFFFFFF00; | |
41 | _erotext = .; | |
42 | PROVIDE (erotext = .); | |
43 | .reloc : | |
44 | { | |
feb7838f | 45 | _GOT2_TABLE_ = .; |
fbe53f59 | 46 | KEEP(*(.got2)) |
337f5f50 JT |
47 | KEEP(*(.got)) |
48 | PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); | |
feb7838f | 49 | _FIXUP_TABLE_ = .; |
fbe53f59 | 50 | KEEP(*(.fixup)) |
feb7838f | 51 | } |
337f5f50 | 52 | __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; |
feb7838f SS |
53 | __fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
54 | ||
55 | .data : | |
56 | { | |
fbe53f59 PT |
57 | *(.data*) |
58 | *(.sdata*) | |
feb7838f SS |
59 | } |
60 | _edata = .; | |
61 | PROVIDE (edata = .); | |
62 | ||
63 | . = .; | |
feb7838f | 64 | |
55675142 MV |
65 | . = ALIGN(4); |
66 | .u_boot_list : { | |
ef123c52 | 67 | KEEP(*(SORT(.u_boot_list*))); |
55675142 MV |
68 | } |
69 | ||
feb7838f SS |
70 | . = .; |
71 | __start___ex_table = .; | |
72 | __ex_table : { *(__ex_table) } | |
73 | __stop___ex_table = .; | |
74 | ||
75 | . = ALIGN(256); | |
76 | __init_begin = .; | |
77 | .text.init : { *(.text.init) } | |
78 | .data.init : { *(.data.init) } | |
79 | . = ALIGN(256); | |
80 | __init_end = .; | |
81 | ||
5df572f0 YZ |
82 | #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC |
83 | .bootpg ADDR(.text) - 0x1000 : | |
84 | { | |
85 | KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg)) | |
86 | } :text = 0xffff | |
87 | . = ADDR(.text) + 0x80000; | |
88 | #else | |
6c97a20d | 89 | .bootpg RESET_VECTOR_ADDRESS - 0xffc : |
feb7838f | 90 | { |
a47a12be | 91 | arch/powerpc/cpu/mpc85xx/start.o (.bootpg) |
feb7838f SS |
92 | } :text = 0xffff |
93 | ||
6c97a20d | 94 | .resetvec RESET_VECTOR_ADDRESS : |
feb7838f | 95 | { |
fbe53f59 | 96 | KEEP(*(.resetvec)) |
feb7838f SS |
97 | } :text = 0xffff |
98 | ||
6c97a20d | 99 | . = RESET_VECTOR_ADDRESS + 0x4; |
feb7838f | 100 | |
3beb40c2 PT |
101 | /* |
102 | * Make sure that the bss segment isn't linked at 0x0, otherwise its | |
103 | * address won't be updated during relocation fixups. Note that | |
104 | * this is a temporary fix. Code to dynamically the fixup the bss | |
105 | * location will be added in the future. When the bss relocation | |
106 | * fixup code is present this workaround should be removed. | |
107 | */ | |
108 | #if (RESET_VECTOR_ADDRESS == 0xfffffffc) | |
109 | . |= 0x10; | |
5df572f0 | 110 | #endif |
3beb40c2 PT |
111 | #endif |
112 | ||
feb7838f SS |
113 | __bss_start = .; |
114 | .bss (NOLOAD) : | |
115 | { | |
fbe53f59 PT |
116 | *(.sbss*) |
117 | *(.bss*) | |
feb7838f SS |
118 | *(COMMON) |
119 | } :bss | |
120 | ||
121 | . = ALIGN(4); | |
3929fb0a | 122 | __bss_end = . ; |
feb7838f SS |
123 | PROVIDE (end = .); |
124 | } |