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Commit | Line | Data |
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debb7354 | 1 | /* |
9ff32d8c | 2 | * Copyright 2006,2009-2010 Freescale Semiconductor, Inc. |
cb5965fb | 3 | * Jeff Brown |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
debb7354 JL |
7 | */ |
8 | ||
9 | #include <common.h> | |
10 | #include <watchdog.h> | |
11 | #include <command.h> | |
12 | #include <asm/cache.h> | |
e34a0e91 | 13 | #include <asm/mmu.h> |
debb7354 | 14 | #include <mpc86xx.h> |
4f93f8b1 | 15 | #include <asm/fsl_law.h> |
debb7354 | 16 | |
0e870980 PA |
17 | DECLARE_GLOBAL_DATA_PTR; |
18 | ||
4ef630df PT |
19 | /* |
20 | * Default board reset function | |
21 | */ | |
22 | static void | |
23 | __board_reset(void) | |
24 | { | |
25 | /* Do nothing */ | |
26 | } | |
f9a109b3 | 27 | void board_reset(void) __attribute__((weak, alias("__board_reset"))); |
4ef630df PT |
28 | |
29 | ||
ffff3ae5 JL |
30 | int |
31 | checkcpu(void) | |
debb7354 JL |
32 | { |
33 | sys_info_t sysinfo; | |
34 | uint pvr, svr; | |
debb7354 | 35 | uint major, minor; |
a1c8a719 | 36 | char buf1[32], buf2[32]; |
6d0f6bcf | 37 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
9553df86 | 38 | volatile ccsr_gur_t *gur = &immap->im_gur; |
480f6179 | 39 | struct cpu_type *cpu; |
a1c8a719 | 40 | uint msscr0 = mfspr(MSSCR0); |
debb7354 JL |
41 | |
42 | svr = get_svr(); | |
debb7354 JL |
43 | major = SVR_MAJ(svr); |
44 | minor = SVR_MIN(svr); | |
45 | ||
21170c80 PA |
46 | if (cpu_numcores() > 1) { |
47 | #ifndef CONFIG_MP | |
48 | puts("Unicore software on multiprocessor system!!\n" | |
49 | "To enable mutlticore build define CONFIG_MP\n"); | |
50 | #endif | |
51 | } | |
a1c8a719 PT |
52 | puts("CPU: "); |
53 | ||
67ac13b1 | 54 | cpu = gd->arch.cpu; |
0e870980 | 55 | |
58442dc0 | 56 | puts(cpu->name); |
480f6179 | 57 | |
debb7354 | 58 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
a1c8a719 PT |
59 | puts("Core: "); |
60 | ||
61 | pvr = get_pvr(); | |
a1c8a719 PT |
62 | major = PVR_E600_MAJ(pvr); |
63 | minor = PVR_E600_MIN(pvr); | |
64 | ||
6770c5e2 | 65 | printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0); |
a1c8a719 PT |
66 | if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) |
67 | puts("\n Core1Translation Enabled"); | |
68 | debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); | |
69 | ||
70 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); | |
debb7354 JL |
71 | |
72 | get_sys_info(&sysinfo); | |
73 | ||
a1c8a719 PT |
74 | puts("Clock Configuration:\n"); |
75 | printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); | |
76 | printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); | |
77 | printf(" DDR:%-4s MHz (%s MT/s data rate), ", | |
78 | strmhz(buf1, sysinfo.freqSystemBus / 2), | |
79 | strmhz(buf2, sysinfo.freqSystemBus)); | |
5c9efb36 | 80 | |
ada591d2 | 81 | if (sysinfo.freqLocalBus > LCRR_CLKDIV) { |
a1c8a719 | 82 | printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); |
debb7354 | 83 | } else { |
a9f3acbc | 84 | printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", |
ada591d2 | 85 | sysinfo.freqLocalBus); |
debb7354 JL |
86 | } |
87 | ||
a1c8a719 PT |
88 | puts("L1: D-cache 32 KB enabled\n"); |
89 | puts(" I-cache 32 KB enabled\n"); | |
90 | ||
91 | puts("L2: "); | |
92 | if (get_l2cr() & 0x80000000) { | |
93 | #if defined(CONFIG_MPC8610) | |
94 | puts("256"); | |
95 | #elif defined(CONFIG_MPC8641) | |
96 | puts("512"); | |
97 | #endif | |
98 | puts(" KB enabled\n"); | |
99 | } else { | |
cb5965fb | 100 | puts("Disabled\n"); |
a1c8a719 | 101 | } |
5c9efb36 JL |
102 | |
103 | return 0; | |
debb7354 JL |
104 | } |
105 | ||
106 | ||
c22a711d | 107 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
debb7354 | 108 | { |
4ef630df PT |
109 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
110 | volatile ccsr_gur_t *gur = &immap->im_gur; | |
5c9efb36 | 111 | |
4ef630df PT |
112 | /* Attempt board-specific reset */ |
113 | board_reset(); | |
5c9efb36 | 114 | |
4ef630df PT |
115 | /* Next try asserting HRESET_REQ */ |
116 | out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ); | |
5c9efb36 | 117 | |
4ef630df PT |
118 | while (1) |
119 | ; | |
c22a711d PT |
120 | |
121 | return 1; | |
debb7354 JL |
122 | } |
123 | ||
124 | ||
debb7354 JL |
125 | /* |
126 | * Get timebase clock frequency | |
127 | */ | |
ffff3ae5 JL |
128 | unsigned long |
129 | get_tbclk(void) | |
debb7354 | 130 | { |
ffff3ae5 | 131 | sys_info_t sys_info; |
debb7354 JL |
132 | |
133 | get_sys_info(&sys_info); | |
5c9efb36 | 134 | return (sys_info.freqSystemBus + 3L) / 4L; |
debb7354 JL |
135 | } |
136 | ||
debb7354 JL |
137 | |
138 | #if defined(CONFIG_WATCHDOG) | |
139 | void | |
140 | watchdog_reset(void) | |
141 | { | |
3473ab73 JJ |
142 | #if defined(CONFIG_MPC8610) |
143 | /* | |
144 | * This actually feed the hard enabled watchdog. | |
145 | */ | |
6d0f6bcf | 146 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
3473ab73 JJ |
147 | volatile ccsr_wdt_t *wdt = &immap->im_wdt; |
148 | volatile ccsr_gur_t *gur = &immap->im_gur; | |
149 | u32 tmp = gur->pordevsr; | |
150 | ||
151 | if (tmp & 0x4000) { | |
152 | wdt->swsrr = 0x556c; | |
153 | wdt->swsrr = 0xaa39; | |
154 | } | |
155 | #endif | |
debb7354 JL |
156 | } |
157 | #endif /* CONFIG_WATCHDOG */ | |
158 | ||
4f93f8b1 BB |
159 | /* |
160 | * Print out the state of various machine registers. | |
e34a0e91 | 161 | * Currently prints out LAWs, BR0/OR0, and BATs |
4f93f8b1 BB |
162 | */ |
163 | void mpc86xx_reginfo(void) | |
164 | { | |
e34a0e91 | 165 | print_bats(); |
4f93f8b1 | 166 | print_laws(); |
f51cdaf1 | 167 | print_lbc_regs(); |
debb7354 | 168 | } |
9ff32d8c TT |
169 | |
170 | /* | |
171 | * Set the DDR BATs to reflect the actual size of DDR. | |
172 | * | |
173 | * dram_size is the actual size of DDR, in bytes | |
174 | * | |
175 | * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only | |
176 | * are using a single BAT to cover DDR. | |
177 | * | |
178 | * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN | |
179 | * is not defined) then we might have a situation where U-Boot will attempt | |
180 | * to relocated itself outside of the region mapped by DBAT0. | |
181 | * This will cause a machine check. | |
182 | * | |
183 | * Currently we are limited to power of two sized DDR since we only use a | |
184 | * single bat. If a non-power of two size is used that is less than | |
185 | * CONFIG_MAX_MEM_MAPPED u-boot will crash. | |
186 | * | |
187 | */ | |
188 | void setup_ddr_bat(phys_addr_t dram_size) | |
189 | { | |
190 | unsigned long batu, bl; | |
191 | ||
192 | bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED)); | |
193 | ||
194 | if (BATU_SIZE(bl) != dram_size) { | |
195 | u64 sz = (u64)dram_size - BATU_SIZE(bl); | |
196 | print_size(sz, " left unmapped\n"); | |
197 | } | |
198 | ||
199 | batu = bl | BATU_VS | BATU_VP; | |
200 | write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L); | |
201 | write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L); | |
202 | } |