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debb7354 | 1 | /* |
0e870980 | 2 | * Copyright 2004,2009 Freescale Semiconductor, Inc. |
c934f655 | 3 | * Jeff Brown |
debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | /* | |
26 | * cpu_init.c - low level cpu init | |
27 | */ | |
28 | ||
2d0daa03 | 29 | #include <config.h> |
debb7354 JL |
30 | #include <common.h> |
31 | #include <mpc86xx.h> | |
2d0daa03 | 32 | #include <asm/mmu.h> |
83d1b387 | 33 | #include <asm/fsl_law.h> |
7649a590 | 34 | #include <asm/mp.h> |
debb7354 | 35 | |
24bfb48c BB |
36 | void setup_bats(void); |
37 | ||
1218abf1 WD |
38 | DECLARE_GLOBAL_DATA_PTR; |
39 | ||
debb7354 JL |
40 | /* |
41 | * Breathe some life into the CPU... | |
42 | * | |
43 | * Set up the memory map | |
44 | * initialize a bunch of registers | |
45 | */ | |
46 | ||
5c9efb36 | 47 | void cpu_init_f(void) |
debb7354 | 48 | { |
6d0f6bcf | 49 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
debb7354 | 50 | volatile ccsr_lbc_t *memctl = &immap->im_lbc; |
5c9efb36 | 51 | |
ffff3ae5 | 52 | /* Pointer is writable since we allocated a register for it */ |
6d0f6bcf | 53 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
debb7354 JL |
54 | |
55 | /* Clear initial global data */ | |
56 | memset ((void *) gd, 0, sizeof (gd_t)); | |
57 | ||
4933b91f BB |
58 | #ifdef CONFIG_FSL_LAW |
59 | init_laws(); | |
60 | #endif | |
61 | ||
24bfb48c BB |
62 | setup_bats(); |
63 | ||
debb7354 JL |
64 | /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary |
65 | * addresses - these have to be modified later when FLASH size | |
66 | * has been determined | |
67 | */ | |
68 | ||
6d0f6bcf JCPV |
69 | #if defined(CONFIG_SYS_OR0_REMAP) |
70 | memctl->or0 = CONFIG_SYS_OR0_REMAP; | |
debb7354 | 71 | #endif |
6d0f6bcf JCPV |
72 | #if defined(CONFIG_SYS_OR1_REMAP) |
73 | memctl->or1 = CONFIG_SYS_OR1_REMAP; | |
debb7354 JL |
74 | #endif |
75 | ||
76 | /* now restrict to preliminary range */ | |
6d0f6bcf JCPV |
77 | #if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM) |
78 | memctl->br0 = CONFIG_SYS_BR0_PRELIM; | |
79 | memctl->or0 = CONFIG_SYS_OR0_PRELIM; | |
debb7354 JL |
80 | #endif |
81 | ||
6d0f6bcf JCPV |
82 | #if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM) |
83 | memctl->or1 = CONFIG_SYS_OR1_PRELIM; | |
84 | memctl->br1 = CONFIG_SYS_BR1_PRELIM; | |
debb7354 JL |
85 | #endif |
86 | ||
6d0f6bcf JCPV |
87 | #if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM) |
88 | memctl->or2 = CONFIG_SYS_OR2_PRELIM; | |
89 | memctl->br2 = CONFIG_SYS_BR2_PRELIM; | |
debb7354 | 90 | #endif |
5c9efb36 | 91 | |
6d0f6bcf JCPV |
92 | #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) |
93 | memctl->or3 = CONFIG_SYS_OR3_PRELIM; | |
94 | memctl->br3 = CONFIG_SYS_BR3_PRELIM; | |
debb7354 | 95 | #endif |
5c9efb36 | 96 | |
6d0f6bcf JCPV |
97 | #if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM) |
98 | memctl->or4 = CONFIG_SYS_OR4_PRELIM; | |
99 | memctl->br4 = CONFIG_SYS_BR4_PRELIM; | |
debb7354 | 100 | #endif |
5c9efb36 | 101 | |
6d0f6bcf JCPV |
102 | #if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM) |
103 | memctl->or5 = CONFIG_SYS_OR5_PRELIM; | |
104 | memctl->br5 = CONFIG_SYS_BR5_PRELIM; | |
debb7354 JL |
105 | #endif |
106 | ||
6d0f6bcf JCPV |
107 | #if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM) |
108 | memctl->or6 = CONFIG_SYS_OR6_PRELIM; | |
109 | memctl->br6 = CONFIG_SYS_BR6_PRELIM; | |
debb7354 JL |
110 | #endif |
111 | ||
6d0f6bcf JCPV |
112 | #if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM) |
113 | memctl->or7 = CONFIG_SYS_OR7_PRELIM; | |
114 | memctl->br7 = CONFIG_SYS_BR7_PRELIM; | |
debb7354 | 115 | #endif |
79f4333c PT |
116 | #if defined(CONFIG_FSL_DMA) |
117 | dma_init(); | |
118 | #endif | |
debb7354 JL |
119 | |
120 | /* enable the timebase bit in HID0 */ | |
121 | set_hid0(get_hid0() | 0x4000000); | |
122 | ||
cfc7a7f5 JL |
123 | /* enable EMCP, SYNCBE | ABE bits in HID1 */ |
124 | set_hid1(get_hid1() | 0x80000C00); | |
debb7354 JL |
125 | } |
126 | ||
127 | /* | |
128 | * initialize higher level parts of CPU like timers | |
129 | */ | |
5c9efb36 | 130 | int cpu_init_r(void) |
debb7354 | 131 | { |
0e870980 | 132 | #if defined(CONFIG_MP) |
1266df88 BB |
133 | setup_mp(); |
134 | #endif | |
5c9efb36 | 135 | return 0; |
debb7354 | 136 | } |
2d0daa03 BB |
137 | |
138 | /* Set up BAT registers */ | |
139 | void setup_bats(void) | |
140 | { | |
9ff32d8c | 141 | #if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) |
6d0f6bcf | 142 | write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L); |
9ff32d8c TT |
143 | #endif |
144 | #if defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) | |
6d0f6bcf | 145 | write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L); |
9ff32d8c | 146 | #endif |
6d0f6bcf JCPV |
147 | write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L); |
148 | write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L); | |
149 | write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L); | |
150 | write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L); | |
151 | write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L); | |
152 | write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L); | |
153 | write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L); | |
154 | write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L); | |
155 | write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L); | |
156 | write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L); | |
157 | write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); | |
158 | write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); | |
159 | write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L); | |
160 | write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L); | |
2d0daa03 BB |
161 | |
162 | return; | |
163 | } | |
c9315e6b BB |
164 | |
165 | #ifdef CONFIG_ADDR_MAP | |
166 | /* Initialize address mapping array */ | |
167 | void init_addr_map(void) | |
168 | { | |
169 | int i; | |
170 | ppc_bat_t bat = DBAT0; | |
171 | phys_size_t size; | |
172 | unsigned long upper, lower; | |
173 | ||
174 | for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { | |
175 | if (read_bat(bat, &upper, &lower) != -1) { | |
176 | if (!BATU_VALID(upper)) | |
177 | size = 0; | |
178 | else | |
179 | size = BATU_SIZE(upper); | |
180 | addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), | |
181 | size, i); | |
182 | } | |
183 | #ifdef CONFIG_HIGH_BATS | |
184 | /* High bats are not contiguous with low BAT numbers */ | |
185 | if (bat == DBAT3) | |
186 | bat = DBAT4 - 1; | |
187 | #endif | |
188 | } | |
189 | } | |
190 | #endif |