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d7949665 CL |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com | |
4 | * | |
5 | * SPDX-License-Identifier: GPL-2.0+ | |
6 | */ | |
7 | ||
8 | #include <common.h> | |
9 | #include <mpc8xx.h> | |
ba3da734 | 10 | #include <asm/io.h> |
f3603b43 | 11 | #include <asm/ppc.h> |
d7949665 | 12 | |
f3603b43 | 13 | void print_reginfo(void) |
d7949665 | 14 | { |
ba3da734 CL |
15 | immap_t __iomem *immap = (immap_t __iomem *)CONFIG_SYS_IMMR; |
16 | memctl8xx_t __iomem *memctl = &immap->im_memctl; | |
17 | sysconf8xx_t __iomem *sysconf = &immap->im_siu_conf; | |
18 | sit8xx_t __iomem *timers = &immap->im_sit; | |
d7949665 CL |
19 | |
20 | /* Hopefully more PowerPC knowledgable people will add code to display | |
21 | * other useful registers | |
22 | */ | |
23 | ||
70fd0710 | 24 | printf("\nSystem Configuration registers\n" |
d7949665 CL |
25 | "\tIMMR\t0x%08X\n", get_immr(0)); |
26 | ||
ba3da734 CL |
27 | printf("\tSIUMCR\t0x%08X", in_be32(&sysconf->sc_siumcr)); |
28 | printf("\tSYPCR\t0x%08X\n", in_be32(&sysconf->sc_sypcr)); | |
d7949665 | 29 | |
ba3da734 CL |
30 | printf("\tSWT\t0x%08X", in_be32(&sysconf->sc_swt)); |
31 | printf("\tSWSR\t0x%04X\n", in_be16(&sysconf->sc_swsr)); | |
d7949665 CL |
32 | |
33 | printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", | |
ba3da734 | 34 | in_be32(&sysconf->sc_sipend), in_be32(&sysconf->sc_simask)); |
d7949665 | 35 | printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", |
ba3da734 | 36 | in_be32(&sysconf->sc_siel), in_be32(&sysconf->sc_sivec)); |
d7949665 | 37 | printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", |
ba3da734 | 38 | in_be32(&sysconf->sc_tesr), in_be32(&sysconf->sc_sdcr)); |
d7949665 | 39 | |
ba3da734 CL |
40 | printf("Memory Controller Registers\n"); |
41 | printf("\tBR0\t0x%08X\tOR0\t0x%08X\n", in_be32(&memctl->memc_br0), | |
42 | in_be32(&memctl->memc_or0)); | |
43 | printf("\tBR1\t0x%08X\tOR1\t0x%08X\n", in_be32(&memctl->memc_br1), | |
44 | in_be32(&memctl->memc_or1)); | |
45 | printf("\tBR2\t0x%08X\tOR2\t0x%08X\n", in_be32(&memctl->memc_br2), | |
46 | in_be32(&memctl->memc_or2)); | |
47 | printf("\tBR3\t0x%08X\tOR3\t0x%08X\n", in_be32(&memctl->memc_br3), | |
48 | in_be32(&memctl->memc_or3)); | |
49 | printf("\tBR4\t0x%08X\tOR4\t0x%08X\n", in_be32(&memctl->memc_br4), | |
50 | in_be32(&memctl->memc_or4)); | |
51 | printf("\tBR5\t0x%08X\tOR5\t0x%08X\n", in_be32(&memctl->memc_br5), | |
52 | in_be32(&memctl->memc_or5)); | |
53 | printf("\tBR6\t0x%08X\tOR6\t0x%08X\n", in_be32(&memctl->memc_br6), | |
54 | in_be32(&memctl->memc_or6)); | |
55 | printf("\tBR7\t0x%08X\tOR7\t0x%08X\n", in_be32(&memctl->memc_br7), | |
56 | in_be32(&memctl->memc_or7)); | |
57 | printf("\n\tmamr\t0x%08X\tmbmr\t0x%08X\n", in_be32(&memctl->memc_mamr), | |
58 | in_be32(&memctl->memc_mbmr)); | |
59 | printf("\tmstat\t0x%04X\tmptpr\t0x%04X\n", in_be16(&memctl->memc_mstat), | |
60 | in_be16(&memctl->memc_mptpr)); | |
61 | printf("\tmdr\t0x%08X\n", in_be32(&memctl->memc_mdr)); | |
d7949665 | 62 | |
ba3da734 CL |
63 | printf("\nSystem Integration Timers\n"); |
64 | printf("\tTBSCR\t0x%04X\tRTCSC\t0x%04X\n", | |
65 | in_be16(&timers->sit_tbscr), in_be16(&timers->sit_rtcsc)); | |
66 | printf("\tPISCR\t0x%04X\n", in_be16(&timers->sit_piscr)); | |
d7949665 CL |
67 | |
68 | /* | |
69 | * May be some CPM info here? | |
70 | */ | |
71 | } |