[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8xx / serial.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <commproc.h>
#include <command.h>
#include <serial.h>
#include <watchdog.h>
#include <linux/compiler.h>

DECLARE_GLOBAL_DATA_PTR;

#if !defined(CONFIG_8xx_CONS_NONE)	/* No Console at all */

#if defined(CONFIG_8xx_CONS_SMC1)	/* Console on SMC1 */
#define	SMC_INDEX	0
#define PROFF_SMC	PROFF_SMC1
#define CPM_CR_CH_SMC	CPM_CR_CH_SMC1

#elif defined(CONFIG_8xx_CONS_SMC2)	/* Console on SMC2 */
#define SMC_INDEX	1
#define PROFF_SMC	PROFF_SMC2
#define CPM_CR_CH_SMC	CPM_CR_CH_SMC2

#endif /* CONFIG_8xx_CONS_SMCx */

#if defined(CONFIG_8xx_CONS_SCC1)	/* Console on SCC1 */
#define SCC_INDEX	0
#define PROFF_SCC	PROFF_SCC1
#define CPM_CR_CH_SCC	CPM_CR_CH_SCC1

#elif defined(CONFIG_8xx_CONS_SCC2)	/* Console on SCC2 */
#define SCC_INDEX	1
#define PROFF_SCC	PROFF_SCC2
#define CPM_CR_CH_SCC	CPM_CR_CH_SCC2

#elif defined(CONFIG_8xx_CONS_SCC3)	/* Console on SCC3 */
#define SCC_INDEX	2
#define PROFF_SCC	PROFF_SCC3
#define CPM_CR_CH_SCC	CPM_CR_CH_SCC3

#elif defined(CONFIG_8xx_CONS_SCC4)	/* Console on SCC4 */
#define SCC_INDEX	3
#define PROFF_SCC	PROFF_SCC4
#define CPM_CR_CH_SCC	CPM_CR_CH_SCC4

#endif /* CONFIG_8xx_CONS_SCCx */

#if !defined(CONFIG_SYS_SMC_RXBUFLEN)
#define CONFIG_SYS_SMC_RXBUFLEN	1
#define CONFIG_SYS_MAXIDLE	0
#else
#if !defined(CONFIG_SYS_MAXIDLE)
#error "you must define CONFIG_SYS_MAXIDLE"
#endif
#endif

typedef volatile struct serialbuffer {
	cbd_t	rxbd;		/* Rx BD */
	cbd_t	txbd;		/* Tx BD */
	uint	rxindex;	/* index for next character to read */
	volatile uchar	rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
	volatile uchar	txbuf;	/* tx buffers */
} serialbuffer_t;

static void serial_setdivisor(volatile cpm8xx_t *cp)
{
	int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;

	if(divisor/16>0x1000) {
		/* bad divisor, assume 50MHz clock and 9600 baud */
		divisor=(50*1000*1000 + 8*9600)/16/9600;
	}

#ifdef CONFIG_SYS_BRGCLK_PRESCALE
	divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
#endif

	if(divisor<=0x1000) {
		cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
	} else {
		cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
	}
}

#if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))

/*
 * Minimal serial functions needed to use one of the SMC ports
 * as serial console interface.
 */

static void smc_setbrg (void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cp = &(im->im_cpm);

	/* Set up the baud rate generator.
	 * See 8xx_io/commproc.c for details.
	 *
	 * Wire BRG1 to SMCx
	 */

	cp->cp_simode = 0x00000000;

	serial_setdivisor(cp);
}

static int smc_init (void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	volatile smc_t *sp;
	volatile smc_uart_t *up;
	volatile cpm8xx_t *cp = &(im->im_cpm);
#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
	volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
#endif
	uint	dpaddr;
	volatile serialbuffer_t *rtx;

	/* initialize pointers to SMC */

	sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
	up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
#ifdef CONFIG_SYS_SMC_UCODE_PATCH
	up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
#else
	/* Disable relocation */
	up->smc_rpbase = 0;
#endif

	/* Disable transmitter/receiver. */
	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);

	/* Enable SDMA. */
	im->im_siu_conf.sc_sdcr = 1;

	/* clear error conditions */
#ifdef	CONFIG_SYS_SDSR
	im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
#else
	im->im_sdma.sdma_sdsr = 0x83;
#endif

	/* clear SDMA interrupt mask */
#ifdef	CONFIG_SYS_SDMR
	im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
#else
	im->im_sdma.sdma_sdmr = 0x00;
#endif

#if defined(CONFIG_8xx_CONS_SMC1)
	/* Use Port B for SMC1 instead of other functions. */
	cp->cp_pbpar |=  0x000000c0;
	cp->cp_pbdir &= ~0x000000c0;
	cp->cp_pbodr &= ~0x000000c0;
#else	/* CONFIG_8xx_CONS_SMC2 */
# if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
	/* Use Port A for SMC2 instead of other functions. */
	ip->iop_papar |=  0x00c0;
	ip->iop_padir &= ~0x00c0;
	ip->iop_paodr &= ~0x00c0;
# else	/* must be a 860 then */
	/* Use Port B for SMC2 instead of other functions.
	 */
	cp->cp_pbpar |=  0x00000c00;
	cp->cp_pbdir &= ~0x00000c00;
	cp->cp_pbodr &= ~0x00000c00;
# endif
#endif

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */
	dpaddr = CPM_SERIAL_BASE;

	rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
	/* Allocate space for two buffer descriptors in the DP ram.
	 * For now, this address seems OK, but it may have to
	 * change with newer versions of the firmware.
	 * damm: allocating space after the two buffers for rx/tx data
	 */

	rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
	rtx->rxbd.cbd_sc      = 0;

	rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
	rtx->txbd.cbd_sc      = 0;

	/* Set up the uart parameters in the parameter ram. */
	up->smc_rbase = dpaddr;
	up->smc_tbase = dpaddr+sizeof(cbd_t);
	up->smc_rfcr = SMC_EB;
	up->smc_tfcr = SMC_EB;
#if defined (CONFIG_SYS_SMC_UCODE_PATCH)
	up->smc_rbptr = up->smc_rbase;
	up->smc_tbptr = up->smc_tbase;
	up->smc_rstate = 0;
	up->smc_tstate = 0;
#endif

	/* Set UART mode, 8 bit, no parity, one stop.
	 * Enable receive and transmit.
	 */
	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;

	/* Mask all interrupts and remove anything pending.
	*/
	sp->smc_smcm = 0;
	sp->smc_smce = 0xff;

#ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
	/* clock source is PLD */

	/* set freq to 19200 Baud */
	*((volatile uchar *) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
	/* configure clk4 as input */
	im->im_ioport.iop_pdpar |= 0x800;
	im->im_ioport.iop_pddir &= ~0x800;

	cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000);
#else
	/* Set up the baud rate generator */
	smc_setbrg ();
#endif

	/* Make the first buffer the only buffer. */
	rtx->txbd.cbd_sc |= BD_SC_WRAP;
	rtx->rxbd.cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;

	/* single/multi character receive. */
	up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
	up->smc_maxidl = CONFIG_SYS_MAXIDLE;
	rtx->rxindex = 0;

	/* Initialize Tx/Rx parameters.	*/
	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
	  ;

	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;

	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
	  ;

	/* Enable transmitter/receiver.	*/
	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;

	return (0);
}

static void
smc_putc(const char c)
{
	volatile smc_uart_t	*up;
	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
	volatile serialbuffer_t	*rtx;

	if (c == '\n')
		smc_putc ('\r');

	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
#ifdef CONFIG_SYS_SMC_UCODE_PATCH
	up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif

	rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];

	/* Wait for last character to go. */
	rtx->txbuf = c;
	rtx->txbd.cbd_datlen = 1;
	rtx->txbd.cbd_sc |= BD_SC_READY;
	__asm__("eieio");

	while (rtx->txbd.cbd_sc & BD_SC_READY) {
		WATCHDOG_RESET ();
		__asm__("eieio");
	}
}

static void
smc_puts (const char *s)
{
	while (*s) {
		smc_putc (*s++);
	}
}

static int
smc_getc(void)
{
	volatile smc_uart_t	*up;
	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
	volatile serialbuffer_t	*rtx;
	unsigned char  c;

	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
#ifdef CONFIG_SYS_SMC_UCODE_PATCH
	up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif
	rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];

	/* Wait for character to show up. */
	while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
		WATCHDOG_RESET ();

	/* the characters are read one by one,
	 * use the rxindex to know the next char to deliver
	 */
	c = *(unsigned char *) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
	rtx->rxindex++;

	/* check if all char are readout, then make prepare for next receive */
	if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
		rtx->rxindex = 0;
		rtx->rxbd.cbd_sc |= BD_SC_EMPTY;
	}
	return(c);
}

static int
smc_tstc(void)
{
	volatile smc_uart_t	*up;
	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
	volatile serialbuffer_t	*rtx;

	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
#ifdef CONFIG_SYS_SMC_UCODE_PATCH
	up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
#endif

	rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];

	return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
}

struct serial_device serial_smc_device =
{
	.name	= "serial_smc",
	.start	= smc_init,
	.stop	= NULL,
	.setbrg	= smc_setbrg,
	.getc	= smc_getc,
	.tstc	= smc_tstc,
	.putc	= smc_putc,
	.puts	= smc_puts,
};

#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */

#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
    defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)

static void
scc_setbrg (void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cp = &(im->im_cpm);

	/* Set up the baud rate generator.
	 * See 8xx_io/commproc.c for details.
	 *
	 * Wire BRG1 to SCCx
	 */

	cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));

	serial_setdivisor(cp);
}

static int scc_init (void)
{
	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
	volatile scc_t *sp;
	volatile scc_uart_t *up;
	volatile cbd_t *tbdf, *rbdf;
	volatile cpm8xx_t *cp = &(im->im_cpm);
	uint	 dpaddr;
#if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
	volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
#endif

	/* initialize pointers to SCC */

	sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
	up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];

	/* Disable transmitter/receiver. */
	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);

#if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
	/*
	 * The MPC850 has SCC3 on Port B
	 */
	cp->cp_pbpar |=  0x06;
	cp->cp_pbdir &= ~0x06;
	cp->cp_pbodr &= ~0x06;

#elif (SCC_INDEX < 2)
	/*
	 * Standard configuration for SCC's is on Part A
	 */
	ip->iop_papar |=  ((3 << (2 * SCC_INDEX)));
	ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
	ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
#endif

	/* Allocate space for two buffer descriptors in the DP ram. */
	dpaddr = dpram_alloc_align(sizeof(cbd_t)*2 + 2, 8);

	/* Enable SDMA.	*/
	im->im_siu_conf.sc_sdcr = 0x0001;

	/* Set the physical address of the host memory buffers in
	 * the buffer descriptors.
	 */

	rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
	rbdf->cbd_bufaddr = (uint) (rbdf+2);
	rbdf->cbd_sc = 0;
	tbdf = rbdf + 1;
	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
	tbdf->cbd_sc = 0;

	/* Set up the baud rate generator. */
	scc_setbrg ();

	/* Set up the uart parameters in the parameter ram. */
	up->scc_genscc.scc_rbase = dpaddr;
	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);

	/* Initialize Tx/Rx parameters. */
	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
		;
	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;

	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
		;

	up->scc_genscc.scc_rfcr  = SCC_EB | 0x05;
	up->scc_genscc.scc_tfcr  = SCC_EB | 0x05;

	up->scc_genscc.scc_mrblr = 1;	/* Single character receive */
	up->scc_maxidl = 0;		/* disable max idle */
	up->scc_brkcr  = 1;		/* send one break character on stop TX */
	up->scc_parec  = 0;
	up->scc_frmec  = 0;
	up->scc_nosec  = 0;
	up->scc_brkec  = 0;
	up->scc_uaddr1 = 0;
	up->scc_uaddr2 = 0;
	up->scc_toseq  = 0;
	up->scc_char1  = 0x8000;
	up->scc_char2  = 0x8000;
	up->scc_char3  = 0x8000;
	up->scc_char4  = 0x8000;
	up->scc_char5  = 0x8000;
	up->scc_char6  = 0x8000;
	up->scc_char7  = 0x8000;
	up->scc_char8  = 0x8000;
	up->scc_rccm   = 0xc0ff;

	/* Set low latency / small fifo. */
	sp->scc_gsmrh = SCC_GSMRH_RFW;

	/* Set SCC(x) clock mode to 16x
	 * See 8xx_io/commproc.c for details.
	 *
	 * Wire BRG1 to SCCn
	 */

	/* Set UART mode, clock divider 16 on Tx and Rx */
	sp->scc_gsmrl &= ~0xF;
	sp->scc_gsmrl |=
		(SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);

	sp->scc_psmr  = 0;
	sp->scc_psmr  |= SCU_PSMR_CL;

	/* Mask all interrupts and remove anything pending. */
	sp->scc_sccm = 0;
	sp->scc_scce = 0xffff;
	sp->scc_dsr  = 0x7e7e;
	sp->scc_psmr = 0x3000;

	/* Make the first buffer the only buffer. */
	tbdf->cbd_sc |= BD_SC_WRAP;
	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;

	/* Enable transmitter/receiver.	*/
	sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);

	return (0);
}

static void
scc_putc(const char c)
{
	volatile cbd_t		*tbdf;
	volatile char		*buf;
	volatile scc_uart_t	*up;
	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
	volatile cpm8xx_t	*cpmp = &(im->im_cpm);

	if (c == '\n')
		scc_putc ('\r');

	up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];

	tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];

	/* Wait for last character to go. */

	buf = (char *)tbdf->cbd_bufaddr;

	*buf = c;
	tbdf->cbd_datlen = 1;
	tbdf->cbd_sc |= BD_SC_READY;
	__asm__("eieio");

	while (tbdf->cbd_sc & BD_SC_READY) {
		__asm__("eieio");
		WATCHDOG_RESET ();
	}
}

static void
scc_puts (const char *s)
{
	while (*s) {
		scc_putc (*s++);
	}
}

static int
scc_getc(void)
{
	volatile cbd_t		*rbdf;
	volatile unsigned char	*buf;
	volatile scc_uart_t	*up;
	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
	unsigned char		c;

	up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];

	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];

	/* Wait for character to show up. */
	buf = (unsigned char *)rbdf->cbd_bufaddr;

	while (rbdf->cbd_sc & BD_SC_EMPTY)
		WATCHDOG_RESET ();

	c = *buf;
	rbdf->cbd_sc |= BD_SC_EMPTY;

	return(c);
}

static int
scc_tstc(void)
{
	volatile cbd_t		*rbdf;
	volatile scc_uart_t	*up;
	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
	volatile cpm8xx_t	*cpmp = &(im->im_cpm);

	up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];

	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];

	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
}

struct serial_device serial_scc_device =
{
	.name	= "serial_scc",
	.start	= scc_init,
	.stop	= NULL,
	.setbrg	= scc_setbrg,
	.getc	= scc_getc,
	.tstc	= scc_tstc,
	.putc	= scc_putc,
	.puts	= scc_puts,
};

#endif	/* CONFIG_8xx_CONS_SCCx */

__weak struct serial_device *default_serial_console(void)
{
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
	return &serial_smc_device;
#else
	return &serial_scc_device;
#endif
}

void mpc8xx_serial_initialize(void)
{
#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
	serial_register(&serial_smc_device);
#endif
#if	defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
	defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
	serial_register(&serial_scc_device);
#endif
}

#if defined(CONFIG_CMD_KGDB)

void
kgdb_serial_init(void)
{
	int i = -1;

	if (strcmp(default_serial_console()->name, "serial_smc") == 0)
	{
#if defined(CONFIG_8xx_CONS_SMC1)
		i = 1;
#elif defined(CONFIG_8xx_CONS_SMC2)
		i = 2;
#endif
	}
	else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
	{
#if defined(CONFIG_8xx_CONS_SCC1)
		i = 1;
#elif defined(CONFIG_8xx_CONS_SCC2)
		i = 2;
#elif defined(CONFIG_8xx_CONS_SCC3)
		i = 3;
#elif defined(CONFIG_8xx_CONS_SCC4)
		i = 4;
#endif
	}

	if (i >= 0)
	{
		serial_printf("[on %s%d] ", default_serial_console()->name, i);
	}
}

void
putDebugChar (int c)
{
	serial_putc (c);
}

void
putDebugStr (const char *str)
{
	serial_puts (str);
}

int
getDebugChar (void)
{
	return serial_getc();
}

void
kgdb_interruptible (int yes)
{
	return;
}
#endif

#endif	/* CONFIG_8xx_CONS_NONE */
Commit	Line	Data
4a9cbbe8 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
4a9cbbe8 WD	6	*/
	7
	8	#include <common.h>
	9	#include <commproc.h>
	10	#include <command.h>
281e00a3	11	#include <serial.h>
d0fb80c3	12	#include <watchdog.h>
6c768ca7	13	#include <linux/compiler.h>
4a9cbbe8	14
d87080b7 WD	15	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	16
4a9cbbe8 WD	17	#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
	18
	19	#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
	20	#define SMC_INDEX 0
4a9cbbe8 WD	21	#define PROFF_SMC PROFF_SMC1
	22	#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
	23
	24	#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
	25	#define SMC_INDEX 1
4a9cbbe8 WD	26	#define PROFF_SMC PROFF_SMC2
	27	#define CPM_CR_CH_SMC CPM_CR_CH_SMC2
	28
281e00a3 WD	29	#endif /* CONFIG_8xx_CONS_SMCx */
	30
	31	#if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
4a9cbbe8 WD	32	#define SCC_INDEX 0
	33	#define PROFF_SCC PROFF_SCC1
	34	#define CPM_CR_CH_SCC CPM_CR_CH_SCC1
	35
	36	#elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
4a9cbbe8 WD	37	#define SCC_INDEX 1
	38	#define PROFF_SCC PROFF_SCC2
	39	#define CPM_CR_CH_SCC CPM_CR_CH_SCC2
	40
	41	#elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
4a9cbbe8 WD	42	#define SCC_INDEX 2
	43	#define PROFF_SCC PROFF_SCC3
	44	#define CPM_CR_CH_SCC CPM_CR_CH_SCC3
	45
	46	#elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
4a9cbbe8 WD	47	#define SCC_INDEX 3
	48	#define PROFF_SCC PROFF_SCC4
	49	#define CPM_CR_CH_SCC CPM_CR_CH_SCC4
	50
281e00a3	51	#endif /* CONFIG_8xx_CONS_SCCx */
4a9cbbe8	52
2b3f12c2 HS	53	#if !defined(CONFIG_SYS_SMC_RXBUFLEN)
	54	#define CONFIG_SYS_SMC_RXBUFLEN 1
	55	#define CONFIG_SYS_MAXIDLE 0
	56	#else
	57	#if !defined(CONFIG_SYS_MAXIDLE)
	58	#error "you must define CONFIG_SYS_MAXIDLE"
	59	#endif
	60	#endif
	61
	62	typedef volatile struct serialbuffer {
	63	cbd_t rxbd; /* Rx BD */
	64	cbd_t txbd; /* Tx BD */
	65	uint rxindex; /* index for next character to read */
	66	volatile uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */
	67	volatile uchar txbuf; /* tx buffers */
	68	} serialbuffer_t;
	69
2535d602 WD	70	static void serial_setdivisor(volatile cpm8xx_t *cp)
2535d602 WD	71	{
75d1ea7f	72	int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
2535d602 WD	73
2535d602 WD	74	if(divisor/16>0x1000) {
8ed44d91	75	/* bad divisor, assume 50MHz clock and 9600 baud */
75d1ea7f	76	divisor=(5010001000 + 8*9600)/16/9600;
2535d602 WD	77	}
2535d602 WD	78
6d0f6bcf JCPV	79	#ifdef CONFIG_SYS_BRGCLK_PRESCALE
6d0f6bcf JCPV	80	divisor /= CONFIG_SYS_BRGCLK_PRESCALE;
3bbc899f WD	81	#endif
3bbc899f WD	82
2535d602 WD	83	if(divisor<=0x1000) {
	84	cp->cp_brgc1=((divisor-1)<<1) \| CPM_BRG_EN;
	85	} else {
	86	cp->cp_brgc1=((divisor/16-1)<<1) \| CPM_BRG_EN \| CPM_BRG_DIV16;
	87	}
	88	}
	89
4a9cbbe8 WD	90	#if (defined (CONFIG_8xx_CONS_SMC1) \|\| defined (CONFIG_8xx_CONS_SMC2))
	91
	92	/*
	93	* Minimal serial functions needed to use one of the SMC ports
	94	* as serial console interface.
	95	*/
	96
281e00a3 WD	97	static void smc_setbrg (void)
281e00a3 WD	98	{
6d0f6bcf	99	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
281e00a3 WD	100	volatile cpm8xx_t *cp = &(im->im_cpm);
	101
	102	/* Set up the baud rate generator.
	103	* See 8xx_io/commproc.c for details.
	104	*
	105	* Wire BRG1 to SMCx
	106	*/
	107
	108	cp->cp_simode = 0x00000000;
	109
	110	serial_setdivisor(cp);
	111	}
	112
	113	static int smc_init (void)
4a9cbbe8	114	{
6d0f6bcf	115	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8 WD	116	volatile smc_t *sp;
4a9cbbe8 WD	117	volatile smc_uart_t *up;
4a9cbbe8 WD	118	volatile cpm8xx_t *cp = &(im->im_cpm);
	119	#if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) \|\| defined(CONFIG_MPC850))
	120	volatile iop8xx_t ip = (iop8xx_t )&(im->im_ioport);
	121	#endif
	122	uint dpaddr;
2b3f12c2	123	volatile serialbuffer_t *rtx;
4a9cbbe8 WD	124
	125	/* initialize pointers to SMC */
	126
	127	sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
	128	up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
6d0f6bcf	129	#ifdef CONFIG_SYS_SMC_UCODE_PATCH
b423d055 HS	130	up = (smc_uart_t *) &cp->cp_dpmem[up->smc_rpbase];
	131	#else
	132	/* Disable relocation */
	133	up->smc_rpbase = 0;
	134	#endif
4a9cbbe8	135
255d28e1	136	/* Disable transmitter/receiver. */
4a9cbbe8 WD	137	sp->smc_smcmr &= ~(SMCMR_REN \| SMCMR_TEN);
4a9cbbe8 WD	138
255d28e1	139	/* Enable SDMA. */
4a9cbbe8 WD	140	im->im_siu_conf.sc_sdcr = 1;
	141
	142	/* clear error conditions */
6d0f6bcf JCPV	143	#ifdef CONFIG_SYS_SDSR
6d0f6bcf JCPV	144	im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
4a9cbbe8 WD	145	#else
	146	im->im_sdma.sdma_sdsr = 0x83;
	147	#endif
	148
	149	/* clear SDMA interrupt mask */
6d0f6bcf JCPV	150	#ifdef CONFIG_SYS_SDMR
6d0f6bcf JCPV	151	im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
4a9cbbe8 WD	152	#else
	153	im->im_sdma.sdma_sdmr = 0x00;
	154	#endif
	155
	156	#if defined(CONFIG_8xx_CONS_SMC1)
255d28e1	157	/* Use Port B for SMC1 instead of other functions. */
4a9cbbe8 WD	158	cp->cp_pbpar \|= 0x000000c0;
	159	cp->cp_pbdir &= ~0x000000c0;
	160	cp->cp_pbodr &= ~0x000000c0;
	161	#else /* CONFIG_8xx_CONS_SMC2 */
	162	# if defined(CONFIG_MPC823) \|\| defined(CONFIG_MPC850)
255d28e1	163	/* Use Port A for SMC2 instead of other functions. */
4a9cbbe8 WD	164	ip->iop_papar \|= 0x00c0;
	165	ip->iop_padir &= ~0x00c0;
	166	ip->iop_paodr &= ~0x00c0;
	167	# else /* must be a 860 then */
	168	/* Use Port B for SMC2 instead of other functions.
255d28e1	169	*/
4a9cbbe8 WD	170	cp->cp_pbpar \|= 0x00000c00;
	171	cp->cp_pbdir &= ~0x00000c00;
	172	cp->cp_pbodr &= ~0x00000c00;
	173	# endif
	174	#endif
	175
4a9cbbe8 WD	176	/* Set the physical address of the host memory buffers in
	177	* the buffer descriptors.
	178	*/
8f3086aa	179	dpaddr = CPM_SERIAL_BASE;
4a9cbbe8	180
2b3f12c2	181	rtx = (serialbuffer_t *)&cp->cp_dpmem[dpaddr];
4a9cbbe8 WD	182	/* Allocate space for two buffer descriptors in the DP ram.
	183	* For now, this address seems OK, but it may have to
	184	* change with newer versions of the firmware.
	185	* damm: allocating space after the two buffers for rx/tx data
	186	*/
	187
2b3f12c2 HS	188	rtx->rxbd.cbd_bufaddr = (uint) &rtx->rxbuf;
	189	rtx->rxbd.cbd_sc = 0;
	190
	191	rtx->txbd.cbd_bufaddr = (uint) &rtx->txbuf;
	192	rtx->txbd.cbd_sc = 0;
4a9cbbe8	193
255d28e1	194	/* Set up the uart parameters in the parameter ram. */
4a9cbbe8 WD	195	up->smc_rbase = dpaddr;
	196	up->smc_tbase = dpaddr+sizeof(cbd_t);
	197	up->smc_rfcr = SMC_EB;
	198	up->smc_tfcr = SMC_EB;
6d0f6bcf	199	#if defined (CONFIG_SYS_SMC_UCODE_PATCH)
b423d055 HS	200	up->smc_rbptr = up->smc_rbase;
	201	up->smc_tbptr = up->smc_tbase;
	202	up->smc_rstate = 0;
	203	up->smc_tstate = 0;
	204	#endif
4a9cbbe8	205
4a9cbbe8 WD	206	/* Set UART mode, 8 bit, no parity, one stop.
	207	* Enable receive and transmit.
	208	*/
	209	sp->smc_smcmr = smcr_mk_clen(9) \| SMCMR_SM_UART;
	210
	211	/* Mask all interrupts and remove anything pending.
	212	*/
	213	sp->smc_smcm = 0;
	214	sp->smc_smce = 0xff;
	215
6d0f6bcf	216	#ifdef CONFIG_SYS_SPC1920_SMC1_CLK4
8139567b	217	/* clock source is PLD */
2a8dfe08	218
8139567b	219	/* set freq to 19200 Baud */
6d0f6bcf	220	((volatile uchar ) CONFIG_SYS_SPC1920_PLD_BASE+6) = 0x3;
8139567b MK	221	/* configure clk4 as input */
	222	im->im_ioport.iop_pdpar \|= 0x800;
	223	im->im_ioport.iop_pddir &= ~0x800;
f11033e7	224
2a8dfe08	225	cp->cp_simode = ((cp->cp_simode & ~0xf000) \| 0x7000);
b02d0177 MK	226	#else
b02d0177 MK	227	/* Set up the baud rate generator */
281e00a3	228	smc_setbrg ();
b02d0177	229	#endif
4a9cbbe8	230
255d28e1	231	/* Make the first buffer the only buffer. */
2b3f12c2 HS	232	rtx->txbd.cbd_sc \|= BD_SC_WRAP;
2b3f12c2 HS	233	rtx->rxbd.cbd_sc \|= BD_SC_EMPTY \| BD_SC_WRAP;
4a9cbbe8	234
2b3f12c2 HS	235	/* single/multi character receive. */
	236	up->smc_mrblr = CONFIG_SYS_SMC_RXBUFLEN;
	237	up->smc_maxidl = CONFIG_SYS_MAXIDLE;
	238	rtx->rxindex = 0;
4a9cbbe8	239
255d28e1	240	/* Initialize Tx/Rx parameters. */
4a9cbbe8 WD	241	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
	242	;
	243
	244	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) \| CPM_CR_FLG;
	245
	246	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
	247	;
	248
255d28e1	249	/* Enable transmitter/receiver. */
4a9cbbe8 WD	250	sp->smc_smcmr \|= SMCMR_REN \| SMCMR_TEN;
	251
	252	return (0);
	253	}
	254
281e00a3 WD	255	static void
281e00a3 WD	256	smc_putc(const char c)
4a9cbbe8	257	{
4a9cbbe8	258	volatile smc_uart_t *up;
6d0f6bcf	259	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8	260	volatile cpm8xx_t *cpmp = &(im->im_cpm);
2b3f12c2	261	volatile serialbuffer_t *rtx;
4a9cbbe8 WD	262
4a9cbbe8 WD	263	if (c == '\n')
281e00a3	264	smc_putc ('\r');
4a9cbbe8 WD	265
4a9cbbe8 WD	266	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
6d0f6bcf	267	#ifdef CONFIG_SYS_SMC_UCODE_PATCH
b423d055 HS	268	up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
b423d055 HS	269	#endif
4a9cbbe8	270
2b3f12c2	271	rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
4a9cbbe8	272
255d28e1	273	/* Wait for last character to go. */
2b3f12c2 HS	274	rtx->txbuf = c;
	275	rtx->txbd.cbd_datlen = 1;
	276	rtx->txbd.cbd_sc \|= BD_SC_READY;
4a9cbbe8	277	__asm__("eieio");
d0fb80c3	278
2b3f12c2	279	while (rtx->txbd.cbd_sc & BD_SC_READY) {
d0fb80c3	280	WATCHDOG_RESET ();
4a9cbbe8	281	__asm__("eieio");
d0fb80c3	282	}
4a9cbbe8 WD	283	}
4a9cbbe8 WD	284
281e00a3 WD	285	static void
	286	smc_puts (const char *s)
	287	{
	288	while (*s) {
	289	smc_putc (*s++);
	290	}
	291	}
	292
	293	static int
	294	smc_getc(void)
4a9cbbe8	295	{
4a9cbbe8	296	volatile smc_uart_t *up;
6d0f6bcf	297	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8	298	volatile cpm8xx_t *cpmp = &(im->im_cpm);
2b3f12c2 HS	299	volatile serialbuffer_t *rtx;
2b3f12c2 HS	300	unsigned char c;
4a9cbbe8 WD	301
4a9cbbe8 WD	302	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
6d0f6bcf	303	#ifdef CONFIG_SYS_SMC_UCODE_PATCH
b423d055 HS	304	up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
b423d055 HS	305	#endif
2b3f12c2	306	rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
4a9cbbe8	307
255d28e1	308	/* Wait for character to show up. */
2b3f12c2	309	while (rtx->rxbd.cbd_sc & BD_SC_EMPTY)
d0fb80c3 WD	310	WATCHDOG_RESET ();
d0fb80c3 WD	311
2b3f12c2 HS	312	/* the characters are read one by one,
	313	* use the rxindex to know the next char to deliver
	314	*/
	315	c = (unsigned char ) (rtx->rxbd.cbd_bufaddr+rtx->rxindex);
	316	rtx->rxindex++;
4a9cbbe8	317
2b3f12c2 HS	318	/* check if all char are readout, then make prepare for next receive */
	319	if (rtx->rxindex >= rtx->rxbd.cbd_datlen) {
	320	rtx->rxindex = 0;
	321	rtx->rxbd.cbd_sc \|= BD_SC_EMPTY;
	322	}
4a9cbbe8 WD	323	return(c);
	324	}
	325
281e00a3 WD	326	static int
281e00a3 WD	327	smc_tstc(void)
4a9cbbe8	328	{
4a9cbbe8	329	volatile smc_uart_t *up;
6d0f6bcf	330	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8	331	volatile cpm8xx_t *cpmp = &(im->im_cpm);
2b3f12c2	332	volatile serialbuffer_t *rtx;
4a9cbbe8 WD	333
4a9cbbe8 WD	334	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
6d0f6bcf	335	#ifdef CONFIG_SYS_SMC_UCODE_PATCH
b423d055 HS	336	up = (smc_uart_t *) &cpmp->cp_dpmem[up->smc_rpbase];
b423d055 HS	337	#endif
4a9cbbe8	338
2b3f12c2	339	rtx = (serialbuffer_t *)&cpmp->cp_dpmem[up->smc_rbase];
4a9cbbe8	340
2b3f12c2	341	return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
4a9cbbe8 WD	342	}
4a9cbbe8 WD	343
281e00a3 WD	344	struct serial_device serial_smc_device =
281e00a3 WD	345	{
90bad891 MV	346	.name = "serial_smc",
	347	.start = smc_init,
	348	.stop = NULL,
	349	.setbrg = smc_setbrg,
	350	.getc = smc_getc,
	351	.tstc = smc_tstc,
	352	.putc = smc_putc,
	353	.puts = smc_puts,
281e00a3 WD	354	};
	355
	356	#endif /* CONFIG_8xx_CONS_SMC1 \|\| CONFIG_8xx_CONS_SMC2 */
	357
	358	#if defined(CONFIG_8xx_CONS_SCC1) \|\| defined(CONFIG_8xx_CONS_SCC2) \|\| \
	359	defined(CONFIG_8xx_CONS_SCC3) \|\| defined(CONFIG_8xx_CONS_SCC4)
	360
	361	static void
	362	scc_setbrg (void)
	363	{
6d0f6bcf	364	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
281e00a3	365	volatile cpm8xx_t *cp = &(im->im_cpm);
4a9cbbe8	366
281e00a3 WD	367	/* Set up the baud rate generator.
	368	* See 8xx_io/commproc.c for details.
	369	*
	370	* Wire BRG1 to SCCx
	371	*/
	372
	373	cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
	374
	375	serial_setdivisor(cp);
	376	}
	377
	378	static int scc_init (void)
4a9cbbe8	379	{
6d0f6bcf	380	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8 WD	381	volatile scc_t *sp;
	382	volatile scc_uart_t *up;
	383	volatile cbd_t tbdf, rbdf;
	384	volatile cpm8xx_t *cp = &(im->im_cpm);
	385	uint dpaddr;
	386	#if (SCC_INDEX != 2) \|\| !defined(CONFIG_MPC850)
	387	volatile iop8xx_t ip = (iop8xx_t )&(im->im_ioport);
	388	#endif
	389
	390	/* initialize pointers to SCC */
	391
	392	sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
	393	up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
	394
255d28e1	395	/* Disable transmitter/receiver. */
4a9cbbe8 WD	396	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	397
	398	#if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
	399	/*
	400	* The MPC850 has SCC3 on Port B
	401	*/
	402	cp->cp_pbpar \|= 0x06;
	403	cp->cp_pbdir &= ~0x06;
	404	cp->cp_pbodr &= ~0x06;
	405
5ec71100	406	#elif (SCC_INDEX < 2)
4a9cbbe8 WD	407	/*
	408	* Standard configuration for SCC's is on Part A
	409	*/
	410	ip->iop_papar \|= ((3 << (2 * SCC_INDEX)));
	411	ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
	412	ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
4a9cbbe8 WD	413	#endif
4a9cbbe8 WD	414
255d28e1	415	/* Allocate space for two buffer descriptors in the DP ram. */
8f3086aa	416	dpaddr = dpram_alloc_align(sizeof(cbd_t)*2 + 2, 8);
4a9cbbe8	417
255d28e1	418	/* Enable SDMA. */
4a9cbbe8 WD	419	im->im_siu_conf.sc_sdcr = 0x0001;
	420
	421	/* Set the physical address of the host memory buffers in
	422	* the buffer descriptors.
	423	*/
	424
	425	rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
	426	rbdf->cbd_bufaddr = (uint) (rbdf+2);
	427	rbdf->cbd_sc = 0;
	428	tbdf = rbdf + 1;
	429	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
	430	tbdf->cbd_sc = 0;
	431
255d28e1	432	/* Set up the baud rate generator. */
281e00a3	433	scc_setbrg ();
4a9cbbe8	434
255d28e1	435	/* Set up the uart parameters in the parameter ram. */
4a9cbbe8 WD	436	up->scc_genscc.scc_rbase = dpaddr;
	437	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
	438
255d28e1	439	/* Initialize Tx/Rx parameters. */
4a9cbbe8 WD	440	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
	441	;
	442	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) \| CPM_CR_FLG;
	443
	444	while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
	445	;
	446
	447	up->scc_genscc.scc_rfcr = SCC_EB \| 0x05;
	448	up->scc_genscc.scc_tfcr = SCC_EB \| 0x05;
	449
	450	up->scc_genscc.scc_mrblr = 1; /* Single character receive */
	451	up->scc_maxidl = 0; /* disable max idle */
	452	up->scc_brkcr = 1; /* send one break character on stop TX */
	453	up->scc_parec = 0;
	454	up->scc_frmec = 0;
	455	up->scc_nosec = 0;
	456	up->scc_brkec = 0;
	457	up->scc_uaddr1 = 0;
	458	up->scc_uaddr2 = 0;
	459	up->scc_toseq = 0;
	460	up->scc_char1 = 0x8000;
	461	up->scc_char2 = 0x8000;
	462	up->scc_char3 = 0x8000;
	463	up->scc_char4 = 0x8000;
	464	up->scc_char5 = 0x8000;
	465	up->scc_char6 = 0x8000;
	466	up->scc_char7 = 0x8000;
	467	up->scc_char8 = 0x8000;
	468	up->scc_rccm = 0xc0ff;
	469
255d28e1	470	/* Set low latency / small fifo. */
4a9cbbe8 WD	471	sp->scc_gsmrh = SCC_GSMRH_RFW;
	472
	473	/* Set SCC(x) clock mode to 16x
	474	* See 8xx_io/commproc.c for details.
	475	*
	476	* Wire BRG1 to SCCn
	477	*/
	478
255d28e1	479	/* Set UART mode, clock divider 16 on Tx and Rx */
281e00a3	480	sp->scc_gsmrl &= ~0xF;
4a9cbbe8 WD	481	sp->scc_gsmrl \|=
	482	(SCC_GSMRL_MODE_UART \| SCC_GSMRL_TDCR_16 \| SCC_GSMRL_RDCR_16);
	483
281e00a3	484	sp->scc_psmr = 0;
4a9cbbe8 WD	485	sp->scc_psmr \|= SCU_PSMR_CL;
4a9cbbe8 WD	486
255d28e1	487	/* Mask all interrupts and remove anything pending. */
4a9cbbe8 WD	488	sp->scc_sccm = 0;
	489	sp->scc_scce = 0xffff;
	490	sp->scc_dsr = 0x7e7e;
	491	sp->scc_psmr = 0x3000;
	492
255d28e1	493	/* Make the first buffer the only buffer. */
4a9cbbe8 WD	494	tbdf->cbd_sc \|= BD_SC_WRAP;
	495	rbdf->cbd_sc \|= BD_SC_EMPTY \| BD_SC_WRAP;
	496
255d28e1	497	/* Enable transmitter/receiver. */
4a9cbbe8 WD	498	sp->scc_gsmrl \|= (SCC_GSMRL_ENR \| SCC_GSMRL_ENT);
	499
	500	return (0);
	501	}
	502
281e00a3 WD	503	static void
281e00a3 WD	504	scc_putc(const char c)
4a9cbbe8 WD	505	{
	506	volatile cbd_t *tbdf;
	507	volatile char *buf;
	508	volatile scc_uart_t *up;
6d0f6bcf	509	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8 WD	510	volatile cpm8xx_t *cpmp = &(im->im_cpm);
	511
	512	if (c == '\n')
281e00a3	513	scc_putc ('\r');
4a9cbbe8 WD	514
	515	up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
	516
	517	tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
	518
255d28e1	519	/* Wait for last character to go. */
4a9cbbe8 WD	520
4a9cbbe8 WD	521	buf = (char *)tbdf->cbd_bufaddr;
4a9cbbe8 WD	522
	523	*buf = c;
	524	tbdf->cbd_datlen = 1;
	525	tbdf->cbd_sc \|= BD_SC_READY;
	526	__asm__("eieio");
d0fb80c3 WD	527
d0fb80c3 WD	528	while (tbdf->cbd_sc & BD_SC_READY) {
4a9cbbe8	529	__asm__("eieio");
d0fb80c3 WD	530	WATCHDOG_RESET ();
d0fb80c3 WD	531	}
4a9cbbe8 WD	532	}
4a9cbbe8 WD	533
281e00a3 WD	534	static void
	535	scc_puts (const char *s)
	536	{
	537	while (*s) {
	538	scc_putc (*s++);
	539	}
	540	}
	541
	542	static int
	543	scc_getc(void)
4a9cbbe8 WD	544	{
	545	volatile cbd_t *rbdf;
	546	volatile unsigned char *buf;
	547	volatile scc_uart_t *up;
6d0f6bcf	548	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8 WD	549	volatile cpm8xx_t *cpmp = &(im->im_cpm);
	550	unsigned char c;
	551
	552	up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
	553
	554	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
	555
255d28e1	556	/* Wait for character to show up. */
4a9cbbe8	557	buf = (unsigned char *)rbdf->cbd_bufaddr;
d0fb80c3	558
4a9cbbe8	559	while (rbdf->cbd_sc & BD_SC_EMPTY)
d0fb80c3 WD	560	WATCHDOG_RESET ();
d0fb80c3 WD	561
4a9cbbe8 WD	562	c = *buf;
	563	rbdf->cbd_sc \|= BD_SC_EMPTY;
	564
	565	return(c);
	566	}
	567
281e00a3 WD	568	static int
281e00a3 WD	569	scc_tstc(void)
4a9cbbe8 WD	570	{
	571	volatile cbd_t *rbdf;
	572	volatile scc_uart_t *up;
6d0f6bcf	573	volatile immap_t im = (immap_t )CONFIG_SYS_IMMR;
4a9cbbe8 WD	574	volatile cpm8xx_t *cpmp = &(im->im_cpm);
	575
	576	up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
	577
	578	rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
	579
	580	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
	581	}
	582
281e00a3 WD	583	struct serial_device serial_scc_device =
281e00a3 WD	584	{
90bad891 MV	585	.name = "serial_scc",
	586	.start = scc_init,
	587	.stop = NULL,
	588	.setbrg = scc_setbrg,
	589	.getc = scc_getc,
	590	.tstc = scc_tstc,
	591	.putc = scc_putc,
	592	.puts = scc_puts,
281e00a3 WD	593	};
	594
	595	#endif /* CONFIG_8xx_CONS_SCCx */
4a9cbbe8	596
6c768ca7 MF	597	__weak struct serial_device *default_serial_console(void)
	598	{
	599	#if defined(CONFIG_8xx_CONS_SMC1) \|\| defined(CONFIG_8xx_CONS_SMC2)
	600	return &serial_smc_device;
	601	#else
	602	return &serial_scc_device;
	603	#endif
	604	}
	605
f0eb1f61 MV	606	void mpc8xx_serial_initialize(void)
	607	{
	608	#if defined(CONFIG_8xx_CONS_SMC1) \|\| defined(CONFIG_8xx_CONS_SMC2)
	609	serial_register(&serial_smc_device);
	610	#endif
	611	#if defined(CONFIG_8xx_CONS_SCC1) \|\| defined(CONFIG_8xx_CONS_SCC2) \|\| \
	612	defined(CONFIG_8xx_CONS_SCC3) \|\| defined(CONFIG_8xx_CONS_SCC4)
	613	serial_register(&serial_scc_device);
	614	#endif
	615	}
	616
4431283c	617	#if defined(CONFIG_CMD_KGDB)
4a9cbbe8 WD	618
	619	void
	620	kgdb_serial_init(void)
	621	{
281e00a3 WD	622	int i = -1;
281e00a3 WD	623
1c9a5606	624	if (strcmp(default_serial_console()->name, "serial_smc") == 0)
281e00a3	625	{
4a9cbbe8	626	#if defined(CONFIG_8xx_CONS_SMC1)
281e00a3	627	i = 1;
4a9cbbe8	628	#elif defined(CONFIG_8xx_CONS_SMC2)
281e00a3 WD	629	i = 2;
	630	#endif
	631	}
1c9a5606	632	else if (strcmp(default_serial_console()->name, "serial_scc") == 0)
281e00a3 WD	633	{
	634	#if defined(CONFIG_8xx_CONS_SCC1)
	635	i = 1;
4a9cbbe8	636	#elif defined(CONFIG_8xx_CONS_SCC2)
281e00a3	637	i = 2;
4a9cbbe8	638	#elif defined(CONFIG_8xx_CONS_SCC3)
281e00a3	639	i = 3;
4a9cbbe8	640	#elif defined(CONFIG_8xx_CONS_SCC4)
281e00a3	641	i = 4;
4a9cbbe8	642	#endif
281e00a3 WD	643	}
	644
	645	if (i >= 0)
	646	{
1c9a5606	647	serial_printf("[on %s%d] ", default_serial_console()->name, i);
281e00a3	648	}
4a9cbbe8 WD	649	}
	650
	651	void
	652	putDebugChar (int c)
	653	{
	654	serial_putc (c);
	655	}
	656
	657	void
	658	putDebugStr (const char *str)
	659	{
	660	serial_puts (str);
	661	}
	662
	663	int
	664	getDebugChar (void)
	665	{
	666	return serial_getc();
	667	}
	668
	669	void
	670	kgdb_interruptible (int yes)
	671	{
	672	return;
	673	}
068b60a0	674	#endif
4a9cbbe8 WD	675
4a9cbbe8 WD	676	#endif /* CONFIG_8xx_CONS_NONE */