[people/ms/u-boot.git] / arch / powerpc / cpu / mpc8xx / spi.c

/*
 * Copyright (c) 2001 Navin Boppuri / Prashant Patel
 *	<nboppuri@trinetcommunication.com>,
 *	<pmpatel@trinetcommunication.com>
 * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
 * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * MPC8xx CPM SPI interface.
 *
 * Parts of this code are probably not portable and/or specific to
 * the board which I used for the tests. Please send fixes/complaints
 * to wd@denx.de
 *
 */

#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <linux/ctype.h>
#include <malloc.h>
#include <post.h>
#include <serial.h>

#if (defined(CONFIG_SPI)) || (CONFIG_POST & CONFIG_SYS_POST_SPI)

/* Warning:
 * You cannot enable DEBUG for early system initalization, i. e. when
 * this driver is used to read environment parameters like "baudrate"
 * from EEPROM which are used to initialize the serial port which is
 * needed to print the debug messages...
 */
#undef	DEBUG

#define SPI_EEPROM_WREN		0x06
#define SPI_EEPROM_RDSR		0x05
#define SPI_EEPROM_READ		0x03
#define SPI_EEPROM_WRITE	0x02

/* ---------------------------------------------------------------
 * Offset for initial SPI buffers in DPRAM:
 * We need a 520 byte scratch DPRAM area to use at an early stage.
 * It is used between the two initialization calls (spi_init_f()
 * and spi_init_r()).
 * The value 0xb00 makes it far enough from the start of the data
 * area (as well as from the stack pointer).
 * --------------------------------------------------------------- */
#ifndef	CONFIG_SYS_SPI_INIT_OFFSET
#define	CONFIG_SYS_SPI_INIT_OFFSET	0xB00
#endif

#ifdef	DEBUG

#define	DPRINT(a)	printf a;
/* -----------------------------------------------
 * Helper functions to peek into tx and rx buffers
 * ----------------------------------------------- */
static const char * const hex_digit = "0123456789ABCDEF";

static char quickhex (int i)
{
	return hex_digit[i];
}

static void memdump (void *pv, int num)
{
	int i;
	unsigned char *pc = (unsigned char *) pv;

	for (i = 0; i < num; i++)
		printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
	printf ("\t");
	for (i = 0; i < num; i++)
		printf ("%c", isprint (pc[i]) ? pc[i] : '.');
	printf ("\n");
}
#else	/* !DEBUG */

#define	DPRINT(a)

#endif	/* DEBUG */

/* -------------------
 * Function prototypes
 * ------------------- */
void spi_init (void);

ssize_t spi_read (uchar *, int, uchar *, int);
ssize_t spi_write (uchar *, int, uchar *, int);
ssize_t spi_xfer (size_t);

/* -------------------
 * Variables
 * ------------------- */

#define MAX_BUFFER	0x104

/* ----------------------------------------------------------------------
 * Initially we place the RX and TX buffers at a fixed location in DPRAM!
 * ---------------------------------------------------------------------- */
static uchar *rxbuf =
  (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
			[CONFIG_SYS_SPI_INIT_OFFSET];
static uchar *txbuf =
  (uchar *)&((cpm8xx_t *)&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
			[CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];

/* **************************************************************************
 *
 *  Function:    spi_init_f
 *
 *  Description: Init SPI-Controller (ROM part)
 *
 *  return:      ---
 *
 * *********************************************************************** */
void spi_init_f (void)
{
	unsigned int dpaddr;

	volatile spi_t *spi;
	volatile immap_t *immr;
	volatile cpm8xx_t *cp;
	volatile cbd_t *tbdf, *rbdf;

	immr = (immap_t *)  CONFIG_SYS_IMMR;
	cp   = (cpm8xx_t *) &immr->im_cpm;

#ifdef CONFIG_SYS_SPI_UCODE_PATCH
	spi  = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
#else
	spi  = (spi_t *)&cp->cp_dparam[PROFF_SPI];
	/* Disable relocation */
	spi->spi_rpbase = 0;
#endif

/* 1 */
	/* ------------------------------------------------
	 * Initialize Port B SPI pins -> page 34-8 MPC860UM
	 * (we are only in Master Mode !)
	 * ------------------------------------------------ */

	/* --------------------------------------------
	 * GPIO or per. Function
	 * PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
	 * PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
	 * PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
	 * PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
	 * -------------------------------------------- */
	cp->cp_pbpar |=  0x0000000E;	/* set  bits	*/
	cp->cp_pbpar &= ~0x00000001;	/* reset bit	*/

	/* ----------------------------------------------
	 * In/Out or per. Function 0/1
	 * PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
	 * PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
	 * PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
	 * PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
	 * ---------------------------------------------- */
	cp->cp_pbdir |= 0x0000000F;

	/* ----------------------------------------------
	 * open drain or active output
	 * PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
	 * PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
	 * PBODR[30] = 0 [0x00000002] -> active output: SPICLK
	 * PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
	 * ---------------------------------------------- */

	cp->cp_pbodr |=  0x00000008;
	cp->cp_pbodr &= ~0x00000007;

	/* Initialize the parameter ram.
	 * We need to make sure many things are initialized to zero
	 */
	spi->spi_rstate	= 0;
	spi->spi_rdp	= 0;
	spi->spi_rbptr	= 0;
	spi->spi_rbc	= 0;
	spi->spi_rxtmp	= 0;
	spi->spi_tstate	= 0;
	spi->spi_tdp	= 0;
	spi->spi_tbptr	= 0;
	spi->spi_tbc	= 0;
	spi->spi_txtmp	= 0;

	dpaddr = CPM_SPI_BASE;

/* 3 */
	/* Set up the SPI parameters in the parameter ram */
	spi->spi_rbase = dpaddr;
	spi->spi_tbase = dpaddr + sizeof (cbd_t);

	/***********IMPORTANT******************/

	/*
	 * Setting transmit and receive buffer descriptor pointers
	 * initially to rbase and tbase. Only the microcode patches
	 * documentation talks about initializing this pointer. This
	 * is missing from the sample I2C driver. If you dont
	 * initialize these pointers, the kernel hangs.
	 */
	spi->spi_rbptr = spi->spi_rbase;
	spi->spi_tbptr = spi->spi_tbase;

/* 4 */
#ifdef CONFIG_SYS_SPI_UCODE_PATCH
	/*
	 *  Initialize required parameters if using microcode patch.
	 */
	spi->spi_rstate = 0;
	spi->spi_tstate = 0;
#else
	/* Init SPI Tx + Rx Parameters */
	while (cp->cp_cpcr & CPM_CR_FLG)
		;
	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) | CPM_CR_FLG;
	while (cp->cp_cpcr & CPM_CR_FLG)
		;
#endif	/* CONFIG_SYS_SPI_UCODE_PATCH */

/* 5 */
	/* Set SDMA configuration register */
	immr->im_siu_conf.sc_sdcr = 0x0001;

/* 6 */
	/* Set to big endian. */
	spi->spi_tfcr = SMC_EB;
	spi->spi_rfcr = SMC_EB;

/* 7 */
	/* Set maximum receive size. */
	spi->spi_mrblr = MAX_BUFFER;

/* 8 + 9 */
	/* tx and rx buffer descriptors */
	tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
	rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];

	tbdf->cbd_sc &= ~BD_SC_READY;
	rbdf->cbd_sc &= ~BD_SC_EMPTY;

	/* Set the bd's rx and tx buffer address pointers */
	rbdf->cbd_bufaddr = (ulong) rxbuf;
	tbdf->cbd_bufaddr = (ulong) txbuf;

/* 10 + 11 */
	cp->cp_spim = 0;			/* Mask  all SPI events */
	cp->cp_spie = SPI_EMASK;		/* Clear all SPI events	*/

	return;
}

/* **************************************************************************
 *
 *  Function:    spi_init_r
 *
 *  Description: Init SPI-Controller (RAM part) -
 *		 The malloc engine is ready and we can move our buffers to
 *		 normal RAM
 *
 *  return:      ---
 *
 * *********************************************************************** */
void spi_init_r (void)
{
	volatile cpm8xx_t *cp;
	volatile spi_t *spi;
	volatile immap_t *immr;
	volatile cbd_t *tbdf, *rbdf;

	immr = (immap_t *)  CONFIG_SYS_IMMR;
	cp   = (cpm8xx_t *) &immr->im_cpm;

#ifdef CONFIG_SYS_SPI_UCODE_PATCH
	spi  = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
#else
	spi  = (spi_t *)&cp->cp_dparam[PROFF_SPI];
	/* Disable relocation */
	spi->spi_rpbase = 0;
#endif

	/* tx and rx buffer descriptors */
	tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
	rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];

	/* Allocate memory for RX and TX buffers */
	rxbuf = (uchar *) malloc (MAX_BUFFER);
	txbuf = (uchar *) malloc (MAX_BUFFER);

	rbdf->cbd_bufaddr = (ulong) rxbuf;
	tbdf->cbd_bufaddr = (ulong) txbuf;

	return;
}

/****************************************************************************
 *  Function:    spi_write
 **************************************************************************** */
ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
{
	int i;

	memset(rxbuf, 0, MAX_BUFFER);
	memset(txbuf, 0, MAX_BUFFER);
	*txbuf = SPI_EEPROM_WREN;		/* write enable		*/
	spi_xfer(1);
	memcpy(txbuf, addr, alen);
	*txbuf = SPI_EEPROM_WRITE;		/* WRITE memory array	*/
	memcpy(alen + txbuf, buffer, len);
	spi_xfer(alen + len);
						/* ignore received data	*/
	for (i = 0; i < 1000; i++) {
		*txbuf = SPI_EEPROM_RDSR;	/* read status		*/
		txbuf[1] = 0;
		spi_xfer(2);
		if (!(rxbuf[1] & 1)) {
			break;
		}
		udelay(1000);
	}
	if (i >= 1000) {
		printf ("*** spi_write: Time out while writing!\n");
	}

	return len;
}

/****************************************************************************
 *  Function:    spi_read
 **************************************************************************** */
ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
{
	memset(rxbuf, 0, MAX_BUFFER);
	memset(txbuf, 0, MAX_BUFFER);
	memcpy(txbuf, addr, alen);
	*txbuf = SPI_EEPROM_READ;		/* READ memory array	*/

	/*
	 * There is a bug in 860T (?) that cuts the last byte of input
	 * if we're reading into DPRAM. The solution we choose here is
	 * to always read len+1 bytes (we have one extra byte at the
	 * end of the buffer).
	 */
	spi_xfer(alen + len + 1);
	memcpy(buffer, alen + rxbuf, len);

	return len;
}

/****************************************************************************
 *  Function:    spi_xfer
 **************************************************************************** */
ssize_t spi_xfer (size_t count)
{
	volatile immap_t *immr;
	volatile cpm8xx_t *cp;
	volatile spi_t *spi;
	cbd_t *tbdf, *rbdf;
	ushort loop;
	int tm;

	DPRINT (("*** spi_xfer entered ***\n"));

	immr = (immap_t *) CONFIG_SYS_IMMR;
	cp   = (cpm8xx_t *) &immr->im_cpm;

#ifdef CONFIG_SYS_SPI_UCODE_PATCH
	spi  = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
#else
	spi  = (spi_t *)&cp->cp_dparam[PROFF_SPI];
	/* Disable relocation */
	spi->spi_rpbase = 0;
#endif

	tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
	rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];

	/* Set CS for device */
	cp->cp_pbdat &= ~0x0001;

	/* Setting tx bd status and data length */
	tbdf->cbd_sc  = BD_SC_READY | BD_SC_LAST | BD_SC_WRAP;
	tbdf->cbd_datlen = count;

	DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n",
							tbdf->cbd_datlen));

	/* Setting rx bd status and data length */
	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
	rbdf->cbd_datlen = 0;	 /* rx length has no significance */

	loop = cp->cp_spmode & SPMODE_LOOP;
	cp->cp_spmode = /*SPMODE_DIV16	|*/	/* BRG/16 mode not used here */
			loop		|
			SPMODE_REV	|
			SPMODE_MSTR	|
			SPMODE_EN	|
			SPMODE_LEN(8)	|	/* 8 Bits per char */
			SPMODE_PM(0x8) ;	/* medium speed */
	cp->cp_spim = 0;			/* Mask  all SPI events */
	cp->cp_spie = SPI_EMASK;		/* Clear all SPI events	*/

	/* start spi transfer */
	DPRINT (("*** spi_xfer: Performing transfer ...\n"));
	cp->cp_spcom |= SPI_STR;		/* Start transmit */

	/* --------------------------------
	 * Wait for SPI transmit to get out
	 * or time out (1 second = 1000 ms)
	 * -------------------------------- */
	for (tm=0; tm<1000; ++tm) {
		if (cp->cp_spie & SPI_TXB) {	/* Tx Buffer Empty */
			DPRINT (("*** spi_xfer: Tx buffer empty\n"));
			break;
		}
		if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
			DPRINT (("*** spi_xfer: Tx BD done\n"));
			break;
		}
		udelay (1000);
	}
	if (tm >= 1000) {
		printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
	}
	DPRINT (("*** spi_xfer: ... transfer ended\n"));

#ifdef	DEBUG
	printf ("\nspi_xfer: txbuf after xfer\n");
	memdump ((void *) txbuf, 16);	/* dump of txbuf before transmit */
	printf ("spi_xfer: rxbuf after xfer\n");
	memdump ((void *) rxbuf, 16);	/* dump of rxbuf after transmit */
	printf ("\n");
#endif

	/* Clear CS for device */
	cp->cp_pbdat |= 0x0001;

	return count;
}
#endif	/* CONFIG_SPI || (CONFIG_POST & CONFIG_SYS_POST_SPI) */

/*
 * SPI test
 *
 * The Serial Peripheral Interface (SPI) is tested in the local loopback mode.
 * The interface is configured accordingly and several packets
 * are transferred. The configurable test parameters are:
 *   TEST_MIN_LENGTH - minimum size of packet to transfer
 *   TEST_MAX_LENGTH - maximum size of packet to transfer
 *   TEST_NUM - number of tests
 */

#if CONFIG_POST & CONFIG_SYS_POST_SPI

#define TEST_MIN_LENGTH		1
#define TEST_MAX_LENGTH		MAX_BUFFER
#define TEST_NUM		1

static void packet_fill (char * packet, int length)
{
	char c = (char) length;
	int i;

	for (i = 0; i < length; i++)
	{
	    packet[i] = c++;
	}
}

static int packet_check (char * packet, int length)
{
	char c = (char) length;
	int i;

	for (i = 0; i < length; i++) {
	    if (packet[i] != c++) return -1;
	}

	return 0;
}

int spi_post_test (int flags)
{
	int res = -1;
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile cpm8xx_t *cp = (cpm8xx_t *) & immr->im_cpm;
	int i;
	int l;

	spi_init_f ();
	spi_init_r ();

	cp->cp_spmode |= SPMODE_LOOP;

	for (i = 0; i < TEST_NUM; i++) {
		for (l = TEST_MIN_LENGTH; l <= TEST_MAX_LENGTH; l += 8) {
			packet_fill ((char *)txbuf, l);

			spi_xfer (l);

			if (packet_check ((char *)rxbuf, l) < 0) {
				goto Done;
			}
		}
	}

	res = 0;

      Done:

	cp->cp_spmode &= ~SPMODE_LOOP;

	/*
	 * SCC2 parameter RAM space overlaps
	 * the SPI parameter RAM space. So we need to restore
	 * the SCC2 configuration if it is used by UART.
	 */

#if !defined(CONFIG_8xx_CONS_NONE)
	serial_reinit_all ();
#endif

	if (res != 0) {
		post_log ("SPI test failed\n");
	}

	return res;
}
#endif	/* CONFIG_POST & CONFIG_SYS_POST_SPI */
Commit	Line	Data
c609719b WD	1	/*
	2	* Copyright (c) 2001 Navin Boppuri / Prashant Patel
	3	* <nboppuri@trinetcommunication.com>,
	4	* <pmpatel@trinetcommunication.com>
	5	* Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
	6	* Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	9	*/
	10
	11	/*
	12	* MPC8xx CPM SPI interface.
	13	*
	14	* Parts of this code are probably not portable and/or specific to
	15	* the board which I used for the tests. Please send fixes/complaints
	16	* to wd@denx.de
	17	*
	18	*/
	19
	20	#include <common.h>
	21	#include <mpc8xx.h>
	22	#include <commproc.h>
	23	#include <linux/ctype.h>
	24	#include <malloc.h>
	25	#include <post.h>
281e00a3	26	#include <serial.h>
c609719b	27
6d0f6bcf	28	#if (defined(CONFIG_SPI)) \|\| (CONFIG_POST & CONFIG_SYS_POST_SPI)
c609719b WD	29
	30	/* Warning:
	31	* You cannot enable DEBUG for early system initalization, i. e. when
	32	* this driver is used to read environment parameters like "baudrate"
	33	* from EEPROM which are used to initialize the serial port which is
	34	* needed to print the debug messages...
	35	*/
	36	#undef DEBUG
	37
	38	#define SPI_EEPROM_WREN 0x06
	39	#define SPI_EEPROM_RDSR 0x05
	40	#define SPI_EEPROM_READ 0x03
	41	#define SPI_EEPROM_WRITE 0x02
	42
	43	/* ---------------------------------------------------------------
	44	* Offset for initial SPI buffers in DPRAM:
	45	* We need a 520 byte scratch DPRAM area to use at an early stage.
	46	* It is used between the two initialization calls (spi_init_f()
	47	* and spi_init_r()).
	48	* The value 0xb00 makes it far enough from the start of the data
	49	* area (as well as from the stack pointer).
	50	* --------------------------------------------------------------- */
6d0f6bcf JCPV	51	#ifndef CONFIG_SYS_SPI_INIT_OFFSET
6d0f6bcf JCPV	52	#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
c609719b WD	53	#endif
	54
	55	#ifdef DEBUG
	56
	57	#define DPRINT(a) printf a;
	58	/* -----------------------------------------------
	59	* Helper functions to peek into tx and rx buffers
	60	* ----------------------------------------------- */
	61	static const char * const hex_digit = "0123456789ABCDEF";
	62
	63	static char quickhex (int i)
	64	{
	65	return hex_digit[i];
	66	}
	67
	68	static void memdump (void *pv, int num)
	69	{
	70	int i;
	71	unsigned char pc = (unsigned char ) pv;
	72
	73	for (i = 0; i < num; i++)
	74	printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
	75	printf ("\t");
	76	for (i = 0; i < num; i++)
	77	printf ("%c", isprint (pc[i]) ? pc[i] : '.');
	78	printf ("\n");
	79	}
	80	#else /* !DEBUG */
	81
	82	#define DPRINT(a)
	83
	84	#endif /* DEBUG */
	85
	86	/* -------------------
	87	* Function prototypes
	88	* ------------------- */
	89	void spi_init (void);
	90
	91	ssize_t spi_read (uchar , int, uchar , int);
	92	ssize_t spi_write (uchar , int, uchar , int);
	93	ssize_t spi_xfer (size_t);
	94
	95	/* -------------------
	96	* Variables
	97	* ------------------- */
	98
	99	#define MAX_BUFFER 0x104
	100
	101	/* ----------------------------------------------------------------------
	102	* Initially we place the RX and TX buffers at a fixed location in DPRAM!
	103	* ---------------------------------------------------------------------- */
	104	static uchar *rxbuf =
6d0f6bcf JCPV	105	(uchar )&((cpm8xx_t )&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
6d0f6bcf JCPV	106	[CONFIG_SYS_SPI_INIT_OFFSET];
c609719b	107	static uchar *txbuf =
6d0f6bcf JCPV	108	(uchar )&((cpm8xx_t )&((immap_t *)CONFIG_SYS_IMMR)->im_cpm)->cp_dpmem
6d0f6bcf JCPV	109	[CONFIG_SYS_SPI_INIT_OFFSET+MAX_BUFFER];
c609719b WD	110
	111	/* **************************************************************************
	112	*
	113	* Function: spi_init_f
	114	*
	115	* Description: Init SPI-Controller (ROM part)
	116	*
	117	* return: ---
	118	*
	119	* *********************************************************************** */
	120	void spi_init_f (void)
	121	{
	122	unsigned int dpaddr;
	123
	124	volatile spi_t *spi;
	125	volatile immap_t *immr;
c609719b	126	volatile cpm8xx_t *cp;
c609719b WD	127	volatile cbd_t tbdf, rbdf;
c609719b WD	128
6d0f6bcf	129	immr = (immap_t *) CONFIG_SYS_IMMR;
c609719b WD	130	cp = (cpm8xx_t *) &immr->im_cpm;
c609719b WD	131
6d0f6bcf	132	#ifdef CONFIG_SYS_SPI_UCODE_PATCH
c609719b WD	133	spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
	134	#else
	135	spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
	136	/* Disable relocation */
	137	spi->spi_rpbase = 0;
	138	#endif
	139
	140	/* 1 */
	141	/* ------------------------------------------------
	142	* Initialize Port B SPI pins -> page 34-8 MPC860UM
	143	* (we are only in Master Mode !)
	144	* ------------------------------------------------ */
	145
	146	/* --------------------------------------------
	147	* GPIO or per. Function
	148	* PBPAR[28] = 1 [0x00000008] -> PERI: (SPIMISO)
	149	* PBPAR[29] = 1 [0x00000004] -> PERI: (SPIMOSI)
	150	* PBPAR[30] = 1 [0x00000002] -> PERI: (SPICLK)
	151	* PBPAR[31] = 0 [0x00000001] -> GPIO: (CS for PCUE/CCM-EEPROM)
	152	* -------------------------------------------- */
	153	cp->cp_pbpar \|= 0x0000000E; /* set bits */
	154	cp->cp_pbpar &= ~0x00000001; /* reset bit */
	155
	156	/* ----------------------------------------------
	157	* In/Out or per. Function 0/1
	158	* PBDIR[28] = 1 [0x00000008] -> PERI1: SPIMISO
	159	* PBDIR[29] = 1 [0x00000004] -> PERI1: SPIMOSI
	160	* PBDIR[30] = 1 [0x00000002] -> PERI1: SPICLK
	161	* PBDIR[31] = 1 [0x00000001] -> GPIO OUT: CS for PCUE/CCM-EEPROM
	162	* ---------------------------------------------- */
	163	cp->cp_pbdir \|= 0x0000000F;
	164
	165	/* ----------------------------------------------
	166	* open drain or active output
	167	* PBODR[28] = 1 [0x00000008] -> open drain: SPIMISO
	168	* PBODR[29] = 0 [0x00000004] -> active output SPIMOSI
	169	* PBODR[30] = 0 [0x00000002] -> active output: SPICLK
	170	* PBODR[31] = 0 [0x00000001] -> active output: GPIO OUT: CS for PCUE/CCM
	171	* ---------------------------------------------- */
	172
	173	cp->cp_pbodr \|= 0x00000008;
	174	cp->cp_pbodr &= ~0x00000007;
	175
	176	/* Initialize the parameter ram.
	177	* We need to make sure many things are initialized to zero
	178	*/
	179	spi->spi_rstate = 0;
	180	spi->spi_rdp = 0;
	181	spi->spi_rbptr = 0;
	182	spi->spi_rbc = 0;
	183	spi->spi_rxtmp = 0;
	184	spi->spi_tstate = 0;
	185	spi->spi_tdp = 0;
	186	spi->spi_tbptr = 0;
	187	spi->spi_tbc = 0;
	188	spi->spi_txtmp = 0;
	189
c609719b	190	dpaddr = CPM_SPI_BASE;
c609719b WD	191
	192	/* 3 */
	193	/* Set up the SPI parameters in the parameter ram */
	194	spi->spi_rbase = dpaddr;
	195	spi->spi_tbase = dpaddr + sizeof (cbd_t);
	196
	197	/*********IMPORTANT****************/
	198
8bde7f77 WD	199	/*
	200	* Setting transmit and receive buffer descriptor pointers
	201	* initially to rbase and tbase. Only the microcode patches
	202	* documentation talks about initializing this pointer. This
	203	* is missing from the sample I2C driver. If you dont
	204	* initialize these pointers, the kernel hangs.
c609719b WD	205	*/
	206	spi->spi_rbptr = spi->spi_rbase;
	207	spi->spi_tbptr = spi->spi_tbase;
	208
	209	/* 4 */
6d0f6bcf	210	#ifdef CONFIG_SYS_SPI_UCODE_PATCH
c609719b WD	211	/*
	212	* Initialize required parameters if using microcode patch.
	213	*/
	214	spi->spi_rstate = 0;
	215	spi->spi_tstate = 0;
	216	#else
	217	/* Init SPI Tx + Rx Parameters */
	218	while (cp->cp_cpcr & CPM_CR_FLG)
	219	;
	220	cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SPI, CPM_CR_INIT_TRX) \| CPM_CR_FLG;
	221	while (cp->cp_cpcr & CPM_CR_FLG)
	222	;
6d0f6bcf	223	#endif /* CONFIG_SYS_SPI_UCODE_PATCH */
c609719b WD	224
	225	/* 5 */
	226	/* Set SDMA configuration register */
	227	immr->im_siu_conf.sc_sdcr = 0x0001;
	228
	229	/* 6 */
	230	/* Set to big endian. */
	231	spi->spi_tfcr = SMC_EB;
	232	spi->spi_rfcr = SMC_EB;
	233
	234	/* 7 */
	235	/* Set maximum receive size. */
	236	spi->spi_mrblr = MAX_BUFFER;
	237
	238	/* 8 + 9 */
	239	/* tx and rx buffer descriptors */
	240	tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
	241	rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
	242
	243	tbdf->cbd_sc &= ~BD_SC_READY;
	244	rbdf->cbd_sc &= ~BD_SC_EMPTY;
	245
	246	/* Set the bd's rx and tx buffer address pointers */
	247	rbdf->cbd_bufaddr = (ulong) rxbuf;
	248	tbdf->cbd_bufaddr = (ulong) txbuf;
	249
	250	/* 10 + 11 */
	251	cp->cp_spim = 0; /* Mask all SPI events */
	252	cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
	253
	254	return;
	255	}
	256
	257	/* **************************************************************************
	258	*
	259	* Function: spi_init_r
	260	*
	261	* Description: Init SPI-Controller (RAM part) -
	262	* The malloc engine is ready and we can move our buffers to
	263	* normal RAM
	264	*
	265	* return: ---
	266	*
	267	* *********************************************************************** */
	268	void spi_init_r (void)
	269	{
	270	volatile cpm8xx_t *cp;
	271	volatile spi_t *spi;
	272	volatile immap_t *immr;
	273	volatile cbd_t tbdf, rbdf;
	274
6d0f6bcf	275	immr = (immap_t *) CONFIG_SYS_IMMR;
c609719b WD	276	cp = (cpm8xx_t *) &immr->im_cpm;
c609719b WD	277
6d0f6bcf	278	#ifdef CONFIG_SYS_SPI_UCODE_PATCH
c609719b WD	279	spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
	280	#else
	281	spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
	282	/* Disable relocation */
	283	spi->spi_rpbase = 0;
	284	#endif
	285
	286	/* tx and rx buffer descriptors */
	287	tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
	288	rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
	289
	290	/* Allocate memory for RX and TX buffers */
	291	rxbuf = (uchar *) malloc (MAX_BUFFER);
	292	txbuf = (uchar *) malloc (MAX_BUFFER);
	293
	294	rbdf->cbd_bufaddr = (ulong) rxbuf;
	295	tbdf->cbd_bufaddr = (ulong) txbuf;
	296
	297	return;
	298	}
	299
	300	/****************************************************************************
	301	* Function: spi_write
	302	**************************************************************************** */
	303	ssize_t spi_write (uchar addr, int alen, uchar buffer, int len)
	304	{
	305	int i;
	306
	307	memset(rxbuf, 0, MAX_BUFFER);
	308	memset(txbuf, 0, MAX_BUFFER);
	309	txbuf = SPI_EEPROM_WREN; / write enable */
	310	spi_xfer(1);
	311	memcpy(txbuf, addr, alen);
	312	txbuf = SPI_EEPROM_WRITE; / WRITE memory array */
	313	memcpy(alen + txbuf, buffer, len);
	314	spi_xfer(alen + len);
	315	/* ignore received data */
	316	for (i = 0; i < 1000; i++) {
	317	txbuf = SPI_EEPROM_RDSR; / read status */
	318	txbuf[1] = 0;
	319	spi_xfer(2);
	320	if (!(rxbuf[1] & 1)) {
	321	break;
	322	}
	323	udelay(1000);
	324	}
	325	if (i >= 1000) {
	326	printf ("*** spi_write: Time out while writing!\n");
	327	}
	328
	329	return len;
	330	}
	331
	332	/****************************************************************************
	333	* Function: spi_read
	334	**************************************************************************** */
	335	ssize_t spi_read (uchar addr, int alen, uchar buffer, int len)
	336	{
	337	memset(rxbuf, 0, MAX_BUFFER);
	338	memset(txbuf, 0, MAX_BUFFER);
	339	memcpy(txbuf, addr, alen);
	340	txbuf = SPI_EEPROM_READ; / READ memory array */
	341
	342	/*
343	* There is a bug in 860T (?) that cuts the last byte of input
344	* if we're reading into DPRAM. The solution we choose here is
345	* to always read len+1 bytes (we have one extra byte at the
346	* end of the buffer).
347	*/
348	spi_xfer(alen + len + 1);
349	memcpy(buffer, alen + rxbuf, len);
350
351	return len;
352	}
353
354	/****************************************************************************
355	* Function: spi_xfer
356	**************************************************************************** */
357	ssize_t spi_xfer (size_t count)
358	{
359	volatile immap_t *immr;
360	volatile cpm8xx_t *cp;
361	volatile spi_t *spi;
362	cbd_t tbdf, rbdf;
363	ushort loop;
364	int tm;
365
366	DPRINT (("* spi_xfer entered *\n"));
367
6d0f6bcf	368	immr = (immap_t *) CONFIG_SYS_IMMR;
c609719b WD	369	cp = (cpm8xx_t *) &immr->im_cpm;
c609719b WD	370
6d0f6bcf	371	#ifdef CONFIG_SYS_SPI_UCODE_PATCH
c609719b WD	372	spi = (spi_t *)&cp->cp_dpmem[spi->spi_rpbase];
	373	#else
	374	spi = (spi_t *)&cp->cp_dparam[PROFF_SPI];
	375	/* Disable relocation */
	376	spi->spi_rpbase = 0;
	377	#endif
	378
	379	tbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_tbase];
	380	rbdf = (cbd_t *) & cp->cp_dpmem[spi->spi_rbase];
	381
	382	/* Set CS for device */
	383	cp->cp_pbdat &= ~0x0001;
	384
	385	/* Setting tx bd status and data length */
	386	tbdf->cbd_sc = BD_SC_READY \| BD_SC_LAST \| BD_SC_WRAP;
	387	tbdf->cbd_datlen = count;
	388
	389	DPRINT (("* spi_xfer: Bytes to be xferred: %d *\n",
	390	tbdf->cbd_datlen));
	391
	392	/* Setting rx bd status and data length */
	393	rbdf->cbd_sc = BD_SC_EMPTY \| BD_SC_WRAP;
	394	rbdf->cbd_datlen = 0; /* rx length has no significance */
	395
	396	loop = cp->cp_spmode & SPMODE_LOOP;
	397	cp->cp_spmode = /SPMODE_DIV16 \|/ /* BRG/16 mode not used here */
	398	loop \|
	399	SPMODE_REV \|
	400	SPMODE_MSTR \|
	401	SPMODE_EN \|
	402	SPMODE_LEN(8) \| /* 8 Bits per char */
	403	SPMODE_PM(0x8) ; /* medium speed */
	404	cp->cp_spim = 0; /* Mask all SPI events */
	405	cp->cp_spie = SPI_EMASK; /* Clear all SPI events */
	406
	407	/* start spi transfer */
	408	DPRINT (("*** spi_xfer: Performing transfer ...\n"));
	409	cp->cp_spcom \|= SPI_STR; /* Start transmit */
	410
	411	/* --------------------------------
	412	* Wait for SPI transmit to get out
	413	* or time out (1 second = 1000 ms)
	414	* -------------------------------- */
	415	for (tm=0; tm<1000; ++tm) {
	416	if (cp->cp_spie & SPI_TXB) { /* Tx Buffer Empty */
	417	DPRINT (("*** spi_xfer: Tx buffer empty\n"));
	418	break;
	419	}
	420	if ((tbdf->cbd_sc & BD_SC_READY) == 0) {
	421	DPRINT (("*** spi_xfer: Tx BD done\n"));
	422	break;
	423	}
	424	udelay (1000);
	425	}
	426	if (tm >= 1000) {
	427	printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
	428	}
	429	DPRINT (("*** spi_xfer: ... transfer ended\n"));
	430
	431	#ifdef DEBUG
	432	printf ("\nspi_xfer: txbuf after xfer\n");
	433	memdump ((void ) txbuf, 16); / dump of txbuf before transmit */
	434	printf ("spi_xfer: rxbuf after xfer\n");
	435	memdump ((void ) rxbuf, 16); / dump of rxbuf after transmit */
436	printf ("\n");
437	#endif
438
439	/* Clear CS for device */
440	cp->cp_pbdat \|= 0x0001;
441
442	return count;
443	}
6d0f6bcf	444	#endif /* CONFIG_SPI \|\| (CONFIG_POST & CONFIG_SYS_POST_SPI) */
c609719b WD	445
	446	/*
	447	* SPI test
	448	*
	449	* The Serial Peripheral Interface (SPI) is tested in the local loopback mode.
	450	* The interface is configured accordingly and several packets
a6f70a3d	451	* are transferred. The configurable test parameters are:
c609719b WD	452	* TEST_MIN_LENGTH - minimum size of packet to transfer
	453	* TEST_MAX_LENGTH - maximum size of packet to transfer
	454	* TEST_NUM - number of tests
	455	*/
	456
6d0f6bcf	457	#if CONFIG_POST & CONFIG_SYS_POST_SPI
c609719b WD	458
	459	#define TEST_MIN_LENGTH 1
	460	#define TEST_MAX_LENGTH MAX_BUFFER
	461	#define TEST_NUM 1
	462
	463	static void packet_fill (char * packet, int length)
	464	{
	465	char c = (char) length;
	466	int i;
	467
	468	for (i = 0; i < length; i++)
	469	{
	470	packet[i] = c++;
	471	}
	472	}
	473
	474	static int packet_check (char * packet, int length)
	475	{
	476	char c = (char) length;
	477	int i;
	478
c837dcb1	479	for (i = 0; i < length; i++) {
c609719b WD	480	if (packet[i] != c++) return -1;
	481	}
	482
	483	return 0;
	484	}
	485
	486	int spi_post_test (int flags)
	487	{
c609719b	488	int res = -1;
6d0f6bcf	489	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
c837dcb1	490	volatile cpm8xx_t cp = (cpm8xx_t ) & immr->im_cpm;
c609719b WD	491	int i;
	492	int l;
	493
c837dcb1 WD	494	spi_init_f ();
c837dcb1 WD	495	spi_init_r ();
c609719b WD	496
	497	cp->cp_spmode \|= SPMODE_LOOP;
	498
c837dcb1 WD	499	for (i = 0; i < TEST_NUM; i++) {
c837dcb1 WD	500	for (l = TEST_MIN_LENGTH; l <= TEST_MAX_LENGTH; l += 8) {
77ddac94	501	packet_fill ((char *)txbuf, l);
c609719b	502
c837dcb1	503	spi_xfer (l);
c609719b	504
77ddac94	505	if (packet_check ((char *)rxbuf, l) < 0) {
c837dcb1 WD	506	goto Done;
c837dcb1 WD	507	}
c609719b	508	}
c609719b WD	509	}
	510
	511	res = 0;
	512
c837dcb1	513	Done:
c609719b WD	514
	515	cp->cp_spmode &= ~SPMODE_LOOP;
	516
	517	/*
281e00a3	518	* SCC2 parameter RAM space overlaps
c609719b	519	* the SPI parameter RAM space. So we need to restore
281e00a3	520	* the SCC2 configuration if it is used by UART.
c609719b WD	521	*/
c609719b WD	522
281e00a3 WD	523	#if !defined(CONFIG_8xx_CONS_NONE)
281e00a3 WD	524	serial_reinit_all ();
c609719b WD	525	#endif
c609719b WD	526
c837dcb1 WD	527	if (res != 0) {
c837dcb1 WD	528	post_log ("SPI test failed\n");
c609719b WD	529	}
	530
	531	return res;
	532	}
6d0f6bcf	533	#endif /* CONFIG_POST & CONFIG_SYS_POST_SPI */