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18bacc20 | 1 | /* |
21608275 | 2 | * Copyright 2009-2010 Freescale Semiconductor, Inc. |
18bacc20 | 3 | * |
a47a12be SR |
4 | * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and |
5 | * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains | |
8d1f2682 | 6 | * cpu specific common code for 85xx/86xx processors. |
18bacc20 PA |
7 | * See file CREDITS for list of people who contributed to this |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <config.h> | |
27 | #include <common.h> | |
28 | #include <command.h> | |
29 | #include <tsec.h> | |
30 | #include <netdev.h> | |
31 | #include <asm/cache.h> | |
32 | #include <asm/io.h> | |
33 | ||
34 | DECLARE_GLOBAL_DATA_PTR; | |
35 | ||
36 | struct cpu_type cpu_type_list [] = { | |
37 | #if defined(CONFIG_MPC85xx) | |
0e870980 PA |
38 | CPU_TYPE_ENTRY(8533, 8533, 1), |
39 | CPU_TYPE_ENTRY(8533, 8533_E, 1), | |
40 | CPU_TYPE_ENTRY(8535, 8535, 1), | |
41 | CPU_TYPE_ENTRY(8535, 8535_E, 1), | |
42 | CPU_TYPE_ENTRY(8536, 8536, 1), | |
43 | CPU_TYPE_ENTRY(8536, 8536_E, 1), | |
44 | CPU_TYPE_ENTRY(8540, 8540, 1), | |
45 | CPU_TYPE_ENTRY(8541, 8541, 1), | |
46 | CPU_TYPE_ENTRY(8541, 8541_E, 1), | |
47 | CPU_TYPE_ENTRY(8543, 8543, 1), | |
48 | CPU_TYPE_ENTRY(8543, 8543_E, 1), | |
49 | CPU_TYPE_ENTRY(8544, 8544, 1), | |
50 | CPU_TYPE_ENTRY(8544, 8544_E, 1), | |
51 | CPU_TYPE_ENTRY(8545, 8545, 1), | |
52 | CPU_TYPE_ENTRY(8545, 8545_E, 1), | |
53 | CPU_TYPE_ENTRY(8547, 8547_E, 1), | |
54 | CPU_TYPE_ENTRY(8548, 8548, 1), | |
55 | CPU_TYPE_ENTRY(8548, 8548_E, 1), | |
56 | CPU_TYPE_ENTRY(8555, 8555, 1), | |
57 | CPU_TYPE_ENTRY(8555, 8555_E, 1), | |
58 | CPU_TYPE_ENTRY(8560, 8560, 1), | |
59 | CPU_TYPE_ENTRY(8567, 8567, 1), | |
60 | CPU_TYPE_ENTRY(8567, 8567_E, 1), | |
61 | CPU_TYPE_ENTRY(8568, 8568, 1), | |
62 | CPU_TYPE_ENTRY(8568, 8568_E, 1), | |
63 | CPU_TYPE_ENTRY(8569, 8569, 1), | |
64 | CPU_TYPE_ENTRY(8569, 8569_E, 1), | |
65 | CPU_TYPE_ENTRY(8572, 8572, 2), | |
66 | CPU_TYPE_ENTRY(8572, 8572_E, 2), | |
a713ba92 PA |
67 | CPU_TYPE_ENTRY(P1011, P1011, 1), |
68 | CPU_TYPE_ENTRY(P1011, P1011_E, 1), | |
21608275 KG |
69 | CPU_TYPE_ENTRY(P1012, P1012, 1), |
70 | CPU_TYPE_ENTRY(P1012, P1012_E, 1), | |
71 | CPU_TYPE_ENTRY(P1013, P1013, 1), | |
72 | CPU_TYPE_ENTRY(P1013, P1013_E, 1), | |
87c7661b PA |
73 | CPU_TYPE_ENTRY(P1020, P1020, 2), |
74 | CPU_TYPE_ENTRY(P1020, P1020_E, 2), | |
21608275 KG |
75 | CPU_TYPE_ENTRY(P1021, P1021, 2), |
76 | CPU_TYPE_ENTRY(P1021, P1021_E, 2), | |
77 | CPU_TYPE_ENTRY(P1022, P1022, 2), | |
78 | CPU_TYPE_ENTRY(P1022, P1022_E, 2), | |
a713ba92 PA |
79 | CPU_TYPE_ENTRY(P2010, P2010, 1), |
80 | CPU_TYPE_ENTRY(P2010, P2010_E, 1), | |
81 | CPU_TYPE_ENTRY(P2020, P2020, 2), | |
82 | CPU_TYPE_ENTRY(P2020, P2020_E, 2), | |
7e4259bb KG |
83 | CPU_TYPE_ENTRY(P4040, P4040, 4), |
84 | CPU_TYPE_ENTRY(P4040, P4040_E, 4), | |
85 | CPU_TYPE_ENTRY(P4080, P4080, 8), | |
86 | CPU_TYPE_ENTRY(P4080, P4080_E, 8), | |
18bacc20 | 87 | #elif defined(CONFIG_MPC86xx) |
0e870980 PA |
88 | CPU_TYPE_ENTRY(8610, 8610, 1), |
89 | CPU_TYPE_ENTRY(8641, 8641, 2), | |
90 | CPU_TYPE_ENTRY(8641D, 8641D, 2), | |
18bacc20 PA |
91 | #endif |
92 | }; | |
93 | ||
58442dc0 PA |
94 | struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); |
95 | ||
18bacc20 PA |
96 | struct cpu_type *identify_cpu(u32 ver) |
97 | { | |
98 | int i; | |
99 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) { | |
100 | if (cpu_type_list[i].soc_ver == ver) | |
101 | return &cpu_type_list[i]; | |
102 | } | |
58442dc0 | 103 | return &cpu_type_unknown; |
18bacc20 PA |
104 | } |
105 | ||
0e870980 PA |
106 | int cpu_numcores() { |
107 | struct cpu_type *cpu; | |
108 | cpu = gd->cpu; | |
109 | return cpu->num_cores; | |
110 | } | |
111 | ||
112 | int probecpu (void) | |
113 | { | |
114 | uint svr; | |
115 | uint ver; | |
116 | ||
117 | svr = get_svr(); | |
118 | ver = SVR_SOC_VER(svr); | |
119 | ||
120 | gd->cpu = identify_cpu(ver); | |
121 | ||
0e870980 PA |
122 | return 0; |
123 | } | |
124 | ||
18bacc20 PA |
125 | /* |
126 | * Initializes on-chip ethernet controllers. | |
127 | * to override, implement board_eth_init() | |
128 | */ | |
129 | int cpu_eth_init(bd_t *bis) | |
130 | { | |
131 | #if defined(CONFIG_ETHER_ON_FCC) | |
132 | fec_initialize(bis); | |
133 | #endif | |
134 | ||
135 | #if defined(CONFIG_UEC_ETH) | |
136 | uec_standard_init(bis); | |
137 | #endif | |
138 | ||
139 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC) | |
140 | tsec_standard_init(bis); | |
141 | #endif | |
142 | ||
143 | return 0; | |
144 | } |