[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / 40x_spd_sdram.c

/*
 * arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
 * This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
 * SDRAM controller. Those are all current 405 PPC's.
 *
 * (C) Copyright 2001
 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
 *
 * Based on code by:
 *
 * Kenneth Johansson ,Ericsson AB.
 * kenneth.johansson@etx.ericsson.se
 *
 * hacked up by bill hunter. fixed so we could run before
 * serial_init and console_init. previous version avoided this by
 * running out of cache memory during serial/console init, then running
 * this code later.
 *
 * (C) Copyright 2002
 * Jun Gu, Artesyn Technology, jung@artesyncp.com
 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
 *
 * (C) Copyright 2005
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <i2c.h>
#include <asm/ppc4xx.h>

#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)

/*
 * Set default values
 */
#define ONE_BILLION	1000000000

#define	 SDRAM0_CFG_DCE		0x80000000
#define	 SDRAM0_CFG_SRE		0x40000000
#define	 SDRAM0_CFG_PME		0x20000000
#define	 SDRAM0_CFG_MEMCHK	0x10000000
#define	 SDRAM0_CFG_REGEN	0x08000000
#define	 SDRAM0_CFG_ECCDD	0x00400000
#define	 SDRAM0_CFG_EMDULR	0x00200000
#define	 SDRAM0_CFG_DRW_SHIFT	(31-6)
#define	 SDRAM0_CFG_BRPF_SHIFT	(31-8)

#define	 SDRAM0_TR_CASL_SHIFT	(31-8)
#define	 SDRAM0_TR_PTA_SHIFT	(31-13)
#define	 SDRAM0_TR_CTP_SHIFT	(31-15)
#define	 SDRAM0_TR_LDF_SHIFT	(31-17)
#define	 SDRAM0_TR_RFTA_SHIFT	(31-29)
#define	 SDRAM0_TR_RCD_SHIFT	(31-31)

#define	 SDRAM0_RTR_SHIFT	(31-15)
#define	 SDRAM0_ECCCFG_SHIFT	(31-11)

/* SDRAM0_CFG enable macro  */
#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )

#define SDRAM0_BXCR_SZ_MASK	0x000e0000
#define SDRAM0_BXCR_AM_MASK	0x0000e000

#define SDRAM0_BXCR_SZ_SHIFT	(31-14)
#define SDRAM0_BXCR_AM_SHIFT	(31-18)

#define SDRAM0_BXCR_SZ(x)	( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
#define SDRAM0_BXCR_AM(x)	( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )

#ifdef CONFIG_SPDDRAM_SILENT
# define SPD_ERR(x) do { return 0; } while (0)
#else
# define SPD_ERR(x) do { printf(x); return(0); } while (0)
#endif

#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))

/* function prototypes */
int spd_read(uint addr);


/*
 * This function is reading data from the DIMM module EEPROM over the SPD bus
 * and uses that to program the sdram controller.
 *
 * This works on boards that has the same schematics that the AMCC walnut has.
 *
 * Input: null for default I2C spd functions or a pointer to a custom function
 * returning spd_data.
 */

long int spd_sdram(int(read_spd)(uint addr))
{
	int tmp,row,col;
	int total_size,bank_size,bank_code;
	int mode;
	int bank_cnt;

	int sdram0_pmit=0x07c00000;
	int sdram0_b0cr;
	int sdram0_b1cr = 0;
#ifndef CONFIG_405EP /* not on PPC405EP */
	int sdram0_b2cr = 0;
	int sdram0_b3cr = 0;
	int sdram0_besr0 = -1;
	int sdram0_besr1 = -1;
	int sdram0_eccesr = -1;
	int sdram0_ecccfg;
	int ecc_on;
#endif

	int sdram0_rtr=0;
	int sdram0_tr=0;

	int sdram0_cfg=0;

	int t_rp;
	int t_rcd;
	int t_ras;
	int t_rc;
	int min_cas;

	PPC4xx_SYS_INFO sys_info;
	unsigned long bus_period_x_10;

	/*
	 * get the board info
	 */
	get_sys_info(&sys_info);
	bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);

	if (read_spd == 0){
		read_spd=spd_read;
		/*
		 * Make sure I2C controller is initialized
		 * before continuing.
		 */
		i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
	}

	/* Make shure we are using SDRAM */
	if (read_spd(2) != 0x04) {
		SPD_ERR("SDRAM - non SDRAM memory module found\n");
	}

	/* ------------------------------------------------------------------
	 * configure memory timing register
	 *
	 * data from DIMM:
	 * 27	IN Row Precharge Time ( t RP)
	 * 29	MIN RAS to CAS Delay ( t RCD)
	 * 127	 Component and Clock Detail ,clk0-clk3, junction temp, CAS
	 * -------------------------------------------------------------------*/

	/*
	 * first figure out which cas latency mode to use
	 * use the min supported mode
	 */

	tmp = read_spd(127) & 0x6;
	if (tmp == 0x02) {		/* only cas = 2 supported */
		min_cas = 2;
/*		t_ck = read_spd(9); */
/*		t_ac = read_spd(10); */
	} else if (tmp == 0x04) {	/* only cas = 3 supported */
		min_cas = 3;
/*		t_ck = read_spd(9); */
/*		t_ac = read_spd(10); */
	} else if (tmp == 0x06) {	/* 2,3 supported, so use 2 */
		min_cas = 2;
/*		t_ck = read_spd(23); */
/*		t_ac = read_spd(24); */
	} else {
		SPD_ERR("SDRAM - unsupported CAS latency \n");
	}

	/* get some timing values, t_rp,t_rcd,t_ras,t_rc
	 */
	t_rp = read_spd(27);
	t_rcd = read_spd(29);
	t_ras = read_spd(30);
	t_rc = t_ras + t_rp;

	/* The following timing calcs subtract 1 before deviding.
	 * this has effect of using ceiling instead of floor rounding,
	 * and also subtracting 1 to convert number to reg value
	 */
	/* set up CASL */
	sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
	/* set up PTA */
	sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
	/* set up CTP */
	tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
	if (tmp < 1)
		tmp = 1;
	sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
	/* set LDF	= 2 cycles, reg value = 1 */
	sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
	/* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
	tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
	if (tmp < 0)
		tmp = 0;
	if (tmp > 6)
		tmp = 6;
	sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
	/* set RCD = t_rcd/bus_period*/
	sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;


	/*------------------------------------------------------------------
	 * configure RTR register
	 * -------------------------------------------------------------------*/
	row = read_spd(3);
	col = read_spd(4);
	tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
	switch (tmp) {
	case 0x00:
		tmp = 15625;
		break;
	case 0x01:
		tmp = 15625 / 4;
		break;
	case 0x02:
		tmp = 15625 / 2;
		break;
	case 0x03:
		tmp = 15625 * 2;
		break;
	case 0x04:
		tmp = 15625 * 4;
		break;
	case 0x05:
		tmp = 15625 * 8;
		break;
	default:
		SPD_ERR("SDRAM - Bad refresh period \n");
	}
	/* convert from nsec to bus cycles */
	tmp = (tmp * 10) / bus_period_x_10;
	sdram0_rtr = (tmp & 0x3ff8) <<	SDRAM0_RTR_SHIFT;

	/*------------------------------------------------------------------
	 * determine the number of banks used
	 * -------------------------------------------------------------------*/
	/* byte 7:6 is module data width */
	if (read_spd(7) != 0)
		SPD_ERR("SDRAM - unsupported module width\n");
	tmp = read_spd(6);
	if (tmp < 32)
		SPD_ERR("SDRAM - unsupported module width\n");
	else if (tmp < 64)
		bank_cnt = 1;		/* one bank per sdram side */
	else if (tmp < 73)
		bank_cnt = 2;	/* need two banks per side */
	else if (tmp < 161)
		bank_cnt = 4;	/* need four banks per side */
	else
		SPD_ERR("SDRAM - unsupported module width\n");

	/* byte 5 is the module row count (refered to as dimm "sides") */
	tmp = read_spd(5);
	if (tmp == 1)
		;
	else if (tmp==2)
		bank_cnt *= 2;
	else if (tmp==4)
		bank_cnt *= 4;
	else
		bank_cnt = 8;		/* 8 is an error code */

	if (bank_cnt > 4)	/* we only have 4 banks to work with */
		SPD_ERR("SDRAM - unsupported module rows for this width\n");

#ifndef CONFIG_405EP /* not on PPC405EP */
	/* now check for ECC ability of module. We only support ECC
	 *   on 32 bit wide devices with 8 bit ECC.
	 */
	if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
		sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
		ecc_on = 1;
	} else {
		sdram0_ecccfg = 0;
		ecc_on = 0;
	}
#endif

	/*------------------------------------------------------------------
	 * calculate total size
	 * -------------------------------------------------------------------*/
	/* calculate total size and do sanity check */
	tmp = read_spd(31);
	total_size = 1 << 22;	/* total_size = 4MB */
	/* now multiply 4M by the smallest device row density */
	/* note that we don't support asymetric rows */
	while (((tmp & 0x0001) == 0) && (tmp != 0)) {
		total_size = total_size << 1;
		tmp = tmp >> 1;
	}
	total_size *= read_spd(5);	/* mult by module rows (dimm sides) */

	/*------------------------------------------------------------------
	 * map	rows * cols * banks to a mode
	 * -------------------------------------------------------------------*/

	switch (row) {
	case 11:
		switch (col) {
		case 8:
			mode=4; /* mode 5 */
			break;
		case 9:
		case 10:
			mode=0; /* mode 1 */
			break;
		default:
			SPD_ERR("SDRAM - unsupported mode\n");
		}
		break;
	case 12:
		switch (col) {
		case 8:
			mode=3; /* mode 4 */
			break;
		case 9:
		case 10:
			mode=1; /* mode 2 */
			break;
		default:
			SPD_ERR("SDRAM - unsupported mode\n");
		}
		break;
	case 13:
		switch (col) {
		case 8:
			mode=5; /* mode 6 */
			break;
		case 9:
		case 10:
			if (read_spd(17) == 2)
				mode = 6; /* mode 7 */
			else
				mode = 2; /* mode 3 */
			break;
		case 11:
			mode = 2; /* mode 3 */
			break;
		default:
			SPD_ERR("SDRAM - unsupported mode\n");
		}
		break;
	default:
		SPD_ERR("SDRAM - unsupported mode\n");
	}

	/*------------------------------------------------------------------
	 * using the calculated values, compute the bank
	 * config register values.
	 * -------------------------------------------------------------------*/

	/* compute the size of each bank */
	bank_size = total_size / bank_cnt;
	/* convert bank size to bank size code for ppc4xx
	   by takeing log2(bank_size) - 22 */
	tmp = bank_size;		/* start with tmp = bank_size */
	bank_code = 0;			/* and bank_code = 0 */
	while (tmp > 1) {		/* this takes log2 of tmp */
		bank_code++;		/* and stores result in bank_code */
		tmp = tmp >> 1;
	}				/* bank_code is now log2(bank_size) */
	bank_code -= 22;		/* subtract 22 to get the code */

	tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
	sdram0_b0cr = (bank_size * 0) | tmp;
#ifndef CONFIG_405EP /* not on PPC405EP */
	if (bank_cnt > 1)
		sdram0_b2cr = (bank_size * 1) | tmp;
	if (bank_cnt > 2)
		sdram0_b1cr = (bank_size * 2) | tmp;
	if (bank_cnt > 3)
		sdram0_b3cr = (bank_size * 3) | tmp;
#else
	/* PPC405EP chip only supports two SDRAM banks */
	if (bank_cnt > 1)
		sdram0_b1cr = (bank_size * 1) | tmp;
	if (bank_cnt > 2)
		total_size = 2 * bank_size;
#endif

	/*
	 *   enable sdram controller DCE=1
	 *  enable burst read prefetch to 32 bytes BRPF=2
	 *  leave other functions off
	 */

	/*------------------------------------------------------------------
	 * now that we've done our calculations, we are ready to
	 * program all the registers.
	 * -------------------------------------------------------------------*/

	/* disable memcontroller so updates work */
	mtsdram(SDRAM0_CFG, 0);

#ifndef CONFIG_405EP /* not on PPC405EP */
	mtsdram(SDRAM0_BESR0, sdram0_besr0);
	mtsdram(SDRAM0_BESR1, sdram0_besr1);
	mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
	mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
#endif
	mtsdram(SDRAM0_RTR, sdram0_rtr);
	mtsdram(SDRAM0_PMIT, sdram0_pmit);
	mtsdram(SDRAM0_B0CR, sdram0_b0cr);
	mtsdram(SDRAM0_B1CR, sdram0_b1cr);
#ifndef CONFIG_405EP /* not on PPC405EP */
	mtsdram(SDRAM0_B2CR, sdram0_b2cr);
	mtsdram(SDRAM0_B3CR, sdram0_b3cr);
#endif
	mtsdram(SDRAM0_TR, sdram0_tr);

	/* SDRAM have a power on delay,	 500 micro should do */
	udelay(500);
	sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
#ifndef CONFIG_405EP /* not on PPC405EP */
	if (ecc_on)
		sdram0_cfg |= SDRAM0_CFG_MEMCHK;
#endif
	mtsdram(SDRAM0_CFG, sdram0_cfg);

	return (total_size);
}

int spd_read(uint addr)
{
	uchar data[2];

	if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
		return (int)data[0];
	else
		return 0;
}

#endif /* CONFIG_SPD_EEPROM */
Commit	Line	Data
36d830c9	1	/*
a47a12be	2	* arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
36d830c9 SR	3	* This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
	4	* SDRAM controller. Those are all current 405 PPC's.
	5	*
	6	* (C) Copyright 2001
	7	* Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
	8	*
	9	* Based on code by:
	10	*
	11	* Kenneth Johansson ,Ericsson AB.
	12	* kenneth.johansson@etx.ericsson.se
	13	*
	14	* hacked up by bill hunter. fixed so we could run before
	15	* serial_init and console_init. previous version avoided this by
	16	* running out of cache memory during serial/console init, then running
	17	* this code later.
	18	*
	19	* (C) Copyright 2002
	20	* Jun Gu, Artesyn Technology, jung@artesyncp.com
	21	* Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
	22	*
	23	* (C) Copyright 2005
	24	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	25	*
	26	* See file CREDITS for list of people who contributed to this
	27	* project.
	28	*
	29	* This program is free software; you can redistribute it and/or
	30	* modify it under the terms of the GNU General Public License as
	31	* published by the Free Software Foundation; either version 2 of
	32	* the License, or (at your option) any later version.
	33	*
	34	* This program is distributed in the hope that it will be useful,
	35	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	36	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	37	* GNU General Public License for more details.
	38	*
	39	* You should have received a copy of the GNU General Public License
	40	* along with this program; if not, write to the Free Software
	41	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	42	* MA 02111-1307 USA
	43	*/
	44
	45	#include <common.h>
	46	#include <asm/processor.h>
	47	#include <i2c.h>
b36df561	48	#include <asm/ppc4xx.h>
36d830c9 SR	49
	50	#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
	51
	52	/*
	53	* Set default values
	54	*/
36d830c9 SR	55	#define ONE_BILLION 1000000000
	56
	57	#define SDRAM0_CFG_DCE 0x80000000
	58	#define SDRAM0_CFG_SRE 0x40000000
	59	#define SDRAM0_CFG_PME 0x20000000
	60	#define SDRAM0_CFG_MEMCHK 0x10000000
	61	#define SDRAM0_CFG_REGEN 0x08000000
	62	#define SDRAM0_CFG_ECCDD 0x00400000
	63	#define SDRAM0_CFG_EMDULR 0x00200000
	64	#define SDRAM0_CFG_DRW_SHIFT (31-6)
	65	#define SDRAM0_CFG_BRPF_SHIFT (31-8)
	66
	67	#define SDRAM0_TR_CASL_SHIFT (31-8)
	68	#define SDRAM0_TR_PTA_SHIFT (31-13)
	69	#define SDRAM0_TR_CTP_SHIFT (31-15)
	70	#define SDRAM0_TR_LDF_SHIFT (31-17)
	71	#define SDRAM0_TR_RFTA_SHIFT (31-29)
	72	#define SDRAM0_TR_RCD_SHIFT (31-31)
	73
	74	#define SDRAM0_RTR_SHIFT (31-15)
	75	#define SDRAM0_ECCCFG_SHIFT (31-11)
	76
	77	/* SDRAM0_CFG enable macro */
	78	#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
	79
	80	#define SDRAM0_BXCR_SZ_MASK 0x000e0000
	81	#define SDRAM0_BXCR_AM_MASK 0x0000e000
	82
	83	#define SDRAM0_BXCR_SZ_SHIFT (31-14)
	84	#define SDRAM0_BXCR_AM_SHIFT (31-18)
	85
	86	#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
	87	#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
	88
	89	#ifdef CONFIG_SPDDRAM_SILENT
	90	# define SPD_ERR(x) do { return 0; } while (0)
	91	#else
	92	# define SPD_ERR(x) do { printf(x); return(0); } while (0)
	93	#endif
	94
	95	#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
	96
	97	/* function prototypes */
	98	int spd_read(uint addr);
	99
	100
	101	/*
	102	* This function is reading data from the DIMM module EEPROM over the SPD bus
	103	* and uses that to program the sdram controller.
	104	*
	105	* This works on boards that has the same schematics that the AMCC walnut has.
	106	*
	107	* Input: null for default I2C spd functions or a pointer to a custom function
	108	* returning spd_data.
	109	*/
	110
	111	long int spd_sdram(int(read_spd)(uint addr))
	112	{
	113	int tmp,row,col;
	114	int total_size,bank_size,bank_code;
36d830c9 SR	115	int mode;
	116	int bank_cnt;
	117
	118	int sdram0_pmit=0x07c00000;
4a127266 SR	119	int sdram0_b0cr;
4a127266 SR	120	int sdram0_b1cr = 0;
36d830c9	121	#ifndef CONFIG_405EP /* not on PPC405EP */
4a127266 SR	122	int sdram0_b2cr = 0;
4a127266 SR	123	int sdram0_b3cr = 0;
d0ff51ba WD	124	int sdram0_besr0 = -1;
	125	int sdram0_besr1 = -1;
	126	int sdram0_eccesr = -1;
36d830c9	127	int sdram0_ecccfg;
4a127266 SR	128	int ecc_on;
4a127266 SR	129	#endif
36d830c9 SR	130
	131	int sdram0_rtr=0;
	132	int sdram0_tr=0;
	133
36d830c9 SR	134	int sdram0_cfg=0;
	135
	136	int t_rp;
	137	int t_rcd;
	138	int t_ras;
	139	int t_rc;
	140	int min_cas;
	141
087dfdb7	142	PPC4xx_SYS_INFO sys_info;
36d830c9 SR	143	unsigned long bus_period_x_10;
	144
	145	/*
	146	* get the board info
	147	*/
	148	get_sys_info(&sys_info);
	149	bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
	150
	151	if (read_spd == 0){
	152	read_spd=spd_read;
	153	/*
	154	* Make sure I2C controller is initialized
	155	* before continuing.
	156	*/
880540de	157	i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
36d830c9 SR	158	}
	159
	160	/* Make shure we are using SDRAM */
	161	if (read_spd(2) != 0x04) {
	162	SPD_ERR("SDRAM - non SDRAM memory module found\n");
	163	}
	164
	165	/* ------------------------------------------------------------------
	166	* configure memory timing register
	167	*
	168	* data from DIMM:
	169	* 27 IN Row Precharge Time ( t RP)
	170	* 29 MIN RAS to CAS Delay ( t RCD)
	171	* 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
	172	* -------------------------------------------------------------------*/
	173
	174	/*
	175	* first figure out which cas latency mode to use
	176	* use the min supported mode
	177	*/
	178
	179	tmp = read_spd(127) & 0x6;
	180	if (tmp == 0x02) { /* only cas = 2 supported */
	181	min_cas = 2;
	182	/* t_ck = read_spd(9); */
	183	/* t_ac = read_spd(10); */
	184	} else if (tmp == 0x04) { /* only cas = 3 supported */
	185	min_cas = 3;
	186	/* t_ck = read_spd(9); */
	187	/* t_ac = read_spd(10); */
	188	} else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
	189	min_cas = 2;
	190	/* t_ck = read_spd(23); */
	191	/* t_ac = read_spd(24); */
	192	} else {
	193	SPD_ERR("SDRAM - unsupported CAS latency \n");
	194	}
	195
	196	/* get some timing values, t_rp,t_rcd,t_ras,t_rc
	197	*/
	198	t_rp = read_spd(27);
	199	t_rcd = read_spd(29);
	200	t_ras = read_spd(30);
	201	t_rc = t_ras + t_rp;
	202
	203	/* The following timing calcs subtract 1 before deviding.
	204	* this has effect of using ceiling instead of floor rounding,
	205	* and also subtracting 1 to convert number to reg value
	206	*/
	207	/* set up CASL */
	208	sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
	209	/* set up PTA */
	210	sdram0_tr \|= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
	211	/* set up CTP */
	212	tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
	213	if (tmp < 1)
	214	tmp = 1;
	215	sdram0_tr \|= tmp << SDRAM0_TR_CTP_SHIFT;
	216	/* set LDF = 2 cycles, reg value = 1 */
	217	sdram0_tr \|= 1 << SDRAM0_TR_LDF_SHIFT;
	218	/* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
	219	tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
	220	if (tmp < 0)
	221	tmp = 0;
222	if (tmp > 6)
223	tmp = 6;
224	sdram0_tr \|= tmp << SDRAM0_TR_RFTA_SHIFT;
225	/* set RCD = t_rcd/bus_period*/
226	sdram0_tr \|= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
227
228
229	/*------------------------------------------------------------------
230	* configure RTR register
231	* -------------------------------------------------------------------*/
232	row = read_spd(3);
233	col = read_spd(4);
234	tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
235	switch (tmp) {
236	case 0x00:
237	tmp = 15625;
238	break;
239	case 0x01:
240	tmp = 15625 / 4;
241	break;
242	case 0x02:
243	tmp = 15625 / 2;
244	break;
245	case 0x03:
246	tmp = 15625 * 2;
247	break;
248	case 0x04:
249	tmp = 15625 * 4;
250	break;
251	case 0x05:
252	tmp = 15625 * 8;
253	break;
254	default:
255	SPD_ERR("SDRAM - Bad refresh period \n");
256	}
257	/* convert from nsec to bus cycles */
258	tmp = (tmp * 10) / bus_period_x_10;
259	sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
260
261	/*------------------------------------------------------------------
262	* determine the number of banks used
263	* -------------------------------------------------------------------*/
264	/* byte 7:6 is module data width */
265	if (read_spd(7) != 0)
266	SPD_ERR("SDRAM - unsupported module width\n");
267	tmp = read_spd(6);
268	if (tmp < 32)
269	SPD_ERR("SDRAM - unsupported module width\n");
270	else if (tmp < 64)
271	bank_cnt = 1; /* one bank per sdram side */
272	else if (tmp < 73)
273	bank_cnt = 2; /* need two banks per side */
274	else if (tmp < 161)
275	bank_cnt = 4; /* need four banks per side */
276	else
277	SPD_ERR("SDRAM - unsupported module width\n");
278
279	/* byte 5 is the module row count (refered to as dimm "sides") */
280	tmp = read_spd(5);
281	if (tmp == 1)
282	;
283	else if (tmp==2)
284	bank_cnt *= 2;
285	else if (tmp==4)
286	bank_cnt *= 4;
287	else
288	bank_cnt = 8; /* 8 is an error code */
289
290	if (bank_cnt > 4) /* we only have 4 banks to work with */
291	SPD_ERR("SDRAM - unsupported module rows for this width\n");
292
4a127266	293	#ifndef CONFIG_405EP /* not on PPC405EP */
36d830c9 SR	294	/* now check for ECC ability of module. We only support ECC
	295	* on 32 bit wide devices with 8 bit ECC.
	296	*/
	297	if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
	298	sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
	299	ecc_on = 1;
	300	} else {
	301	sdram0_ecccfg = 0;
	302	ecc_on = 0;
	303	}
4a127266	304	#endif
36d830c9 SR	305
	306	/*------------------------------------------------------------------
	307	* calculate total size
	308	* -------------------------------------------------------------------*/
	309	/* calculate total size and do sanity check */
	310	tmp = read_spd(31);
	311	total_size = 1 << 22; /* total_size = 4MB */
	312	/* now multiply 4M by the smallest device row density */
	313	/* note that we don't support asymetric rows */
	314	while (((tmp & 0x0001) == 0) && (tmp != 0)) {
	315	total_size = total_size << 1;
	316	tmp = tmp >> 1;
	317	}
	318	total_size = read_spd(5); / mult by module rows (dimm sides) */
	319
	320	/*------------------------------------------------------------------
	321	* map rows * cols * banks to a mode
	322	* -------------------------------------------------------------------*/
	323
	324	switch (row) {
	325	case 11:
	326	switch (col) {
	327	case 8:
	328	mode=4; /* mode 5 */
	329	break;
	330	case 9:
	331	case 10:
	332	mode=0; /* mode 1 */
	333	break;
	334	default:
	335	SPD_ERR("SDRAM - unsupported mode\n");
	336	}
	337	break;
	338	case 12:
	339	switch (col) {
	340	case 8:
	341	mode=3; /* mode 4 */
	342	break;
	343	case 9:
	344	case 10:
	345	mode=1; /* mode 2 */
	346	break;
	347	default:
	348	SPD_ERR("SDRAM - unsupported mode\n");
	349	}
	350	break;
	351	case 13:
	352	switch (col) {
	353	case 8:
	354	mode=5; /* mode 6 */
	355	break;
	356	case 9:
	357	case 10:
	358	if (read_spd(17) == 2)
	359	mode = 6; /* mode 7 */
	360	else
	361	mode = 2; /* mode 3 */
	362	break;
	363	case 11:
	364	mode = 2; /* mode 3 */
	365	break;
	366	default:
	367	SPD_ERR("SDRAM - unsupported mode\n");
	368	}
369	break;
370	default:
371	SPD_ERR("SDRAM - unsupported mode\n");
372	}
373
374	/*------------------------------------------------------------------
375	* using the calculated values, compute the bank
376	* config register values.
377	* -------------------------------------------------------------------*/
36d830c9 SR	378
	379	/* compute the size of each bank */
	380	bank_size = total_size / bank_cnt;
	381	/* convert bank size to bank size code for ppc4xx
	382	by takeing log2(bank_size) - 22 */
	383	tmp = bank_size; /* start with tmp = bank_size */
	384	bank_code = 0; /* and bank_code = 0 */
	385	while (tmp > 1) { /* this takes log2 of tmp */
	386	bank_code++; /* and stores result in bank_code */
	387	tmp = tmp >> 1;
	388	} /* bank_code is now log2(bank_size) */
	389	bank_code -= 22; /* subtract 22 to get the code */
	390
	391	tmp = SDRAM0_BXCR_SZ(bank_code) \| SDRAM0_BXCR_AM(mode) \| 1;
	392	sdram0_b0cr = (bank_size * 0) \| tmp;
	393	#ifndef CONFIG_405EP /* not on PPC405EP */
	394	if (bank_cnt > 1)
	395	sdram0_b2cr = (bank_size * 1) \| tmp;
	396	if (bank_cnt > 2)
	397	sdram0_b1cr = (bank_size * 2) \| tmp;
	398	if (bank_cnt > 3)
	399	sdram0_b3cr = (bank_size * 3) \| tmp;
	400	#else
	401	/* PPC405EP chip only supports two SDRAM banks */
	402	if (bank_cnt > 1)
	403	sdram0_b1cr = (bank_size * 1) \| tmp;
	404	if (bank_cnt > 2)
	405	total_size = 2 * bank_size;
	406	#endif
	407
	408	/*
	409	* enable sdram controller DCE=1
	410	* enable burst read prefetch to 32 bytes BRPF=2
	411	* leave other functions off
	412	*/
	413
	414	/*------------------------------------------------------------------
	415	* now that we've done our calculations, we are ready to
	416	* program all the registers.
	417	* -------------------------------------------------------------------*/
	418
36d830c9	419	/* disable memcontroller so updates work */
b306db2f	420	mtsdram(SDRAM0_CFG, 0);
36d830c9 SR	421
36d830c9 SR	422	#ifndef CONFIG_405EP /* not on PPC405EP */
b306db2f SR	423	mtsdram(SDRAM0_BESR0, sdram0_besr0);
	424	mtsdram(SDRAM0_BESR1, sdram0_besr1);
	425	mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
	426	mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
36d830c9	427	#endif
b306db2f SR	428	mtsdram(SDRAM0_RTR, sdram0_rtr);
	429	mtsdram(SDRAM0_PMIT, sdram0_pmit);
	430	mtsdram(SDRAM0_B0CR, sdram0_b0cr);
	431	mtsdram(SDRAM0_B1CR, sdram0_b1cr);
36d830c9	432	#ifndef CONFIG_405EP /* not on PPC405EP */
b306db2f SR	433	mtsdram(SDRAM0_B2CR, sdram0_b2cr);
b306db2f SR	434	mtsdram(SDRAM0_B3CR, sdram0_b3cr);
36d830c9	435	#endif
b306db2f	436	mtsdram(SDRAM0_TR, sdram0_tr);
36d830c9 SR	437
	438	/* SDRAM have a power on delay, 500 micro should do */
	439	udelay(500);
	440	sdram0_cfg = SDRAM0_CFG_DCE \| SDRAM0_CFG_BRPF(1) \| SDRAM0_CFG_ECCDD \| SDRAM0_CFG_EMDULR;
4a127266	441	#ifndef CONFIG_405EP /* not on PPC405EP */
36d830c9 SR	442	if (ecc_on)
36d830c9 SR	443	sdram0_cfg \|= SDRAM0_CFG_MEMCHK;
4a127266	444	#endif
b306db2f	445	mtsdram(SDRAM0_CFG, sdram0_cfg);
36d830c9 SR	446
	447	return (total_size);
	448	}
	449
	450	int spd_read(uint addr)
	451	{
	452	uchar data[2];
	453
	454	if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
	455	return (int)data[0];
	456	else
	457	return 0;
	458	}
	459
	460	#endif /* CONFIG_SPD_EEPROM */