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Fix incorrect array size of phy settings for 405EX
[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / 44x_spd_ddr2.c
CommitLineData
4037ed3b 1/*
a47a12be 2 * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
4037ed3b 3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
ea9202a6
SR		 4 * DDR2 controller (non Denali Core). Those currently are:
5 *
c821b5f1 6 * 405: 405EX(r)
ea9202a6 7 * 440/460: 440SP/440SPe/460EX/460GT
4037ed3b 8 *
c821b5f1
GE		 9 * Copyright (c) 2008 Nuovation System Designs, LLC
10 * Grant Erickson <gerickson@nuovations.com>
11
fb95169e 12 * (C) Copyright 2007-2009
4037ed3b
SR		 13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
14 *
15 * COPYRIGHT AMCC CORPORATION 2004
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 *
35 */
36
37/* define DEBUG for debugging output (obviously ;-)) */
38#if 0
39#define DEBUG
40#endif
41
42#include <common.h>
ba58e4c9 43#include <command.h>
b36df561 44#include <asm/ppc4xx.h>
4037ed3b
SR		 45#include <i2c.h>
46#include <asm/io.h>
47#include <asm/processor.h>
48#include <asm/mmu.h>
85ad184b 49#include <asm/cache.h>
4037ed3b 50
fb95169e
SR		 51#include "ecc.h"
52
08250eb2
SR		 53#define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic) \
54 do { \
55 u32 data; \
56 mfsdram(SDRAM_##mnemonic, data); \
57 printf("%20s[%02x] = 0x%08X\n", \
58 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
59 } while (0)
60
48e2b535
FR		 61#define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic) \
62 do { \
63 u32 data; \
64 data = mfdcr(SDRAM_##mnemonic); \
65 printf("%20s[%02x] = 0x%08X\n", \
66 "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
67 } while (0)
68
e9c020df
SR		 69#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
70static void update_rdcc(void)
71{
72 u32 val;
73
74 /*
75 * Complete RDSS configuration as mentioned on page 7 of the AMCC
76 * PowerPC440SP/SPe DDR2 application note:
77 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
78 *
79 * Or item #10 "10. Complete RDSS configuration" in chapter
80 * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
81 * manual.
82 */
83 mfsdram(SDRAM_RTSR, val);
84 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
85 mfsdram(SDRAM_RDCC, val);
86 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
87 val += 0x40000000;
88 mtsdram(SDRAM_RDCC, val);
89 }
90 }
91}
92#endif
93
59217bae
AG		 94#if defined(CONFIG_440)
95/*
96 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
97 * memory region. Right now the cache should still be disabled in U-Boot
98 * because of the EMAC driver, that need its buffer descriptor to be located
99 * in non cached memory.
100 *
101 * If at some time this restriction doesn't apply anymore, just define
102 * CONFIG_4xx_DCACHE in the board config file and this code should setup
103 * everything correctly.
104 */
105#ifdef CONFIG_4xx_DCACHE
106/* enable caching on SDRAM */
107#define MY_TLB_WORD2_I_ENABLE 0
108#else
109/* disable caching on SDRAM */
110#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE
111#endif /* CONFIG_4xx_DCACHE */
d24bd251
FR		 112
113void dcbz_area(u32 start_address, u32 num_bytes);
59217bae
AG		 114#endif /* CONFIG_440 */
115
d24bd251
FR		 116#define MAXRANKS 4
117#define MAXBXCF 4
118
119#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
120
fb95169e 121#if !defined(CONFIG_NAND_SPL)
d24bd251
FR		 122/*-----------------------------------------------------------------------------+
123 * sdram_memsize
124 *-----------------------------------------------------------------------------*/
fb95169e 125phys_size_t sdram_memsize(void)
d24bd251
FR		 126{
127 phys_size_t mem_size;
128 unsigned long mcopt2;
129 unsigned long mcstat;
130 unsigned long mb0cf;
131 unsigned long sdsz;
132 unsigned long i;
133
134 mem_size = 0;
135
136 mfsdram(SDRAM_MCOPT2, mcopt2);
137 mfsdram(SDRAM_MCSTAT, mcstat);
138
139 /* DDR controller must be enabled and not in self-refresh. */
140 /* Otherwise memsize is zero. */
141 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
142 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
143 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
144 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
145 for (i = 0; i < MAXBXCF; i++) {
146 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
147 /* Banks enabled */
148 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
149#if defined(CONFIG_440)
150 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
151#else
152 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
153#endif
154 switch(sdsz) {
155 case SDRAM_RXBAS_SDSZ_8:
156 mem_size+=8;
157 break;
158 case SDRAM_RXBAS_SDSZ_16:
159 mem_size+=16;
160 break;
161 case SDRAM_RXBAS_SDSZ_32:
162 mem_size+=32;
163 break;
164 case SDRAM_RXBAS_SDSZ_64:
165 mem_size+=64;
166 break;
167 case SDRAM_RXBAS_SDSZ_128:
168 mem_size+=128;
169 break;
170 case SDRAM_RXBAS_SDSZ_256:
171 mem_size+=256;
172 break;
173 case SDRAM_RXBAS_SDSZ_512:
174 mem_size+=512;
175 break;
176 case SDRAM_RXBAS_SDSZ_1024:
177 mem_size+=1024;
178 break;
179 case SDRAM_RXBAS_SDSZ_2048:
180 mem_size+=2048;
181 break;
182 case SDRAM_RXBAS_SDSZ_4096:
183 mem_size+=4096;
184 break;
185 default:
186 printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
187 , sdsz);
188 mem_size=0;
189 break;
190 }
191 }
192 }
193 }
194
195 return mem_size << 20;
196}
197
fb95169e
SR		 198/*-----------------------------------------------------------------------------+
199 * is_ecc_enabled
200 *-----------------------------------------------------------------------------*/
201static unsigned long is_ecc_enabled(void)
202{
203 unsigned long val;
204
205 mfsdram(SDRAM_MCOPT1, val);
206
207 return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
208}
209
d24bd251
FR		 210/*-----------------------------------------------------------------------------+
211 * board_add_ram_info
212 *-----------------------------------------------------------------------------*/
213void board_add_ram_info(int use_default)
214{
215 PPC4xx_SYS_INFO board_cfg;
216 u32 val;
217
218 if (is_ecc_enabled())
219 puts(" (ECC");
220 else
221 puts(" (ECC not");
222
223 get_sys_info(&board_cfg);
224
fb95169e
SR		 225#if defined(CONFIG_405EX)
226 val = board_cfg.freqPLB;
227#else
d24bd251
FR		 228 mfsdr(SDR0_DDR0, val);
229 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
d24bd251
FR		 230#endif
231 printf(" enabled, %d MHz", (val * 2) / 1000000);
232
233 mfsdram(SDRAM_MMODE, val);
234 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
235 printf(", CL%d)", val);
236}
fb95169e 237#endif /* !CONFIG_NAND_SPL */
d24bd251 238
08250eb2 239#if defined(CONFIG_SPD_EEPROM)
4037ed3b 240
ba58e4c9
SR		 241/*-----------------------------------------------------------------------------+
242 * Defines
243 *-----------------------------------------------------------------------------*/
4037ed3b 244#ifndef TRUE
74357114 245#define TRUE 1
4037ed3b
SR		 246#endif
247#ifndef FALSE
74357114 248#define FALSE 0
4037ed3b
SR		 249#endif
250
251#define SDRAM_DDR1 1
252#define SDRAM_DDR2 2
253#define SDRAM_NONE 0
254
1636d1c8 255#define MAXDIMMS 2
4037ed3b
SR		 256#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
257
258#define ONE_BILLION 1000000000
259
ba58e4c9
SR		 260#define CMD_NOP (7 << 19)
261#define CMD_PRECHARGE (2 << 19)
262#define CMD_REFRESH (1 << 19)
263#define CMD_EMR (0 << 19)
264#define CMD_READ (5 << 19)
265#define CMD_WRITE (4 << 19)
266
267#define SELECT_MR (0 << 16)
268#define SELECT_EMR (1 << 16)
269#define SELECT_EMR2 (2 << 16)
270#define SELECT_EMR3 (3 << 16)
271
272/* MR */
273#define DLL_RESET 0x00000100
274
275#define WRITE_RECOV_2 (1 << 9)
276#define WRITE_RECOV_3 (2 << 9)
277#define WRITE_RECOV_4 (3 << 9)
278#define WRITE_RECOV_5 (4 << 9)
279#define WRITE_RECOV_6 (5 << 9)
280
281#define BURST_LEN_4 0x00000002
282
283/* EMR */
284#define ODT_0_OHM 0x00000000
285#define ODT_50_OHM 0x00000044
286#define ODT_75_OHM 0x00000004
287#define ODT_150_OHM 0x00000040
288
289#define ODS_FULL 0x00000000
290#define ODS_REDUCED 0x00000002
04737d5f 291#define OCD_CALIB_DEF 0x00000380
ba58e4c9
SR		 292
293/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
294#define ODT_EB0R (0x80000000 >> 8)
295#define ODT_EB0W (0x80000000 >> 7)
296#define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
297#define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
298#define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
4037ed3b 299
4037ed3b 300/* Defines for the Read Cycle Delay test */
94f54703
SR		 301#define NUMMEMTESTS 8
302#define NUMMEMWORDS 8
6ed14add 303#define NUMLOOPS 64 /* memory test loops */
4037ed3b 304
5d812b8b
SR		 305/*
306 * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
307 * To support such configurations, we "only" map the first 2GB via the TLB's. We
308 * need some free virtual address space for the remaining peripherals like, SoC
309 * devices, FLASH etc.
310 *
311 * Note that ECC is currently not supported on configurations with more than 2GB
312 * SDRAM. This is because we only map the first 2GB on such systems, and therefore
313 * the ECC parity byte of the remaining area can't be written.
314 */
5d812b8b 315
a5d71e29
HS		 316/*
317 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
318 */
319void __spd_ddr_init_hang (void)
320{
321 hang ();
322}
323void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
324
6ed14add
SR		 325/*
326 * To provide an interface for board specific config values in this common
327 * DDR setup code, we implement he "weak" default functions here. They return
328 * the default value back to the caller.
329 *
330 * Please see include/configs/yucca.h for an example fora board specific
331 * implementation.
332 */
333u32 __ddr_wrdtr(u32 default_val)
334{
335 return default_val;
336}
337u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
338
339u32 __ddr_clktr(u32 default_val)
340{
341 return default_val;
342}
343u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
344
566a494f 345
4037ed3b
SR		 346/* Private Structure Definitions */
347
348/* enum only to ease code for cas latency setting */
349typedef enum ddr_cas_id {
350 DDR_CAS_2 = 20,
351 DDR_CAS_2_5 = 25,
352 DDR_CAS_3 = 30,
353 DDR_CAS_4 = 40,
354 DDR_CAS_5 = 50
355} ddr_cas_id_t;
356
357/*-----------------------------------------------------------------------------+
358 * Prototypes
359 *-----------------------------------------------------------------------------*/
4037ed3b
SR		 360static void get_spd_info(unsigned long *dimm_populated,
361 unsigned char *iic0_dimm_addr,
362 unsigned long num_dimm_banks);
363static void check_mem_type(unsigned long *dimm_populated,
364 unsigned char *iic0_dimm_addr,
365 unsigned long num_dimm_banks);
366static void check_frequency(unsigned long *dimm_populated,
367 unsigned char *iic0_dimm_addr,
368 unsigned long num_dimm_banks);
369static void check_rank_number(unsigned long *dimm_populated,
370 unsigned char *iic0_dimm_addr,
371 unsigned long num_dimm_banks);
372static void check_voltage_type(unsigned long *dimm_populated,
373 unsigned char *iic0_dimm_addr,
374 unsigned long num_dimm_banks);
375static void program_memory_queue(unsigned long *dimm_populated,
376 unsigned char *iic0_dimm_addr,
377 unsigned long num_dimm_banks);
378static void program_codt(unsigned long *dimm_populated,
379 unsigned char *iic0_dimm_addr,
380 unsigned long num_dimm_banks);
381static void program_mode(unsigned long *dimm_populated,
382 unsigned char *iic0_dimm_addr,
383 unsigned long num_dimm_banks,
ad5bb451
WD		 384 ddr_cas_id_t *selected_cas,
385 int *write_recovery);
4037ed3b
SR		 386static void program_tr(unsigned long *dimm_populated,
387 unsigned char *iic0_dimm_addr,
388 unsigned long num_dimm_banks);
389static void program_rtr(unsigned long *dimm_populated,
390 unsigned char *iic0_dimm_addr,
391 unsigned long num_dimm_banks);
392static void program_bxcf(unsigned long *dimm_populated,
393 unsigned char *iic0_dimm_addr,
394 unsigned long num_dimm_banks);
395static void program_copt1(unsigned long *dimm_populated,
396 unsigned char *iic0_dimm_addr,
397 unsigned long num_dimm_banks);
398static void program_initplr(unsigned long *dimm_populated,
399 unsigned char *iic0_dimm_addr,
400 unsigned long num_dimm_banks,
ad5bb451 401 ddr_cas_id_t selected_cas,
ba58e4c9 402 int write_recovery);
df294497 403#ifdef CONFIG_DDR_ECC
4037ed3b
SR		 404static void program_ecc(unsigned long *dimm_populated,
405 unsigned char *iic0_dimm_addr,
ba58e4c9
SR		 406 unsigned long num_dimm_banks,
407 unsigned long tlb_word2_i_value);
df294497 408#endif
f6b6c458 409#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
ba58e4c9 410static void program_DQS_calibration(unsigned long *dimm_populated,
f6b6c458
AG		 411 unsigned char *iic0_dimm_addr,
412 unsigned long num_dimm_banks);
4037ed3b 413#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
74357114 414static void test(void);
4037ed3b 415#else
74357114 416static void DQS_calibration_process(void);
4037ed3b 417#endif
f6b6c458 418#endif
4037ed3b 419
4037ed3b
SR		 420static unsigned char spd_read(uchar chip, uint addr)
421{
422 unsigned char data[2];
423
424 if (i2c_probe(chip) == 0)
425 if (i2c_read(chip, addr, 1, data, 1) == 0)
426 return data[0];
427
428 return 0;
429}
430
4037ed3b
SR		 431/*-----------------------------------------------------------------------------+
432 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
433 * Note: This routine runs from flash with a stack set up in the chip's
434 * sram space. It is important that the routine does not require .sbss, .bss or
435 * .data sections. It also cannot call routines that require these sections.
436 *-----------------------------------------------------------------------------*/
437/*-----------------------------------------------------------------------------
74357114 438 * Function: initdram
4037ed3b 439 * Description: Configures SDRAM memory banks for DDR operation.
74357114
WD		 440 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
441 * via the IIC bus and then configures the DDR SDRAM memory
442 * banks appropriately. If Auto Memory Configuration is
443 * not used, it is assumed that no DIMM is plugged
4037ed3b 444 *-----------------------------------------------------------------------------*/
9973e3c6 445phys_size_t initdram(int board_type)
4037ed3b 446{
ba58e4c9 447 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
4037ed3b
SR		 448 unsigned char spd0[MAX_SPD_BYTES];
449 unsigned char spd1[MAX_SPD_BYTES];
450 unsigned char *dimm_spd[MAXDIMMS];
33c8c664 451 unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
9adfc9fb 452 unsigned long num_dimm_banks; /* on board dimm banks */
4037ed3b 453 unsigned long val;
9adfc9fb 454 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
ba58e4c9 455 int write_recovery;
5d812b8b 456 phys_size_t dram_size = 0;
4037ed3b
SR		 457
458 num_dimm_banks = sizeof(iic0_dimm_addr);
459
460 /*------------------------------------------------------------------
461 * Set up an array of SPD matrixes.
462 *-----------------------------------------------------------------*/
463 dimm_spd[0] = spd0;
464 dimm_spd[1] = spd1;
465
4037ed3b
SR		 466 /*------------------------------------------------------------------
467 * Reset the DDR-SDRAM controller.
468 *-----------------------------------------------------------------*/
5e7abce9 469 mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
4037ed3b
SR		 470 mtsdr(SDR0_SRST, 0x00000000);
471
472 /*
473 * Make sure I2C controller is initialized
474 * before continuing.
475 */
476
477 /* switch to correct I2C bus */
6d0f6bcf
JCPV		 478 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
479 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
4037ed3b
SR		 480
481 /*------------------------------------------------------------------
482 * Clear out the serial presence detect buffers.
483 * Perform IIC reads from the dimm. Fill in the spds.
484 * Check to see if the dimm slots are populated
485 *-----------------------------------------------------------------*/
486 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
487
488 /*------------------------------------------------------------------
489 * Check the memory type for the dimms plugged.
490 *-----------------------------------------------------------------*/
491 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
492
493 /*------------------------------------------------------------------
494 * Check the frequency supported for the dimms plugged.
495 *-----------------------------------------------------------------*/
496 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
497
498 /*------------------------------------------------------------------
499 * Check the total rank number.
500 *-----------------------------------------------------------------*/
501 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
502
503 /*------------------------------------------------------------------
504 * Check the voltage type for the dimms plugged.
505 *-----------------------------------------------------------------*/
506 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
507
508 /*------------------------------------------------------------------
509 * Program SDRAM controller options 2 register
510 * Except Enabling of the memory controller.
511 *-----------------------------------------------------------------*/
512 mfsdram(SDRAM_MCOPT2, val);
513 mtsdram(SDRAM_MCOPT2,
514 (val &
515 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
516 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
517 SDRAM_MCOPT2_ISIE_MASK))
518 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
519 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
520 SDRAM_MCOPT2_ISIE_ENABLE));
521
522 /*------------------------------------------------------------------
523 * Program SDRAM controller options 1 register
524 * Note: Does not enable the memory controller.
525 *-----------------------------------------------------------------*/
526 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
527
528 /*------------------------------------------------------------------
529 * Set the SDRAM Controller On Die Termination Register
530 *-----------------------------------------------------------------*/
531 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
532
533 /*------------------------------------------------------------------
534 * Program SDRAM refresh register.
535 *-----------------------------------------------------------------*/
536 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
537
538 /*------------------------------------------------------------------
539 * Program SDRAM mode register.
540 *-----------------------------------------------------------------*/
ba58e4c9
SR		 541 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
542 &selected_cas, &write_recovery);
4037ed3b
SR		 543
544 /*------------------------------------------------------------------
545 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
546 *-----------------------------------------------------------------*/
547 mfsdram(SDRAM_WRDTR, val);
548 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
6ed14add 549 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
4037ed3b
SR		 550
551 /*------------------------------------------------------------------
552 * Set the SDRAM Clock Timing Register
553 *-----------------------------------------------------------------*/
554 mfsdram(SDRAM_CLKTR, val);
6ed14add
SR		 555 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
556 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
4037ed3b
SR		 557
558 /*------------------------------------------------------------------
559 * Program the BxCF registers.
560 *-----------------------------------------------------------------*/
561 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
562
563 /*------------------------------------------------------------------
564 * Program SDRAM timing registers.
565 *-----------------------------------------------------------------*/
566 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
567
568 /*------------------------------------------------------------------
569 * Set the Extended Mode register
570 *-----------------------------------------------------------------*/
571 mfsdram(SDRAM_MEMODE, val);
572 mtsdram(SDRAM_MEMODE,
573 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
574 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
575 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
df294497 576 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
4037ed3b
SR		 577
578 /*------------------------------------------------------------------
579 * Program Initialization preload registers.
580 *-----------------------------------------------------------------*/
581 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
ba58e4c9 582 selected_cas, write_recovery);
4037ed3b
SR		 583
584 /*------------------------------------------------------------------
585 * Delay to ensure 200usec have elapsed since reset.
586 *-----------------------------------------------------------------*/
587 udelay(400);
588
589 /*------------------------------------------------------------------
590 * Set the memory queue core base addr.
591 *-----------------------------------------------------------------*/
592 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
593
594 /*------------------------------------------------------------------
595 * Program SDRAM controller options 2 register
596 * Enable the memory controller.
597 *-----------------------------------------------------------------*/
598 mfsdram(SDRAM_MCOPT2, val);
599 mtsdram(SDRAM_MCOPT2,
600 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
601 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
04737d5f 602 SDRAM_MCOPT2_IPTR_EXECUTE);
4037ed3b
SR		 603
604 /*------------------------------------------------------------------
04737d5f 605 * Wait for IPTR_EXECUTE init sequence to complete.
4037ed3b
SR		 606 *-----------------------------------------------------------------*/
607 do {
608 mfsdram(SDRAM_MCSTAT, val);
609 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
610
04737d5f
PH		 611 /* enable the controller only after init sequence completes */
612 mfsdram(SDRAM_MCOPT2, val);
613 mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
614
615 /* Make sure delay-line calibration is done before proceeding */
616 do {
617 mfsdram(SDRAM_DLCR, val);
618 } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
619
4037ed3b
SR		 620 /* get installed memory size */
621 dram_size = sdram_memsize();
622
5d812b8b
SR		 623 /*
624 * Limit size to 2GB
625 */
626 if (dram_size > CONFIG_MAX_MEM_MAPPED)
627 dram_size = CONFIG_MAX_MEM_MAPPED;
628
4037ed3b 629 /* and program tlb entries for this size (dynamic) */
6ed14add
SR		 630
631 /*
632 * Program TLB entries with caches enabled, for best performace
633 * while auto-calibrating and ECC generation
634 */
635 program_tlb(0, 0, dram_size, 0);
4037ed3b 636
4037ed3b 637 /*------------------------------------------------------------------
ba58e4c9 638 * DQS calibration.
4037ed3b 639 *-----------------------------------------------------------------*/
f6b6c458
AG		 640#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
641 DQS_autocalibration();
642#else
ba58e4c9 643 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
f6b6c458 644#endif
e9c020df
SR		 645 /*
646 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
647 * PowerPC440SP/SPe DDR2 application note:
648 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
649 */
650 update_rdcc();
4037ed3b 651
df294497 652#ifdef CONFIG_DDR_ECC
4037ed3b 653 /*------------------------------------------------------------------
ba58e4c9 654 * If ecc is enabled, initialize the parity bits.
4037ed3b 655 *-----------------------------------------------------------------*/
6ed14add 656 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
df294497 657#endif
4037ed3b 658
6ed14add
SR		 659 /*
660 * Now after initialization (auto-calibration and ECC generation)
661 * remove the TLB entries with caches enabled and program again with
662 * desired cache functionality
663 */
664 remove_tlb(0, dram_size);
665 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
666
2e205084 667 ppc4xx_ibm_ddr2_register_dump();
4037ed3b 668
8ac41e3e
SR		 669 /*
670 * Clear potential errors resulting from auto-calibration.
671 * If not done, then we could get an interrupt later on when
672 * exceptions are enabled.
673 */
674 set_mcsr(get_mcsr());
675
5d812b8b 676 return sdram_memsize();
4037ed3b
SR		 677}
678
679static void get_spd_info(unsigned long *dimm_populated,
680 unsigned char *iic0_dimm_addr,
681 unsigned long num_dimm_banks)
682{
683 unsigned long dimm_num;
684 unsigned long dimm_found;
685 unsigned char num_of_bytes;
686 unsigned char total_size;
687
688 dimm_found = FALSE;
689 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
690 num_of_bytes = 0;
691 total_size = 0;
692
693 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
694 debug("\nspd_read(0x%x) returned %d\n",
695 iic0_dimm_addr[dimm_num], num_of_bytes);
696 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
697 debug("spd_read(0x%x) returned %d\n",
698 iic0_dimm_addr[dimm_num], total_size);
699
700 if ((num_of_bytes != 0) && (total_size != 0)) {
701 dimm_populated[dimm_num] = TRUE;
702 dimm_found = TRUE;
703 debug("DIMM slot %lu: populated\n", dimm_num);
704 } else {
705 dimm_populated[dimm_num] = FALSE;
706 debug("DIMM slot %lu: Not populated\n", dimm_num);
707 }
708 }
709
710 if (dimm_found == FALSE) {
711 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
a5d71e29 712 spd_ddr_init_hang ();
4037ed3b
SR		 713 }
714}
715
4037ed3b
SR		 716
717/*------------------------------------------------------------------
718 * For the memory DIMMs installed, this routine verifies that they
719 * really are DDR specific DIMMs.
720 *-----------------------------------------------------------------*/
721static void check_mem_type(unsigned long *dimm_populated,
722 unsigned char *iic0_dimm_addr,
723 unsigned long num_dimm_banks)
724{
725 unsigned long dimm_num;
726 unsigned long dimm_type;
727
728 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
729 if (dimm_populated[dimm_num] == TRUE) {
730 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
731 switch (dimm_type) {
732 case 1:
733 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
734 "slot %d.\n", (unsigned int)dimm_num);
735 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
736 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 737 spd_ddr_init_hang ();
4037ed3b
SR		 738 break;
739 case 2:
740 printf("ERROR: EDO DIMM detected in slot %d.\n",
741 (unsigned int)dimm_num);
742 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
743 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 744 spd_ddr_init_hang ();
4037ed3b
SR		 745 break;
746 case 3:
747 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
748 (unsigned int)dimm_num);
749 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
750 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 751 spd_ddr_init_hang ();
4037ed3b
SR		 752 break;
753 case 4:
754 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
755 (unsigned int)dimm_num);
756 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
757 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 758 spd_ddr_init_hang ();
4037ed3b
SR		 759 break;
760 case 5:
761 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
762 (unsigned int)dimm_num);
763 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
764 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 765 spd_ddr_init_hang ();
4037ed3b
SR		 766 break;
767 case 6:
768 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
769 (unsigned int)dimm_num);
770 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
771 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 772 spd_ddr_init_hang ();
4037ed3b
SR		 773 break;
774 case 7:
48e2b535 775 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
4037ed3b
SR		 776 dimm_populated[dimm_num] = SDRAM_DDR1;
777 break;
778 case 8:
48e2b535 779 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
4037ed3b
SR		 780 dimm_populated[dimm_num] = SDRAM_DDR2;
781 break;
782 default:
783 printf("ERROR: Unknown DIMM detected in slot %d.\n",
784 (unsigned int)dimm_num);
785 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
786 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 787 spd_ddr_init_hang ();
4037ed3b
SR		 788 break;
789 }
790 }
791 }
792 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
793 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
794 && (dimm_populated[dimm_num] != SDRAM_NONE)
795 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
796 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
a5d71e29 797 spd_ddr_init_hang ();
4037ed3b
SR		 798 }
799 }
800}
801
802/*------------------------------------------------------------------
803 * For the memory DIMMs installed, this routine verifies that
804 * frequency previously calculated is supported.
805 *-----------------------------------------------------------------*/
806static void check_frequency(unsigned long *dimm_populated,
807 unsigned char *iic0_dimm_addr,
808 unsigned long num_dimm_banks)
809{
810 unsigned long dimm_num;
811 unsigned long tcyc_reg;
812 unsigned long cycle_time;
813 unsigned long calc_cycle_time;
814 unsigned long sdram_freq;
815 unsigned long sdr_ddrpll;
087dfdb7 816 PPC4xx_SYS_INFO board_cfg;
4037ed3b
SR		 817
818 /*------------------------------------------------------------------
819 * Get the board configuration info.
820 *-----------------------------------------------------------------*/
821 get_sys_info(&board_cfg);
822
df294497 823 mfsdr(SDR0_DDR0, sdr_ddrpll);
4037ed3b
SR		 824 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
825
826 /*
827 * calc_cycle_time is calculated from DDR frequency set by board/chip
828 * and is expressed in multiple of 10 picoseconds
829 * to match the way DIMM cycle time is calculated below.
830 */
831 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
832
833 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
834 if (dimm_populated[dimm_num] != SDRAM_NONE) {
835 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
836 /*
837 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
838 * the higher order nibble (bits 4-7) designates the cycle time
839 * to a granularity of 1ns;
840 * the value presented by the lower order nibble (bits 0-3)
841 * has a granularity of .1ns and is added to the value designated
842 * by the higher nibble. In addition, four lines of the lower order
843 * nibble are assigned to support +.25,+.33, +.66 and +.75.
844 */
845 /* Convert from hex to decimal */
846 if ((tcyc_reg & 0x0F) == 0x0D)
847 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
848 else if ((tcyc_reg & 0x0F) == 0x0C)
849 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
850 else if ((tcyc_reg & 0x0F) == 0x0B)
851 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
852 else if ((tcyc_reg & 0x0F) == 0x0A)
853 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
854 else
855 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
856 ((tcyc_reg & 0x0F)*10);
48e2b535 857 debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
4037ed3b
SR		 858
859 if (cycle_time > (calc_cycle_time + 10)) {
860 /*
861 * the provided sdram cycle_time is too small
862 * for the available DIMM cycle_time.
863 * The additionnal 100ps is here to accept a small incertainty.
864 */
865 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
866 "slot %d \n while calculated cycle time is %d ps.\n",
867 (unsigned int)(cycle_time*10),
868 (unsigned int)dimm_num,
869 (unsigned int)(calc_cycle_time*10));
870 printf("Replace the DIMM, or change DDR frequency via "
871 "strapping bits.\n\n");
a5d71e29 872 spd_ddr_init_hang ();
4037ed3b
SR		 873 }
874 }
875 }
876}
877
878/*------------------------------------------------------------------
879 * For the memory DIMMs installed, this routine verifies two
880 * ranks/banks maximum are availables.
881 *-----------------------------------------------------------------*/
882static void check_rank_number(unsigned long *dimm_populated,
883 unsigned char *iic0_dimm_addr,
884 unsigned long num_dimm_banks)
885{
886 unsigned long dimm_num;
887 unsigned long dimm_rank;
888 unsigned long total_rank = 0;
889
890 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
891 if (dimm_populated[dimm_num] != SDRAM_NONE) {
892 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
893 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
894 dimm_rank = (dimm_rank & 0x0F) +1;
895 else
896 dimm_rank = dimm_rank & 0x0F;
897
898
899 if (dimm_rank > MAXRANKS) {
b002144e
SR		 900 printf("ERROR: DRAM DIMM detected with %lu ranks in "
901 "slot %lu is not supported.\n", dimm_rank, dimm_num);
4037ed3b
SR		 902 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
903 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 904 spd_ddr_init_hang ();
4037ed3b
SR		 905 } else
906 total_rank += dimm_rank;
907 }
908 if (total_rank > MAXRANKS) {
909 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
910 "for all slots.\n", (unsigned int)total_rank);
911 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
912 printf("Remove one of the DIMM modules.\n\n");
a5d71e29 913 spd_ddr_init_hang ();
4037ed3b
SR		 914 }
915 }
916}
917
918/*------------------------------------------------------------------
919 * only support 2.5V modules.
920 * This routine verifies this.
921 *-----------------------------------------------------------------*/
922static void check_voltage_type(unsigned long *dimm_populated,
923 unsigned char *iic0_dimm_addr,
924 unsigned long num_dimm_banks)
925{
926 unsigned long dimm_num;
927 unsigned long voltage_type;
928
929 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
930 if (dimm_populated[dimm_num] != SDRAM_NONE) {
931 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
932 switch (voltage_type) {
933 case 0x00:
934 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
935 printf("This DIMM is 5.0 Volt/TTL.\n");
936 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
937 (unsigned int)dimm_num);
a5d71e29 938 spd_ddr_init_hang ();
4037ed3b
SR		 939 break;
940 case 0x01:
941 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
942 printf("This DIMM is LVTTL.\n");
943 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
944 (unsigned int)dimm_num);
a5d71e29 945 spd_ddr_init_hang ();
4037ed3b
SR		 946 break;
947 case 0x02:
948 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
949 printf("This DIMM is 1.5 Volt.\n");
950 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
951 (unsigned int)dimm_num);
a5d71e29 952 spd_ddr_init_hang ();
4037ed3b
SR		 953 break;
954 case 0x03:
955 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
956 printf("This DIMM is 3.3 Volt/TTL.\n");
957 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
958 (unsigned int)dimm_num);
a5d71e29 959 spd_ddr_init_hang ();
4037ed3b
SR		 960 break;
961 case 0x04:
962 /* 2.5 Voltage only for DDR1 */
963 break;
964 case 0x05:
965 /* 1.8 Voltage only for DDR2 */
966 break;
967 default:
968 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
969 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
970 (unsigned int)dimm_num);
a5d71e29 971 spd_ddr_init_hang ();
4037ed3b
SR		 972 break;
973 }
974 }
975 }
976}
977
978/*-----------------------------------------------------------------------------+
979 * program_copt1.
980 *-----------------------------------------------------------------------------*/
981static void program_copt1(unsigned long *dimm_populated,
982 unsigned char *iic0_dimm_addr,
983 unsigned long num_dimm_banks)
984{
985 unsigned long dimm_num;
986 unsigned long mcopt1;
987 unsigned long ecc_enabled;
988 unsigned long ecc = 0;
989 unsigned long data_width = 0;
990 unsigned long dimm_32bit;
991 unsigned long dimm_64bit;
992 unsigned long registered = 0;
993 unsigned long attribute = 0;
994 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
995 unsigned long bankcount;
996 unsigned long ddrtype;
997 unsigned long val;
998
df294497 999#ifdef CONFIG_DDR_ECC
4037ed3b 1000 ecc_enabled = TRUE;
df294497
SR		 1001#else
1002 ecc_enabled = FALSE;
1003#endif
4037ed3b
SR		 1004 dimm_32bit = FALSE;
1005 dimm_64bit = FALSE;
1006 buf0 = FALSE;
1007 buf1 = FALSE;
1008
1009 /*------------------------------------------------------------------
1010 * Set memory controller options reg 1, SDRAM_MCOPT1.
1011 *-----------------------------------------------------------------*/
1012 mfsdram(SDRAM_MCOPT1, val);
1013 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
1014 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
1015 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
1016 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
1017 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
1018 SDRAM_MCOPT1_DREF_MASK);
1019
1020 mcopt1 |= SDRAM_MCOPT1_QDEP;
1021 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
1022 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
1023 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1024 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1025 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1026
1027 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1028 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1029 /* test ecc support */
1030 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1031 if (ecc != 0x02) /* ecc not supported */
1032 ecc_enabled = FALSE;
1033
1034 /* test bank count */
1035 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1036 if (bankcount == 0x04) /* bank count = 4 */
1037 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1038 else /* bank count = 8 */
1039 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1040
1041 /* test DDR type */
1042 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
1043 /* test for buffered/unbuffered, registered, differential clocks */
1044 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1045 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1046
1047 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1048 if (dimm_num == 0) {
1049 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1050 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1051 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1052 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1053 if (registered == 1) { /* DDR2 always buffered */
1054 /* TODO: what about above comments ? */
1055 mcopt1 |= SDRAM_MCOPT1_RDEN;
1056 buf0 = TRUE;
1057 } else {
1058 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1059 if ((attribute & 0x02) == 0x00) {
1060 /* buffered not supported */
1061 buf0 = FALSE;
1062 } else {
1063 mcopt1 |= SDRAM_MCOPT1_RDEN;
1064 buf0 = TRUE;
1065 }
1066 }
1067 }
1068 else if (dimm_num == 1) {
1069 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1070 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1071 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1072 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1073 if (registered == 1) {
1074 /* DDR2 always buffered */
1075 mcopt1 |= SDRAM_MCOPT1_RDEN;
1076 buf1 = TRUE;
1077 } else {
1078 if ((attribute & 0x02) == 0x00) {
1079 /* buffered not supported */
1080 buf1 = FALSE;
1081 } else {
1082 mcopt1 |= SDRAM_MCOPT1_RDEN;
1083 buf1 = TRUE;
1084 }
1085 }
1086 }
1087
1088 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1089 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1090 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1091
1092 switch (data_width) {
1093 case 72:
1094 case 64:
1095 dimm_64bit = TRUE;
1096 break;
1097 case 40:
1098 case 32:
1099 dimm_32bit = TRUE;
1100 break;
1101 default:
b002144e 1102 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
4037ed3b
SR		 1103 data_width);
1104 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1105 break;
1106 }
1107 }
1108 }
1109
1110 /* verify matching properties */
1111 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1112 if (buf0 != buf1) {
1113 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
a5d71e29 1114 spd_ddr_init_hang ();
4037ed3b
SR		 1115 }
1116 }
1117
1118 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1119 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
a5d71e29 1120 spd_ddr_init_hang ();
4037ed3b
SR		 1121 }
1122 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1123 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1124 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1125 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1126 } else {
1127 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
a5d71e29 1128 spd_ddr_init_hang ();
4037ed3b
SR		 1129 }
1130
1131 if (ecc_enabled == TRUE)
1132 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1133 else
1134 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1135
1136 mtsdram(SDRAM_MCOPT1, mcopt1);
1137}
1138
1139/*-----------------------------------------------------------------------------+
1140 * program_codt.
1141 *-----------------------------------------------------------------------------*/
1142static void program_codt(unsigned long *dimm_populated,
1143 unsigned char *iic0_dimm_addr,
1144 unsigned long num_dimm_banks)
1145{
1146 unsigned long codt;
1147 unsigned long modt0 = 0;
1148 unsigned long modt1 = 0;
1149 unsigned long modt2 = 0;
1150 unsigned long modt3 = 0;
1151 unsigned char dimm_num;
1152 unsigned char dimm_rank;
1153 unsigned char total_rank = 0;
1154 unsigned char total_dimm = 0;
1155 unsigned char dimm_type = 0;
1156 unsigned char firstSlot = 0;
1157
1158 /*------------------------------------------------------------------
1159 * Set the SDRAM Controller On Die Termination Register
1160 *-----------------------------------------------------------------*/
1161 mfsdram(SDRAM_CODT, codt);
7369f0e3
CS		 1162 codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1163 codt |= SDRAM_CODT_IO_NMODE;
4037ed3b
SR		 1164
1165 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1166 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1167 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1168 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1169 dimm_rank = (dimm_rank & 0x0F) + 1;
1170 dimm_type = SDRAM_DDR2;
1171 } else {
1172 dimm_rank = dimm_rank & 0x0F;
1173 dimm_type = SDRAM_DDR1;
1174 }
1175
ba58e4c9
SR		 1176 total_rank += dimm_rank;
1177 total_dimm++;
4037ed3b
SR		 1178 if ((dimm_num == 0) && (total_dimm == 1))
1179 firstSlot = TRUE;
1180 else
1181 firstSlot = FALSE;
1182 }
1183 }
1184 if (dimm_type == SDRAM_DDR2) {
1185 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1186 if ((total_dimm == 1) && (firstSlot == TRUE)) {
f2302d44 1187 if (total_rank == 1) { /* PUUU */
ba58e4c9
SR		 1188 codt |= CALC_ODT_R(0);
1189 modt0 = CALC_ODT_W(0);
4037ed3b
SR		 1190 modt1 = 0x00000000;
1191 modt2 = 0x00000000;
1192 modt3 = 0x00000000;
1193 }
f2302d44 1194 if (total_rank == 2) { /* PPUU */
ba58e4c9 1195 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
f2302d44
SR		 1196 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1197 modt1 = 0x00000000;
4037ed3b
SR		 1198 modt2 = 0x00000000;
1199 modt3 = 0x00000000;
1200 }
ba58e4c9 1201 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
f2302d44 1202 if (total_rank == 1) { /* UUPU */
ba58e4c9
SR		 1203 codt |= CALC_ODT_R(2);
1204 modt0 = 0x00000000;
4037ed3b 1205 modt1 = 0x00000000;
ba58e4c9 1206 modt2 = CALC_ODT_W(2);
4037ed3b
SR		 1207 modt3 = 0x00000000;
1208 }
f2302d44 1209 if (total_rank == 2) { /* UUPP */
ba58e4c9
SR		 1210 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1211 modt0 = 0x00000000;
1212 modt1 = 0x00000000;
f2302d44
SR		 1213 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1214 modt3 = 0x00000000;
4037ed3b
SR		 1215 }
1216 }
1217 if (total_dimm == 2) {
f2302d44 1218 if (total_rank == 2) { /* PUPU */
ba58e4c9
SR		 1219 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1220 modt0 = CALC_ODT_RW(2);
4037ed3b 1221 modt1 = 0x00000000;
ba58e4c9 1222 modt2 = CALC_ODT_RW(0);
4037ed3b
SR		 1223 modt3 = 0x00000000;
1224 }
f2302d44 1225 if (total_rank == 4) { /* PPPP */
7187db73
SR		 1226 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1227 CALC_ODT_R(2) | CALC_ODT_R(3);
f2302d44 1228 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
ba58e4c9 1229 modt1 = 0x00000000;
f2302d44 1230 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
ba58e4c9 1231 modt3 = 0x00000000;
4037ed3b
SR		 1232 }
1233 }
647d3c3e 1234 } else {
4037ed3b
SR		 1235 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1236 modt0 = 0x00000000;
1237 modt1 = 0x00000000;
1238 modt2 = 0x00000000;
1239 modt3 = 0x00000000;
1240
1241 if (total_dimm == 1) {
1242 if (total_rank == 1)
1243 codt |= 0x00800000;
1244 if (total_rank == 2)
1245 codt |= 0x02800000;
1246 }
1247 if (total_dimm == 2) {
1248 if (total_rank == 2)
1249 codt |= 0x08800000;
1250 if (total_rank == 4)
1251 codt |= 0x2a800000;
1252 }
1253 }
1254
1255 debug("nb of dimm %d\n", total_dimm);
1256 debug("nb of rank %d\n", total_rank);
1257 if (total_dimm == 1)
1258 debug("dimm in slot %d\n", firstSlot);
1259
1260 mtsdram(SDRAM_CODT, codt);
1261 mtsdram(SDRAM_MODT0, modt0);
1262 mtsdram(SDRAM_MODT1, modt1);
1263 mtsdram(SDRAM_MODT2, modt2);
1264 mtsdram(SDRAM_MODT3, modt3);
1265}
1266
1267/*-----------------------------------------------------------------------------+
1268 * program_initplr.
1269 *-----------------------------------------------------------------------------*/
1270static void program_initplr(unsigned long *dimm_populated,
1271 unsigned char *iic0_dimm_addr,
1272 unsigned long num_dimm_banks,
ad5bb451 1273 ddr_cas_id_t selected_cas,
ba58e4c9 1274 int write_recovery)
4037ed3b 1275{
ba58e4c9
SR		 1276 u32 cas = 0;
1277 u32 odt = 0;
1278 u32 ods = 0;
1279 u32 mr;
1280 u32 wr;
1281 u32 emr;
1282 u32 emr2;
1283 u32 emr3;
1284 int dimm_num;
1285 int total_dimm = 0;
4037ed3b
SR		 1286
1287 /******************************************************
1288 ** Assumption: if more than one DIMM, all DIMMs are the same
74357114 1289 ** as already checked in check_memory_type
4037ed3b
SR		 1290 ******************************************************/
1291
1292 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1293 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1294 mtsdram(SDRAM_INITPLR1, 0x81900400);
1295 mtsdram(SDRAM_INITPLR2, 0x81810000);
1296 mtsdram(SDRAM_INITPLR3, 0xff800162);
1297 mtsdram(SDRAM_INITPLR4, 0x81900400);
1298 mtsdram(SDRAM_INITPLR5, 0x86080000);
1299 mtsdram(SDRAM_INITPLR6, 0x86080000);
1300 mtsdram(SDRAM_INITPLR7, 0x81000062);
1301 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1302 switch (selected_cas) {
4037ed3b 1303 case DDR_CAS_3:
ba58e4c9 1304 cas = 3 << 4;
4037ed3b
SR		 1305 break;
1306 case DDR_CAS_4:
ba58e4c9 1307 cas = 4 << 4;
4037ed3b
SR		 1308 break;
1309 case DDR_CAS_5:
ba58e4c9 1310 cas = 5 << 4;
4037ed3b
SR		 1311 break;
1312 default:
ba58e4c9 1313 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
a5d71e29 1314 spd_ddr_init_hang ();
4037ed3b
SR		 1315 break;
1316 }
1317
ba58e4c9
SR		 1318#if 0
1319 /*
1320 * ToDo - Still a problem with the write recovery:
1321 * On the Corsair CM2X512-5400C4 module, setting write recovery
1322 * in the INITPLR reg to the value calculated in program_mode()
1323 * results in not correctly working DDR2 memory (crash after
1324 * relocation).
1325 *
1326 * So for now, set the write recovery to 3. This seems to work
1327 * on the Corair module too.
1328 *
1329 * 2007-03-01, sr
1330 */
1331 switch (write_recovery) {
1332 case 3:
1333 wr = WRITE_RECOV_3;
1334 break;
1335 case 4:
1336 wr = WRITE_RECOV_4;
1337 break;
1338 case 5:
1339 wr = WRITE_RECOV_5;
1340 break;
1341 case 6:
1342 wr = WRITE_RECOV_6;
1343 break;
1344 default:
1345 printf("ERROR: write recovery not support (%d)", write_recovery);
a5d71e29 1346 spd_ddr_init_hang ();
ba58e4c9
SR		 1347 break;
1348 }
1349#else
1350 wr = WRITE_RECOV_3; /* test-only, see description above */
1351#endif
1352
1353 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1354 if (dimm_populated[dimm_num] != SDRAM_NONE)
1355 total_dimm++;
1356 if (total_dimm == 1) {
1357 odt = ODT_150_OHM;
1358 ods = ODS_FULL;
1359 } else if (total_dimm == 2) {
1360 odt = ODT_75_OHM;
1361 ods = ODS_REDUCED;
1362 } else {
1363 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
a5d71e29 1364 spd_ddr_init_hang ();
ba58e4c9
SR		 1365 }
1366
1367 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1368 emr = CMD_EMR | SELECT_EMR | odt | ods;
1369 emr2 = CMD_EMR | SELECT_EMR2;
1370 emr3 = CMD_EMR | SELECT_EMR3;
04737d5f
PH		 1371 /* NOP - Wait 106 MemClk cycles */
1372 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1373 SDRAM_INITPLR_IMWT_ENCODE(106));
ba58e4c9 1374 udelay(1000);
04737d5f
PH		 1375 /* precharge 4 MemClk cycles */
1376 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1377 SDRAM_INITPLR_IMWT_ENCODE(4));
1378 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1379 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1380 SDRAM_INITPLR_IMWT_ENCODE(2));
1381 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1382 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1383 SDRAM_INITPLR_IMWT_ENCODE(2));
1384 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1385 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1386 SDRAM_INITPLR_IMWT_ENCODE(2));
1387 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1388 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1389 SDRAM_INITPLR_IMWT_ENCODE(200));
ba58e4c9 1390 udelay(1000);
04737d5f
PH		 1391 /* precharge 4 MemClk cycles */
1392 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1393 SDRAM_INITPLR_IMWT_ENCODE(4));
1394 /* Refresh 25 MemClk cycles */
1395 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1396 SDRAM_INITPLR_IMWT_ENCODE(25));
1397 /* Refresh 25 MemClk cycles */
1398 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1399 SDRAM_INITPLR_IMWT_ENCODE(25));
1400 /* Refresh 25 MemClk cycles */
1401 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1402 SDRAM_INITPLR_IMWT_ENCODE(25));
1403 /* Refresh 25 MemClk cycles */
1404 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1405 SDRAM_INITPLR_IMWT_ENCODE(25));
1406 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1407 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1408 SDRAM_INITPLR_IMWT_ENCODE(2));
1409 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1410 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1411 SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1412 /* EMR OCD Exit */
1413 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1414 SDRAM_INITPLR_IMWT_ENCODE(2));
4037ed3b
SR		 1415 } else {
1416 printf("ERROR: ucode error as unknown DDR type in program_initplr");
a5d71e29 1417 spd_ddr_init_hang ();
4037ed3b
SR		 1418 }
1419}
1420
1421/*------------------------------------------------------------------
1422 * This routine programs the SDRAM_MMODE register.
1423 * the selected_cas is an output parameter, that will be passed
1424 * by caller to call the above program_initplr( )
1425 *-----------------------------------------------------------------*/
1426static void program_mode(unsigned long *dimm_populated,
1427 unsigned char *iic0_dimm_addr,
1428 unsigned long num_dimm_banks,
ba58e4c9
SR		 1429 ddr_cas_id_t *selected_cas,
1430 int *write_recovery)
4037ed3b
SR		 1431{
1432 unsigned long dimm_num;
1433 unsigned long sdram_ddr1;
1434 unsigned long t_wr_ns;
1435 unsigned long t_wr_clk;
1436 unsigned long cas_bit;
1437 unsigned long cas_index;
1438 unsigned long sdram_freq;
1439 unsigned long ddr_check;
1440 unsigned long mmode;
1441 unsigned long tcyc_reg;
1442 unsigned long cycle_2_0_clk;
1443 unsigned long cycle_2_5_clk;
1444 unsigned long cycle_3_0_clk;
1445 unsigned long cycle_4_0_clk;
1446 unsigned long cycle_5_0_clk;
1447 unsigned long max_2_0_tcyc_ns_x_100;
1448 unsigned long max_2_5_tcyc_ns_x_100;
1449 unsigned long max_3_0_tcyc_ns_x_100;
1450 unsigned long max_4_0_tcyc_ns_x_100;
1451 unsigned long max_5_0_tcyc_ns_x_100;
1452 unsigned long cycle_time_ns_x_100[3];
087dfdb7 1453 PPC4xx_SYS_INFO board_cfg;
4037ed3b
SR		 1454 unsigned char cas_2_0_available;
1455 unsigned char cas_2_5_available;
1456 unsigned char cas_3_0_available;
1457 unsigned char cas_4_0_available;
1458 unsigned char cas_5_0_available;
1459 unsigned long sdr_ddrpll;
1460
1461 /*------------------------------------------------------------------
1462 * Get the board configuration info.
1463 *-----------------------------------------------------------------*/
1464 get_sys_info(&board_cfg);
1465
df294497 1466 mfsdr(SDR0_DDR0, sdr_ddrpll);
4037ed3b 1467 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
48e2b535 1468 debug("sdram_freq=%lu\n", sdram_freq);
4037ed3b
SR		 1469
1470 /*------------------------------------------------------------------
1471 * Handle the timing. We need to find the worst case timing of all
1472 * the dimm modules installed.
1473 *-----------------------------------------------------------------*/
1474 t_wr_ns = 0;
1475 cas_2_0_available = TRUE;
1476 cas_2_5_available = TRUE;
1477 cas_3_0_available = TRUE;
1478 cas_4_0_available = TRUE;
1479 cas_5_0_available = TRUE;
1480 max_2_0_tcyc_ns_x_100 = 10;
1481 max_2_5_tcyc_ns_x_100 = 10;
1482 max_3_0_tcyc_ns_x_100 = 10;
1483 max_4_0_tcyc_ns_x_100 = 10;
1484 max_5_0_tcyc_ns_x_100 = 10;
1485 sdram_ddr1 = TRUE;
1486
1487 /* loop through all the DIMM slots on the board */
1488 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1489 /* If a dimm is installed in a particular slot ... */
1490 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1491 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1492 sdram_ddr1 = TRUE;
1493 else
1494 sdram_ddr1 = FALSE;
1495
1496 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1497 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
48e2b535 1498 debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
4037ed3b
SR		 1499
1500 /* For a particular DIMM, grab the three CAS values it supports */
1501 for (cas_index = 0; cas_index < 3; cas_index++) {
1502 switch (cas_index) {
1503 case 0:
1504 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1505 break;
1506 case 1:
1507 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1508 break;
1509 default:
1510 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1511 break;
1512 }
1513
1514 if ((tcyc_reg & 0x0F) >= 10) {
1515 if ((tcyc_reg & 0x0F) == 0x0D) {
1516 /* Convert from hex to decimal */
cabee756
SR		 1517 cycle_time_ns_x_100[cas_index] =
1518 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
4037ed3b
SR		 1519 } else {
1520 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1521 "in slot %d\n", (unsigned int)dimm_num);
a5d71e29 1522 spd_ddr_init_hang ();
4037ed3b
SR		 1523 }
1524 } else {
1525 /* Convert from hex to decimal */
cabee756
SR		 1526 cycle_time_ns_x_100[cas_index] =
1527 (((tcyc_reg & 0xF0) >> 4) * 100) +
4037ed3b
SR		 1528 ((tcyc_reg & 0x0F)*10);
1529 }
48e2b535 1530 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
cabee756 1531 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1532 }
1533
1534 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1535 /* supported for a particular DIMM. */
1536 cas_index = 0;
1537
1538 if (sdram_ddr1) {
1539 /*
1540 * DDR devices use the following bitmask for CAS latency:
1541 * Bit 7 6 5 4 3 2 1 0
1542 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1543 */
cabee756
SR		 1544 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1545 (cycle_time_ns_x_100[cas_index] != 0)) {
1546 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1547 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1548 cas_index++;
1549 } else {
1550 if (cas_index != 0)
1551 cas_index++;
1552 cas_4_0_available = FALSE;
1553 }
1554
cabee756
SR		 1555 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1556 (cycle_time_ns_x_100[cas_index] != 0)) {
1557 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1558 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1559 cas_index++;
1560 } else {
1561 if (cas_index != 0)
1562 cas_index++;
1563 cas_3_0_available = FALSE;
1564 }
1565
cabee756
SR		 1566 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1567 (cycle_time_ns_x_100[cas_index] != 0)) {
1568 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1569 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1570 cas_index++;
1571 } else {
1572 if (cas_index != 0)
1573 cas_index++;
1574 cas_2_5_available = FALSE;
1575 }
1576
cabee756
SR		 1577 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1578 (cycle_time_ns_x_100[cas_index] != 0)) {
1579 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1580 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1581 cas_index++;
1582 } else {
1583 if (cas_index != 0)
1584 cas_index++;
1585 cas_2_0_available = FALSE;
1586 }
1587 } else {
1588 /*
1589 * DDR2 devices use the following bitmask for CAS latency:
1590 * Bit 7 6 5 4 3 2 1 0
1591 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1592 */
cabee756
SR		 1593 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1594 (cycle_time_ns_x_100[cas_index] != 0)) {
1595 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1596 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1597 cas_index++;
1598 } else {
1599 if (cas_index != 0)
1600 cas_index++;
1601 cas_5_0_available = FALSE;
1602 }
1603
cabee756
SR		 1604 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1605 (cycle_time_ns_x_100[cas_index] != 0)) {
1606 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1607 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1608 cas_index++;
1609 } else {
1610 if (cas_index != 0)
1611 cas_index++;
1612 cas_4_0_available = FALSE;
1613 }
1614
cabee756
SR		 1615 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1616 (cycle_time_ns_x_100[cas_index] != 0)) {
1617 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1618 cycle_time_ns_x_100[cas_index]);
4037ed3b
SR		 1619 cas_index++;
1620 } else {
1621 if (cas_index != 0)
1622 cas_index++;
1623 cas_3_0_available = FALSE;
1624 }
1625 }
1626 }
1627 }
1628
1629 /*------------------------------------------------------------------
1630 * Set the SDRAM mode, SDRAM_MMODE
1631 *-----------------------------------------------------------------*/
1632 mfsdram(SDRAM_MMODE, mmode);
1633 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1634
df294497
SR		 1635 /* add 10 here because of rounding problems */
1636 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1637 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1638 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1639 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1640 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
48e2b535
FR		 1641 debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1642 debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1643 debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
4037ed3b
SR		 1644
1645 if (sdram_ddr1 == TRUE) { /* DDR1 */
1646 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1647 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1648 *selected_cas = DDR_CAS_2;
1649 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1650 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1651 *selected_cas = DDR_CAS_2_5;
1652 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1653 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1654 *selected_cas = DDR_CAS_3;
1655 } else {
1656 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1657 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1658 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
a5d71e29 1659 spd_ddr_init_hang ();
4037ed3b
SR		 1660 }
1661 } else { /* DDR2 */
94f54703
SR		 1662 debug("cas_3_0_available=%d\n", cas_3_0_available);
1663 debug("cas_4_0_available=%d\n", cas_4_0_available);
1664 debug("cas_5_0_available=%d\n", cas_5_0_available);
4037ed3b
SR		 1665 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1666 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1667 *selected_cas = DDR_CAS_3;
1668 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1669 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1670 *selected_cas = DDR_CAS_4;
1671 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1672 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1673 *selected_cas = DDR_CAS_5;
1674 } else {
1675 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1676 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
df294497
SR		 1677 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1678 printf("cas3=%d cas4=%d cas5=%d\n",
1679 cas_3_0_available, cas_4_0_available, cas_5_0_available);
b002144e 1680 printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
df294497 1681 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
a5d71e29 1682 spd_ddr_init_hang ();
4037ed3b
SR		 1683 }
1684 }
1685
1686 if (sdram_ddr1 == TRUE)
1687 mmode |= SDRAM_MMODE_WR_DDR1;
1688 else {
1689
1690 /* loop through all the DIMM slots on the board */
1691 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1692 /* If a dimm is installed in a particular slot ... */
1693 if (dimm_populated[dimm_num] != SDRAM_NONE)
1694 t_wr_ns = max(t_wr_ns,
1695 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1696 }
1697
1698 /*
1699 * convert from nanoseconds to ddr clocks
1700 * round up if necessary
1701 */
1702 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1703 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1704 if (sdram_freq != ddr_check)
1705 t_wr_clk++;
1706
1707 switch (t_wr_clk) {
1708 case 0:
1709 case 1:
1710 case 2:
1711 case 3:
1712 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1713 break;
1714 case 4:
1715 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1716 break;
1717 case 5:
1718 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1719 break;
1720 default:
1721 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1722 break;
1723 }
ba58e4c9 1724 *write_recovery = t_wr_clk;
4037ed3b
SR		 1725 }
1726
ba58e4c9
SR		 1727 debug("CAS latency = %d\n", *selected_cas);
1728 debug("Write recovery = %d\n", *write_recovery);
1729
4037ed3b
SR		 1730 mtsdram(SDRAM_MMODE, mmode);
1731}
1732
1733/*-----------------------------------------------------------------------------+
1734 * program_rtr.
1735 *-----------------------------------------------------------------------------*/
1736static void program_rtr(unsigned long *dimm_populated,
1737 unsigned char *iic0_dimm_addr,
1738 unsigned long num_dimm_banks)
1739{
087dfdb7 1740 PPC4xx_SYS_INFO board_cfg;
4037ed3b
SR		 1741 unsigned long max_refresh_rate;
1742 unsigned long dimm_num;
1743 unsigned long refresh_rate_type;
1744 unsigned long refresh_rate;
1745 unsigned long rint;
1746 unsigned long sdram_freq;
1747 unsigned long sdr_ddrpll;
1748 unsigned long val;
1749
1750 /*------------------------------------------------------------------
1751 * Get the board configuration info.
1752 *-----------------------------------------------------------------*/
1753 get_sys_info(&board_cfg);
1754
1755 /*------------------------------------------------------------------
1756 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1757 *-----------------------------------------------------------------*/
df294497 1758 mfsdr(SDR0_DDR0, sdr_ddrpll);
4037ed3b
SR		 1759 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1760
1761 max_refresh_rate = 0;
1762 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1763 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1764
1765 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1766 refresh_rate_type &= 0x7F;
1767 switch (refresh_rate_type) {
1768 case 0:
1769 refresh_rate = 15625;
1770 break;
1771 case 1:
1772 refresh_rate = 3906;
1773 break;
1774 case 2:
1775 refresh_rate = 7812;
1776 break;
1777 case 3:
1778 refresh_rate = 31250;
1779 break;
1780 case 4:
1781 refresh_rate = 62500;
1782 break;
1783 case 5:
1784 refresh_rate = 125000;
1785 break;
1786 default:
1787 refresh_rate = 0;
1788 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1789 (unsigned int)dimm_num);
1790 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 1791 spd_ddr_init_hang ();
4037ed3b
SR		 1792 break;
1793 }
1794
1795 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1796 }
1797 }
1798
1799 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1800 mfsdram(SDRAM_RTR, val);
1801 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1802 (SDRAM_RTR_RINT_ENCODE(rint)));
1803}
1804
1805/*------------------------------------------------------------------
1806 * This routine programs the SDRAM_TRx registers.
1807 *-----------------------------------------------------------------*/
1808static void program_tr(unsigned long *dimm_populated,
1809 unsigned char *iic0_dimm_addr,
1810 unsigned long num_dimm_banks)
1811{
1812 unsigned long dimm_num;
1813 unsigned long sdram_ddr1;
1814 unsigned long t_rp_ns;
1815 unsigned long t_rcd_ns;
1816 unsigned long t_rrd_ns;
1817 unsigned long t_ras_ns;
1818 unsigned long t_rc_ns;
1819 unsigned long t_rfc_ns;
1820 unsigned long t_wpc_ns;
1821 unsigned long t_wtr_ns;
1822 unsigned long t_rpc_ns;
1823 unsigned long t_rp_clk;
1824 unsigned long t_rcd_clk;
1825 unsigned long t_rrd_clk;
1826 unsigned long t_ras_clk;
1827 unsigned long t_rc_clk;
1828 unsigned long t_rfc_clk;
1829 unsigned long t_wpc_clk;
1830 unsigned long t_wtr_clk;
1831 unsigned long t_rpc_clk;
1832 unsigned long sdtr1, sdtr2, sdtr3;
1833 unsigned long ddr_check;
1834 unsigned long sdram_freq;
1835 unsigned long sdr_ddrpll;
1836
087dfdb7 1837 PPC4xx_SYS_INFO board_cfg;
4037ed3b
SR		 1838
1839 /*------------------------------------------------------------------
1840 * Get the board configuration info.
1841 *-----------------------------------------------------------------*/
1842 get_sys_info(&board_cfg);
1843
df294497 1844 mfsdr(SDR0_DDR0, sdr_ddrpll);
4037ed3b
SR		 1845 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1846
1847 /*------------------------------------------------------------------
1848 * Handle the timing. We need to find the worst case timing of all
1849 * the dimm modules installed.
1850 *-----------------------------------------------------------------*/
1851 t_rp_ns = 0;
1852 t_rrd_ns = 0;
1853 t_rcd_ns = 0;
1854 t_ras_ns = 0;
1855 t_rc_ns = 0;
1856 t_rfc_ns = 0;
1857 t_wpc_ns = 0;
1858 t_wtr_ns = 0;
1859 t_rpc_ns = 0;
1860 sdram_ddr1 = TRUE;
1861
1862 /* loop through all the DIMM slots on the board */
1863 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1864 /* If a dimm is installed in a particular slot ... */
1865 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1866 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1867 sdram_ddr1 = TRUE;
1868 else
1869 sdram_ddr1 = FALSE;
1870
1871 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1872 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1873 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1874 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1875 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1876 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1877 }
1878 }
1879
1880 /*------------------------------------------------------------------
1881 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1882 *-----------------------------------------------------------------*/
1883 mfsdram(SDRAM_SDTR1, sdtr1);
1884 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1885 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1886
1887 /* default values */
1888 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1889 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1890
1891 /* normal operations */
1892 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1893 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1894
1895 mtsdram(SDRAM_SDTR1, sdtr1);
1896
1897 /*------------------------------------------------------------------
1898 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1899 *-----------------------------------------------------------------*/
1900 mfsdram(SDRAM_SDTR2, sdtr2);
1901 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1902 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1903 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1904 SDRAM_SDTR2_RRD_MASK);
1905
1906 /*
1907 * convert t_rcd from nanoseconds to ddr clocks
1908 * round up if necessary
1909 */
1910 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1911 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1912 if (sdram_freq != ddr_check)
1913 t_rcd_clk++;
1914
1915 switch (t_rcd_clk) {
1916 case 0:
1917 case 1:
1918 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1919 break;
1920 case 2:
1921 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1922 break;
1923 case 3:
1924 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1925 break;
1926 case 4:
1927 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1928 break;
1929 default:
1930 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1931 break;
1932 }
1933
1934 if (sdram_ddr1 == TRUE) { /* DDR1 */
1935 if (sdram_freq < 200000000) {
1936 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1937 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1938 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1939 } else {
1940 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1941 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1942 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1943 }
1944 } else { /* DDR2 */
1945 /* loop through all the DIMM slots on the board */
1946 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1947 /* If a dimm is installed in a particular slot ... */
1948 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1949 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1950 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1951 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1952 }
1953 }
1954
1955 /*
1956 * convert from nanoseconds to ddr clocks
1957 * round up if necessary
1958 */
1959 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1960 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1961 if (sdram_freq != ddr_check)
1962 t_wpc_clk++;
1963
1964 switch (t_wpc_clk) {
1965 case 0:
1966 case 1:
1967 case 2:
1968 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1969 break;
1970 case 3:
1971 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1972 break;
1973 case 4:
1974 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1975 break;
1976 case 5:
1977 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1978 break;
1979 default:
1980 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1981 break;
1982 }
1983
1984 /*
1985 * convert from nanoseconds to ddr clocks
1986 * round up if necessary
1987 */
1988 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1989 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1990 if (sdram_freq != ddr_check)
1991 t_wtr_clk++;
1992
1993 switch (t_wtr_clk) {
1994 case 0:
1995 case 1:
1996 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1997 break;
1998 case 2:
1999 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
2000 break;
2001 case 3:
2002 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
2003 break;
2004 default:
2005 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
2006 break;
2007 }
2008
2009 /*
2010 * convert from nanoseconds to ddr clocks
2011 * round up if necessary
2012 */
2013 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
2014 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2015 if (sdram_freq != ddr_check)
2016 t_rpc_clk++;
2017
2018 switch (t_rpc_clk) {
2019 case 0:
2020 case 1:
2021 case 2:
2022 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2023 break;
2024 case 3:
2025 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2026 break;
2027 default:
2028 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2029 break;
2030 }
2031 }
2032
2033 /* default value */
2034 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2035
2036 /*
2037 * convert t_rrd from nanoseconds to ddr clocks
2038 * round up if necessary
2039 */
2040 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2041 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2042 if (sdram_freq != ddr_check)
2043 t_rrd_clk++;
2044
2045 if (t_rrd_clk == 3)
2046 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2047 else
2048 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2049
2050 /*
2051 * convert t_rp from nanoseconds to ddr clocks
2052 * round up if necessary
2053 */
2054 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2055 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2056 if (sdram_freq != ddr_check)
2057 t_rp_clk++;
2058
2059 switch (t_rp_clk) {
2060 case 0:
2061 case 1:
2062 case 2:
2063 case 3:
2064 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2065 break;
2066 case 4:
2067 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2068 break;
2069 case 5:
2070 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2071 break;
2072 case 6:
2073 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2074 break;
2075 default:
2076 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2077 break;
2078 }
2079
2080 mtsdram(SDRAM_SDTR2, sdtr2);
2081
2082 /*------------------------------------------------------------------
2083 * Set the SDRAM Timing Reg 3, SDRAM_TR3
2084 *-----------------------------------------------------------------*/
2085 mfsdram(SDRAM_SDTR3, sdtr3);
2086 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
2087 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2088
2089 /*
2090 * convert t_ras from nanoseconds to ddr clocks
2091 * round up if necessary
2092 */
2093 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2094 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2095 if (sdram_freq != ddr_check)
2096 t_ras_clk++;
2097
2098 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2099
2100 /*
2101 * convert t_rc from nanoseconds to ddr clocks
2102 * round up if necessary
2103 */
2104 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2105 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2106 if (sdram_freq != ddr_check)
2107 t_rc_clk++;
2108
2109 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2110
2111 /* default xcs value */
2112 sdtr3 |= SDRAM_SDTR3_XCS;
2113
2114 /*
2115 * convert t_rfc from nanoseconds to ddr clocks
2116 * round up if necessary
2117 */
2118 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2119 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2120 if (sdram_freq != ddr_check)
2121 t_rfc_clk++;
2122
2123 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2124
2125 mtsdram(SDRAM_SDTR3, sdtr3);
2126}
2127
2128/*-----------------------------------------------------------------------------+
2129 * program_bxcf.
2130 *-----------------------------------------------------------------------------*/
2131static void program_bxcf(unsigned long *dimm_populated,
2132 unsigned char *iic0_dimm_addr,
2133 unsigned long num_dimm_banks)
2134{
2135 unsigned long dimm_num;
2136 unsigned long num_col_addr;
2137 unsigned long num_ranks;
2138 unsigned long num_banks;
2139 unsigned long mode;
2140 unsigned long ind_rank;
2141 unsigned long ind;
2142 unsigned long ind_bank;
2143 unsigned long bank_0_populated;
2144
2145 /*------------------------------------------------------------------
2146 * Set the BxCF regs. First, wipe out the bank config registers.
2147 *-----------------------------------------------------------------*/
087dfdb7
SR		 2148 mtsdram(SDRAM_MB0CF, 0x00000000);
2149 mtsdram(SDRAM_MB1CF, 0x00000000);
2150 mtsdram(SDRAM_MB2CF, 0x00000000);
2151 mtsdram(SDRAM_MB3CF, 0x00000000);
4037ed3b
SR		 2152
2153 mode = SDRAM_BXCF_M_BE_ENABLE;
2154
2155 bank_0_populated = 0;
2156
2157 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2158 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2159 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2160 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2161 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2162 num_ranks = (num_ranks & 0x0F) +1;
2163 else
2164 num_ranks = num_ranks & 0x0F;
2165
2166 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2167
2168 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2169 if (num_banks == 4)
2170 ind = 0;
2171 else
ea9202a6 2172 ind = 5 << 8;
4037ed3b
SR		 2173 switch (num_col_addr) {
2174 case 0x08:
2175 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2176 break;
2177 case 0x09:
2178 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2179 break;
2180 case 0x0A:
2181 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2182 break;
2183 case 0x0B:
2184 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2185 break;
2186 case 0x0C:
2187 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2188 break;
2189 default:
2190 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2191 (unsigned int)dimm_num);
2192 printf("ERROR: Unsupported value for number of "
2193 "column addresses: %d.\n", (unsigned int)num_col_addr);
2194 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 2195 spd_ddr_init_hang ();
4037ed3b
SR		 2196 }
2197 }
2198
2199 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2200 bank_0_populated = 1;
2201
2202 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
087dfdb7
SR		 2203 mtsdram(SDRAM_MB0CF +
2204 ((dimm_num + bank_0_populated + ind_rank) << 2),
2205 mode);
4037ed3b
SR		 2206 }
2207 }
2208 }
2209}
2210
2211/*------------------------------------------------------------------
2212 * program memory queue.
2213 *-----------------------------------------------------------------*/
2214static void program_memory_queue(unsigned long *dimm_populated,
2215 unsigned char *iic0_dimm_addr,
2216 unsigned long num_dimm_banks)
2217{
2218 unsigned long dimm_num;
5d812b8b 2219 phys_size_t rank_base_addr;
4037ed3b 2220 unsigned long rank_reg;
5d812b8b 2221 phys_size_t rank_size_bytes;
4037ed3b
SR		 2222 unsigned long rank_size_id;
2223 unsigned long num_ranks;
2224 unsigned long baseadd_size;
2225 unsigned long i;
2226 unsigned long bank_0_populated = 0;
5d812b8b 2227 phys_size_t total_size = 0;
4037ed3b
SR		 2228
2229 /*------------------------------------------------------------------
2230 * Reset the rank_base_address.
2231 *-----------------------------------------------------------------*/
2232 rank_reg = SDRAM_R0BAS;
2233
2234 rank_base_addr = 0x00000000;
2235
2236 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2237 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2238 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2239 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2240 num_ranks = (num_ranks & 0x0F) + 1;
2241 else
2242 num_ranks = num_ranks & 0x0F;
2243
2244 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2245
2246 /*------------------------------------------------------------------
2247 * Set the sizes
2248 *-----------------------------------------------------------------*/
2249 baseadd_size = 0;
4037ed3b 2250 switch (rank_size_id) {
8ac41e3e
SR		 2251 case 0x01:
2252 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2253 total_size = 1024;
2254 break;
4037ed3b 2255 case 0x02:
8ac41e3e
SR		 2256 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2257 total_size = 2048;
4037ed3b
SR		 2258 break;
2259 case 0x04:
8ac41e3e
SR		 2260 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2261 total_size = 4096;
4037ed3b
SR		 2262 break;
2263 case 0x08:
2264 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
8ac41e3e 2265 total_size = 32;
4037ed3b
SR		 2266 break;
2267 case 0x10:
2268 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
8ac41e3e 2269 total_size = 64;
4037ed3b
SR		 2270 break;
2271 case 0x20:
2272 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
8ac41e3e 2273 total_size = 128;
4037ed3b
SR		 2274 break;
2275 case 0x40:
2276 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
8ac41e3e 2277 total_size = 256;
4037ed3b
SR		 2278 break;
2279 case 0x80:
2280 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
8ac41e3e 2281 total_size = 512;
4037ed3b
SR		 2282 break;
2283 default:
2284 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2285 (unsigned int)dimm_num);
2286 printf("ERROR: Unsupported value for the banksize: %d.\n",
2287 (unsigned int)rank_size_id);
2288 printf("Replace the DIMM module with a supported DIMM.\n\n");
a5d71e29 2289 spd_ddr_init_hang ();
4037ed3b 2290 }
8ac41e3e 2291 rank_size_bytes = total_size << 20;
4037ed3b
SR		 2292
2293 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2294 bank_0_populated = 1;
2295
2296 for (i = 0; i < num_ranks; i++) {
2297 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
df294497
SR		 2298 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2299 baseadd_size));
4037ed3b
SR		 2300 rank_base_addr += rank_size_bytes;
2301 }
2302 }
2303 }
8ac41e3e 2304
079589bc
PH		 2305#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2306 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2307 defined(CONFIG_460SX)
8ac41e3e 2308 /*
079589bc 2309 * Enable high bandwidth access
8ac41e3e
SR		 2310 * This is currently not used, but with this setup
2311 * it is possible to use it later on in e.g. the Linux
2312 * EMAC driver for performance gain.
2313 */
2314 mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2315 mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
079589bc
PH		 2316
2317 /*
2318 * Set optimal value for Memory Queue HB/LL Configuration registers
2319 */
bf29e0ea
YT		 2320 mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2321 SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2322 SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2323 mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2324 SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2325 SDRAM_CONF1LL_RPLM);
f5564837 2326 mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
8ac41e3e 2327#endif
4037ed3b
SR		 2328}
2329
df294497 2330#ifdef CONFIG_DDR_ECC
4037ed3b
SR		 2331/*-----------------------------------------------------------------------------+
2332 * program_ecc.
2333 *-----------------------------------------------------------------------------*/
2334static void program_ecc(unsigned long *dimm_populated,
2335 unsigned char *iic0_dimm_addr,
ba58e4c9
SR		 2336 unsigned long num_dimm_banks,
2337 unsigned long tlb_word2_i_value)
4037ed3b 2338{
4037ed3b
SR		 2339 unsigned long dimm_num;
2340 unsigned long ecc;
2341
2342 ecc = 0;
2343 /* loop through all the DIMM slots on the board */
2344 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2345 /* If a dimm is installed in a particular slot ... */
2346 if (dimm_populated[dimm_num] != SDRAM_NONE)
2347 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2348 }
2349 if (ecc == 0)
2350 return;
2351
d24bd251 2352 do_program_ecc(tlb_word2_i_value);
4037ed3b 2353}
df294497 2354#endif
4037ed3b 2355
f6b6c458 2356#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
4037ed3b
SR		 2357/*-----------------------------------------------------------------------------+
2358 * program_DQS_calibration.
2359 *-----------------------------------------------------------------------------*/
2360static void program_DQS_calibration(unsigned long *dimm_populated,
2361 unsigned char *iic0_dimm_addr,
2362 unsigned long num_dimm_banks)
2363{
2364 unsigned long val;
2365
2366#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2367 mtsdram(SDRAM_RQDC, 0x80000037);
2368 mtsdram(SDRAM_RDCC, 0x40000000);
2369 mtsdram(SDRAM_RFDC, 0x000001DF);
2370
2371 test();
2372#else
2373 /*------------------------------------------------------------------
2374 * Program RDCC register
2375 * Read sample cycle auto-update enable
2376 *-----------------------------------------------------------------*/
2377
4037ed3b
SR		 2378 mfsdram(SDRAM_RDCC, val);
2379 mtsdram(SDRAM_RDCC,
2380 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
845c6c95 2381 | SDRAM_RDCC_RSAE_ENABLE);
4037ed3b
SR		 2382
2383 /*------------------------------------------------------------------
2384 * Program RQDC register
2385 * Internal DQS delay mechanism enable
2386 *-----------------------------------------------------------------*/
2387 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2388
2389 /*------------------------------------------------------------------
2390 * Program RFDC register
2391 * Set Feedback Fractional Oversample
2392 * Auto-detect read sample cycle enable
04737d5f 2393 * Set RFOS to 1/4 of memclk cycle (0x3f)
4037ed3b
SR		 2394 *-----------------------------------------------------------------*/
2395 mfsdram(SDRAM_RFDC, val);
2396 mtsdram(SDRAM_RFDC,
2397 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2398 SDRAM_RFDC_RFFD_MASK))
04737d5f 2399 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
4037ed3b
SR		 2400 SDRAM_RFDC_RFFD_ENCODE(0)));
2401
2402 DQS_calibration_process();
2403#endif
2404}
2405
94f54703 2406static int short_mem_test(void)
4037ed3b
SR		 2407{
2408 u32 *membase;
2409 u32 bxcr_num;
2410 u32 bxcf;
2411 int i;
2412 int j;
5d812b8b 2413 phys_size_t base_addr;
4037ed3b
SR		 2414 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2415 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2416 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2417 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2418 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2419 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2420 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2421 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2422 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2423 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2424 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2425 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2426 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2427 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2428 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2429 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2430 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
94f54703 2431 int l;
4037ed3b
SR		 2432
2433 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2434 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2435
2436 /* Banks enabled */
2437 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
4037ed3b 2438 /* Bank is enabled */
4037ed3b 2439
5d812b8b
SR		 2440 /*
2441 * Only run test on accessable memory (below 2GB)
2442 */
2443 base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2444 if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2445 continue;
2446
4037ed3b
SR		 2447 /*------------------------------------------------------------------
2448 * Run the short memory test.
2449 *-----------------------------------------------------------------*/
5d812b8b 2450 membase = (u32 *)(u32)base_addr;
94f54703 2451
4037ed3b
SR		 2452 for (i = 0; i < NUMMEMTESTS; i++) {
2453 for (j = 0; j < NUMMEMWORDS; j++) {
2454 membase[j] = test[i][j];
2455 ppcDcbf((u32)&(membase[j]));
2456 }
2457 sync();
94f54703
SR		 2458 for (l=0; l<NUMLOOPS; l++) {
2459 for (j = 0; j < NUMMEMWORDS; j++) {
2460 if (membase[j] != test[i][j]) {
2461 ppcDcbf((u32)&(membase[j]));
2462 return 0;
2463 }
4037ed3b 2464 ppcDcbf((u32)&(membase[j]));
4037ed3b 2465 }
94f54703 2466 sync();
4037ed3b 2467 }
4037ed3b 2468 }
4037ed3b
SR		 2469 } /* if bank enabled */
2470 } /* for bxcf_num */
2471
94f54703 2472 return 1;
4037ed3b
SR		 2473}
2474
2475#ifndef HARD_CODED_DQS
2476/*-----------------------------------------------------------------------------+
2477 * DQS_calibration_process.
2478 *-----------------------------------------------------------------------------*/
2479static void DQS_calibration_process(void)
2480{
4037ed3b
SR		 2481 unsigned long rfdc_reg;
2482 unsigned long rffd;
4037ed3b 2483 unsigned long val;
4037ed3b
SR		 2484 long rffd_average;
2485 long max_start;
2486 long min_end;
2487 unsigned long begin_rqfd[MAXRANKS];
2488 unsigned long begin_rffd[MAXRANKS];
2489 unsigned long end_rqfd[MAXRANKS];
2490 unsigned long end_rffd[MAXRANKS];
2491 char window_found;
2492 unsigned long dlycal;
2493 unsigned long dly_val;
2494 unsigned long max_pass_length;
2495 unsigned long current_pass_length;
2496 unsigned long current_fail_length;
2497 unsigned long current_start;
2498 long max_end;
2499 unsigned char fail_found;
2500 unsigned char pass_found;
845c6c95
SR		 2501#if !defined(CONFIG_DDR_RQDC_FIXED)
2502 u32 rqdc_reg;
2503 u32 rqfd;
94f54703 2504 u32 rqfd_start;
845c6c95
SR		 2505 u32 rqfd_average;
2506 int loopi = 0;
94f54703
SR		 2507 char str[] = "Auto calibration -";
2508 char slash[] = "\\|/-\\|/-";
4037ed3b
SR		 2509
2510 /*------------------------------------------------------------------
2511 * Test to determine the best read clock delay tuning bits.
2512 *
2513 * Before the DDR controller can be used, the read clock delay needs to be
2514 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2515 * This value cannot be hardcoded into the program because it changes
2516 * depending on the board's setup and environment.
2517 * To do this, all delay values are tested to see if they
2518 * work or not. By doing this, you get groups of fails with groups of
2519 * passing values. The idea is to find the start and end of a passing
2520 * window and take the center of it to use as the read clock delay.
2521 *
2522 * A failure has to be seen first so that when we hit a pass, we know
2523 * that it is truely the start of the window. If we get passing values
2524 * to start off with, we don't know if we are at the start of the window.
2525 *
2526 * The code assumes that a failure will always be found.
2527 * If a failure is not found, there is no easy way to get the middle
2528 * of the passing window. I guess we can pretty much pick any value
2529 * but some values will be better than others. Since the lowest speed
2530 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2531 * from experimentation it is safe to say you will always have a failure.
2532 *-----------------------------------------------------------------*/
94f54703
SR		 2533
2534 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2535 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2536
2537 puts(str);
2538
2539calibration_loop:
2540 mfsdram(SDRAM_RQDC, rqdc_reg);
2541 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2542 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
845c6c95
SR		 2543#else /* CONFIG_DDR_RQDC_FIXED */
2544 /*
2545 * On Katmai the complete auto-calibration somehow doesn't seem to
2546 * produce the best results, meaning optimal values for RQFD/RFFD.
2547 * This was discovered by GDA using a high bandwidth scope,
2548 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2549 * so now on Katmai "only" RFFD is auto-calibrated.
2550 */
2551 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2552#endif /* CONFIG_DDR_RQDC_FIXED */
4037ed3b
SR		 2553
2554 max_start = 0;
2555 min_end = 0;
2556 begin_rqfd[0] = 0;
2557 begin_rffd[0] = 0;
2558 begin_rqfd[1] = 0;
2559 begin_rffd[1] = 0;
2560 end_rqfd[0] = 0;
2561 end_rffd[0] = 0;
2562 end_rqfd[1] = 0;
2563 end_rffd[1] = 0;
2564 window_found = FALSE;
2565
2566 max_pass_length = 0;
2567 max_start = 0;
2568 max_end = 0;
2569 current_pass_length = 0;
2570 current_fail_length = 0;
2571 current_start = 0;
2572 window_found = FALSE;
2573 fail_found = FALSE;
2574 pass_found = FALSE;
2575
4037ed3b
SR		 2576 /*
2577 * get the delay line calibration register value
2578 */
2579 mfsdram(SDRAM_DLCR, dlycal);
2580 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2581
2582 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2583 mfsdram(SDRAM_RFDC, rfdc_reg);
2584 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2585
2586 /*------------------------------------------------------------------
2587 * Set the timing reg for the test.
2588 *-----------------------------------------------------------------*/
2589 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2590
4037ed3b
SR		 2591 /*------------------------------------------------------------------
2592 * See if the rffd value passed.
2593 *-----------------------------------------------------------------*/
94f54703 2594 if (short_mem_test()) {
4037ed3b
SR		 2595 if (fail_found == TRUE) {
2596 pass_found = TRUE;
2597 if (current_pass_length == 0)
2598 current_start = rffd;
2599
2600 current_fail_length = 0;
2601 current_pass_length++;
2602
2603 if (current_pass_length > max_pass_length) {
2604 max_pass_length = current_pass_length;
2605 max_start = current_start;
2606 max_end = rffd;
2607 }
2608 }
2609 } else {
2610 current_pass_length = 0;
2611 current_fail_length++;
2612
2613 if (current_fail_length >= (dly_val >> 2)) {
2614 if (fail_found == FALSE) {
2615 fail_found = TRUE;
2616 } else if (pass_found == TRUE) {
2617 window_found = TRUE;
2618 break;
2619 }
2620 }
2621 }
2622 } /* for rffd */
2623
4037ed3b
SR		 2624 /*------------------------------------------------------------------
2625 * Set the average RFFD value
2626 *-----------------------------------------------------------------*/
2627 rffd_average = ((max_start + max_end) >> 1);
2628
2629 if (rffd_average < 0)
2630 rffd_average = 0;
2631
2632 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2633 rffd_average = SDRAM_RFDC_RFFD_MAX;
2634 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2635 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2636
845c6c95 2637#if !defined(CONFIG_DDR_RQDC_FIXED)
4037ed3b
SR		 2638 max_pass_length = 0;
2639 max_start = 0;
2640 max_end = 0;
2641 current_pass_length = 0;
2642 current_fail_length = 0;
2643 current_start = 0;
2644 window_found = FALSE;
2645 fail_found = FALSE;
2646 pass_found = FALSE;
2647
2648 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2649 mfsdram(SDRAM_RQDC, rqdc_reg);
2650 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2651
2652 /*------------------------------------------------------------------
2653 * Set the timing reg for the test.
2654 *-----------------------------------------------------------------*/
2655 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2656
4037ed3b
SR		 2657 /*------------------------------------------------------------------
2658 * See if the rffd value passed.
2659 *-----------------------------------------------------------------*/
94f54703 2660 if (short_mem_test()) {
4037ed3b
SR		 2661 if (fail_found == TRUE) {
2662 pass_found = TRUE;
2663 if (current_pass_length == 0)
2664 current_start = rqfd;
2665
2666 current_fail_length = 0;
2667 current_pass_length++;
2668
2669 if (current_pass_length > max_pass_length) {
2670 max_pass_length = current_pass_length;
2671 max_start = current_start;
2672 max_end = rqfd;
2673 }
2674 }
2675 } else {
2676 current_pass_length = 0;
2677 current_fail_length++;
2678
2679 if (fail_found == FALSE) {
2680 fail_found = TRUE;
2681 } else if (pass_found == TRUE) {
2682 window_found = TRUE;
2683 break;
2684 }
2685 }
2686 }
2687
94f54703
SR		 2688 rqfd_average = ((max_start + max_end) >> 1);
2689
4037ed3b
SR		 2690 /*------------------------------------------------------------------
2691 * Make sure we found the valid read passing window. Halt if not
2692 *-----------------------------------------------------------------*/
2693 if (window_found == FALSE) {
94f54703
SR		 2694 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2695 putc('\b');
2696 putc(slash[loopi++ % 8]);
2697
2698 /* try again from with a different RQFD start value */
2699 rqfd_start++;
2700 goto calibration_loop;
2701 }
2702
2703 printf("\nERROR: Cannot determine a common read delay for the "
4037ed3b
SR		 2704 "DIMM(s) installed.\n");
2705 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2e205084 2706 ppc4xx_ibm_ddr2_register_dump();
a5d71e29 2707 spd_ddr_init_hang ();
4037ed3b
SR		 2708 }
2709
4037ed3b
SR		 2710 if (rqfd_average < 0)
2711 rqfd_average = 0;
2712
2713 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2714 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2715
4037ed3b
SR		 2716 mtsdram(SDRAM_RQDC,
2717 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2718 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2719
845c6c95
SR		 2720 blank_string(strlen(str));
2721#endif /* CONFIG_DDR_RQDC_FIXED */
2722
4037ed3b 2723 mfsdram(SDRAM_DLCR, val);
48e2b535 2724 debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
4037ed3b 2725 mfsdram(SDRAM_RQDC, val);
48e2b535 2726 debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
4037ed3b 2727 mfsdram(SDRAM_RFDC, val);
48e2b535 2728 debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
845c6c95 2729 mfsdram(SDRAM_RDCC, val);
48e2b535 2730 debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
4037ed3b
SR		 2731}
2732#else /* calibration test with hardvalues */
2733/*-----------------------------------------------------------------------------+
2734 * DQS_calibration_process.
2735 *-----------------------------------------------------------------------------*/
2736static void test(void)
2737{
2738 unsigned long dimm_num;
2739 unsigned long ecc_temp;
2740 unsigned long i, j;
2741 unsigned long *membase;
2742 unsigned long bxcf[MAXRANKS];
2743 unsigned long val;
2744 char window_found;
2745 char begin_found[MAXDIMMS];
2746 char end_found[MAXDIMMS];
2747 char search_end[MAXDIMMS];
2748 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2749 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2750 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2751 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2752 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2753 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2754 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2755 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2756 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2757 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2758 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2759 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2760 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2761 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2762 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2763 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2764 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2765
2766 /*------------------------------------------------------------------
2767 * Test to determine the best read clock delay tuning bits.
2768 *
2769 * Before the DDR controller can be used, the read clock delay needs to be
2770 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2771 * This value cannot be hardcoded into the program because it changes
2772 * depending on the board's setup and environment.
2773 * To do this, all delay values are tested to see if they
2774 * work or not. By doing this, you get groups of fails with groups of
2775 * passing values. The idea is to find the start and end of a passing
2776 * window and take the center of it to use as the read clock delay.
2777 *
2778 * A failure has to be seen first so that when we hit a pass, we know
2779 * that it is truely the start of the window. If we get passing values
2780 * to start off with, we don't know if we are at the start of the window.
2781 *
2782 * The code assumes that a failure will always be found.
2783 * If a failure is not found, there is no easy way to get the middle
2784 * of the passing window. I guess we can pretty much pick any value
2785 * but some values will be better than others. Since the lowest speed
2786 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2787 * from experimentation it is safe to say you will always have a failure.
2788 *-----------------------------------------------------------------*/
2789 mfsdram(SDRAM_MCOPT1, ecc_temp);
2790 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2791 mfsdram(SDRAM_MCOPT1, val);
2792 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2793 SDRAM_MCOPT1_MCHK_NON);
2794
2795 window_found = FALSE;
2796 begin_found[0] = FALSE;
2797 end_found[0] = FALSE;
2798 search_end[0] = FALSE;
2799 begin_found[1] = FALSE;
2800 end_found[1] = FALSE;
2801 search_end[1] = FALSE;
2802
2803 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2804 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2805
2806 /* Banks enabled */
2807 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2808
2809 /* Bank is enabled */
2810 membase =
2811 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2812
2813 /*------------------------------------------------------------------
2814 * Run the short memory test.
2815 *-----------------------------------------------------------------*/
2816 for (i = 0; i < NUMMEMTESTS; i++) {
2817 for (j = 0; j < NUMMEMWORDS; j++) {
2818 membase[j] = test[i][j];
2819 ppcDcbf((u32)&(membase[j]));
2820 }
2821 sync();
2822 for (j = 0; j < NUMMEMWORDS; j++) {
2823 if (membase[j] != test[i][j]) {
2824 ppcDcbf((u32)&(membase[j]));
2825 break;
2826 }
2827 ppcDcbf((u32)&(membase[j]));
2828 }
2829 sync();
2830 if (j < NUMMEMWORDS)
2831 break;
2832 }
2833
2834 /*------------------------------------------------------------------
2835 * See if the rffd value passed.
2836 *-----------------------------------------------------------------*/
2837 if (i < NUMMEMTESTS) {
2838 if ((end_found[dimm_num] == FALSE) &&
2839 (search_end[dimm_num] == TRUE)) {
2840 end_found[dimm_num] = TRUE;
2841 }
2842 if ((end_found[0] == TRUE) &&
2843 (end_found[1] == TRUE))
2844 break;
2845 } else {
2846 if (begin_found[dimm_num] == FALSE) {
2847 begin_found[dimm_num] = TRUE;
2848 search_end[dimm_num] = TRUE;
2849 }
2850 }
2851 } else {
2852 begin_found[dimm_num] = TRUE;
2853 end_found[dimm_num] = TRUE;
2854 }
2855 }
2856
2857 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2858 window_found = TRUE;
2859
2860 /*------------------------------------------------------------------
2861 * Make sure we found the valid read passing window. Halt if not
2862 *-----------------------------------------------------------------*/
2863 if (window_found == FALSE) {
2864 printf("ERROR: Cannot determine a common read delay for the "
2865 "DIMM(s) installed.\n");
a5d71e29 2866 spd_ddr_init_hang ();
4037ed3b
SR		 2867 }
2868
2869 /*------------------------------------------------------------------
2870 * Restore the ECC variable to what it originally was
2871 *-----------------------------------------------------------------*/
2872 mtsdram(SDRAM_MCOPT1,
2873 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2874 | ecc_temp);
2875}
f6b6c458
AG		 2876#endif /* !HARD_CODED_DQS */
2877#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
4037ed3b 2878
08250eb2
SR		 2879#else /* CONFIG_SPD_EEPROM */
2880
c821b5f1
GE		 2881/*-----------------------------------------------------------------------------
2882 * Function: initdram
59217bae
AG		 2883 * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2884 * The configuration is performed using static, compile-
c821b5f1 2885 * time parameters.
59217bae 2886 * Configures the PPC405EX(r) and PPC460EX/GT
c821b5f1 2887 *---------------------------------------------------------------------------*/
9973e3c6 2888phys_size_t initdram(int board_type)
c821b5f1 2889{
ec724f88
SR		 2890 /*
2891 * Only run this SDRAM init code once. For NAND booting
2892 * targets like Kilauea, we call initdram() early from the
2893 * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2894 * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2895 * which calls initdram() again. This time the controller
2896 * mustn't be reconfigured again since we're already running
2897 * from SDRAM.
2898 */
2899#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
c821b5f1
GE		 2900 unsigned long val;
2901
59217bae
AG		 2902#if defined(CONFIG_440)
2903 mtdcr(SDRAM_R0BAS, CONFIG_SYS_SDRAM_R0BAS);
2904 mtdcr(SDRAM_R1BAS, CONFIG_SYS_SDRAM_R1BAS);
2905 mtdcr(SDRAM_R2BAS, CONFIG_SYS_SDRAM_R2BAS);
2906 mtdcr(SDRAM_R3BAS, CONFIG_SYS_SDRAM_R3BAS);
2907 mtdcr(SDRAM_PLBADDULL, CONFIG_SYS_SDRAM_PLBADDULL); /* MQ0_BAUL */
2908 mtdcr(SDRAM_PLBADDUHB, CONFIG_SYS_SDRAM_PLBADDUHB); /* MQ0_BAUH */
2909 mtdcr(SDRAM_CONF1LL, CONFIG_SYS_SDRAM_CONF1LL);
2910 mtdcr(SDRAM_CONF1HB, CONFIG_SYS_SDRAM_CONF1HB);
2911 mtdcr(SDRAM_CONFPATHB, CONFIG_SYS_SDRAM_CONFPATHB);
2912#endif
2913
c821b5f1
GE		 2914 /* Set Memory Bank Configuration Registers */
2915
6d0f6bcf
JCPV		 2916 mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2917 mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2918 mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2919 mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
c821b5f1
GE		 2920
2921 /* Set Memory Clock Timing Register */
2922
6d0f6bcf 2923 mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
c821b5f1
GE		 2924
2925 /* Set Refresh Time Register */
2926
6d0f6bcf 2927 mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
c821b5f1
GE		 2928
2929 /* Set SDRAM Timing Registers */
2930
6d0f6bcf
JCPV		 2931 mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2932 mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2933 mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
c821b5f1
GE		 2934
2935 /* Set Mode and Extended Mode Registers */
2936
6d0f6bcf
JCPV		 2937 mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2938 mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
c821b5f1
GE		 2939
2940 /* Set Memory Controller Options 1 Register */
2941
6d0f6bcf 2942 mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
c821b5f1
GE		 2943
2944 /* Set Manual Initialization Control Registers */
2945
6d0f6bcf
JCPV		 2946 mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2947 mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2948 mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2949 mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2950 mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2951 mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2952 mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2953 mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2954 mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2955 mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2956 mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2957 mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2958 mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2959 mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2960 mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2961 mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
c821b5f1
GE		 2962
2963 /* Set On-Die Termination Registers */
2964
6d0f6bcf
JCPV		 2965 mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2966 mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2967 mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
c821b5f1
GE		 2968
2969 /* Set Write Timing Register */
2970
6d0f6bcf 2971 mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
c821b5f1
GE		 2972
2973 /*
2974 * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2975 * SDRAM0_MCOPT2[IPTR] = 1
2976 */
2977
2978 mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2979 SDRAM_MCOPT2_IPTR_EXECUTE));
2980
2981 /*
2982 * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2983 * completion of initialization.
2984 */
2985
2986 do {
2987 mfsdram(SDRAM_MCSTAT, val);
2988 } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2989
2990 /* Set Delay Control Registers */
2991
6d0f6bcf 2992 mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
f6b6c458
AG		 2993
2994#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
6d0f6bcf
JCPV		 2995 mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
2996 mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
2997 mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
f6b6c458 2998#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
c821b5f1
GE		 2999
3000 /*
3001 * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
3002 */
3003
3004 mfsdram(SDRAM_MCOPT2, val);
3005 mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
3006
59217bae
AG		 3007#if defined(CONFIG_440)
3008 /*
3009 * Program TLB entries with caches enabled, for best performace
3010 * while auto-calibrating and ECC generation
3011 */
3012 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
3013#endif
3014
f6b6c458
AG		 3015#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3016#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3017 /*------------------------------------------------------------------
3018 | DQS calibration.
3019 +-----------------------------------------------------------------*/
3020 DQS_autocalibration();
3021#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3022#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3023
e9c020df
SR		 3024 /*
3025 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
3026 * PowerPC440SP/SPe DDR2 application note:
3027 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
3028 */
3029 update_rdcc();
3030
c821b5f1 3031#if defined(CONFIG_DDR_ECC)
d24bd251 3032 do_program_ecc(0);
c821b5f1 3033#endif /* defined(CONFIG_DDR_ECC) */
2e205084 3034
59217bae
AG		 3035#if defined(CONFIG_440)
3036 /*
3037 * Now after initialization (auto-calibration and ECC generation)
3038 * remove the TLB entries with caches enabled and program again with
3039 * desired cache functionality
3040 */
3041 remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3042 program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3043#endif
3044
2e205084 3045 ppc4xx_ibm_ddr2_register_dump();
f6b6c458
AG		 3046
3047#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3048 /*
3049 * Clear potential errors resulting from auto-calibration.
3050 * If not done, then we could get an interrupt later on when
3051 * exceptions are enabled.
3052 */
3053 set_mcsr(get_mcsr());
3054#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3055
ec724f88 3056#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
c821b5f1 3057
6d0f6bcf 3058 return (CONFIG_SYS_MBYTES_SDRAM << 20);
c821b5f1 3059}
08250eb2 3060#endif /* CONFIG_SPD_EEPROM */
2e205084 3061
f6b6c458
AG		 3062#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3063#if defined(CONFIG_440)
3064u32 mfdcr_any(u32 dcr)
3065{
3066 u32 val;
3067
3068 switch (dcr) {
3069 case SDRAM_R0BAS + 0:
3070 val = mfdcr(SDRAM_R0BAS + 0);
3071 break;
3072 case SDRAM_R0BAS + 1:
3073 val = mfdcr(SDRAM_R0BAS + 1);
3074 break;
3075 case SDRAM_R0BAS + 2:
3076 val = mfdcr(SDRAM_R0BAS + 2);
3077 break;
3078 case SDRAM_R0BAS + 3:
3079 val = mfdcr(SDRAM_R0BAS + 3);
3080 break;
3081 default:
3082 printf("DCR %d not defined in case statement!!!\n", dcr);
3083 val = 0; /* just to satisfy the compiler */
3084 }
3085
3086 return val;
3087}
3088
3089void mtdcr_any(u32 dcr, u32 val)
3090{
3091 switch (dcr) {
3092 case SDRAM_R0BAS + 0:
3093 mtdcr(SDRAM_R0BAS + 0, val);
3094 break;
3095 case SDRAM_R0BAS + 1:
3096 mtdcr(SDRAM_R0BAS + 1, val);
3097 break;
3098 case SDRAM_R0BAS + 2:
3099 mtdcr(SDRAM_R0BAS + 2, val);
3100 break;
3101 case SDRAM_R0BAS + 3:
3102 mtdcr(SDRAM_R0BAS + 3, val);
3103 break;
3104 default:
3105 printf("DCR %d not defined in case statement!!!\n", dcr);
3106 }
3107}
3108#endif /* defined(CONFIG_440) */
f6b6c458
AG		 3109#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
3110
3111inline void ppc4xx_ibm_ddr2_register_dump(void)
2e205084 3112{
08250eb2 3113#if defined(DEBUG)
2e205084
GE		 3114 printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3115
3116#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3117 defined(CONFIG_460EX) || defined(CONFIG_460GT))
48e2b535
FR		 3118 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3119 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3120 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3121 PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
2e205084
GE		 3122#endif /* (defined(CONFIG_440SP) || ... */
3123#if defined(CONFIG_405EX)
3124 PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3125 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3126 PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3127 PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3128 PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3129 PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3130#endif /* defined(CONFIG_405EX) */
3131 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3132 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3133 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3134 PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3135 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3136 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3137 PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3138 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3139 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3140 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3141 PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3142 PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3143#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3144 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3145 PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3146 PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3147 /*
3148 * OPART is only used as a trigger register.
3149 *
3150 * No data is contained in this register, and reading or writing
3151 * to is can cause bad things to happen (hangs). Just skip it and
3152 * report "N/A".
3153 */
3154 printf("%20s = N/A\n", "SDRAM_OPART");
3155#endif /* defined(CONFIG_440SP) || ... */
3156 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3157 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3158 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3159 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3160 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3161 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3162 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3163 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3164 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3165 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3166 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3167 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3168 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3169 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3170 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3171 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3172 PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3173 PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3174 PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3175 PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3176 PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3177 PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3178 PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3179 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3180 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3181 PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3182 PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3183 PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
4fe5193d 3184 PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
2e205084
GE		 3185#if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3186 defined(CONFIG_460EX) || defined(CONFIG_460GT))
3187 PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3188#endif /* defined(CONFIG_440SP) || ... */
3189 PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3190 PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3191 PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
08250eb2
SR		 3192#endif /* defined(DEBUG) */
3193}
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