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46263f2d 1/*
1b387ef5 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
c609719b
WD		 3 *
4 * File Name: 405gp_pci.c
5 *
6 * Function: Initialization code for the 405GP PCI Configuration regs.
7 *
8 * Author: Mark Game
9 *
10 * Change Activity-
11 *
12 * Date Description of Change BY
13 * --------- --------------------- ---
14 * 09-Sep-98 Created MCG
15 * 02-Nov-98 Removed External arbiter selected message JWB
16 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
17 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
18 * from (0 to n) to (1 to n).
19 * 17-May-99 Port to Walnut JWB
20 * 17-Jun-99 Updated for VGA support JWB
21 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
22 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
23 * target latency timer values are not supported).
24 * Should be fixed in pass 2.
25 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
26 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
27 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
28 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
29 * really required after a reset since PMMxMAs are already
53677ef1 30 * disabled but is a good practice nonetheless. JWB
c609719b
WD		 31 * 12-Jun-01 stefan.roese@esd-electronics.com
32 * - PCI host/adapter handling reworked
33 * 09-Jul-01 stefan.roese@esd-electronics.com
34 * - PCI host now configures from device 0 (not 1) to max_dev,
35 * (host configures itself)
36 * - On CPCI-405 pci base address and size is generated from
37 * SDRAM and FLASH size (CFG regs not used anymore)
38 * - Some minor changes for CPCI-405-A (adapter version)
39 * 14-Sep-01 stefan.roese@esd-electronics.com
40 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
41 * 28-Sep-01 stefan.roese@esd-electronics.com
42 * - Changed pci master configuration for linux compatibility
43 * (no need for bios_fixup() anymore)
44 * 26-Feb-02 stefan.roese@esd-electronics.com
45 * - Bug fixed in pci configuration (Andrew May)
46 * - Removed pci class code init for CPCI405 board
47 * 15-May-02 stefan.roese@esd-electronics.com
48 * - New vga device handling
49 * 29-May-02 stefan.roese@esd-electronics.com
50 * - PCI class code init added (if defined)
51 *----------------------------------------------------------------------------*/
52
53#include <common.h>
54#include <command.h>
3048bcbf 55#include <asm/4xx_pci.h>
c609719b 56#include <asm/processor.h>
1095493a 57#include <asm/io.h>
c609719b 58#include <pci.h>
85043159 59#include <asm/ppc4xx.h>
c609719b 60
5a1c9ff0
MF		 61#ifdef CONFIG_PCI
62
d87080b7
WD		 63DECLARE_GLOBAL_DATA_PTR;
64
a760b020
SR		 65#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
66
a760b020
SR		 67/*#define DEBUG*/
68
5a1c9ff0
MF		 69/*
70 * Board-specific pci initialization
71 * Platform code can reimplement pci_pre_init() if needed
72 */
73int __pci_pre_init(struct pci_controller *hose)
74{
a760b020 75#if defined(CONFIG_405EP)
123f102e
MF		 76 /*
77 * Enable the internal PCI arbiter by default.
78 *
79 * On 405EP CPUs the internal arbiter can be controlled
80 * by the I2C strapping EEPROM. If you want to do so
81 * or if you want to disable the arbiter pci_pre_init()
82 * must be reimplemented without enabling the arbiter.
83 * The arbiter is enabled in this place because of
84 * compatibility reasons.
85 */
d1c3b275 86 mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
123f102e
MF		 87#endif /* CONFIG_405EP */
88
5a1c9ff0
MF		 89 return 1;
90}
a760b020
SR		 91int pci_pre_init(struct pci_controller *hose)
92 __attribute__((weak, alias("__pci_pre_init")));
c609719b 93
d0a1364f
MF		 94int __is_pci_host(struct pci_controller *hose)
95{
96#if defined(CONFIG_405GP)
d1c3b275 97 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
d0a1364f
MF		 98 return 1;
99#elif defined (CONFIG_405EP)
d1c3b275 100 if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
d0a1364f
MF		 101 return 1;
102#endif
103 return 0;
104}
105int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
106
c609719b
WD		 107/*-----------------------------------------------------------------------------+
108 * pci_init. Initializes the 405GP PCI Configuration regs.
109 *-----------------------------------------------------------------------------*/
110void pci_405gp_init(struct pci_controller *hose)
111{
c609719b
WD		 112 int i, reg_num = 0;
113 bd_t *bd = gd->bd;
114
115 unsigned short temp_short;
6d0f6bcf 116 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
99bcf14d 117#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
fddae7b8 118 char *ptmla_str, *ptmms_str;
2076d0a1 119#endif
6d0f6bcf
JCPV		 120 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
121 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
adf32adb
TR		 122#if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
123 || defined(CONFIG_TARGET_MIP405T)
c609719b
WD		 124 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
125 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
126 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
127 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
128#else
129 unsigned long pmmla[3] = {0x80000000, 0,0};
130 unsigned long pmmma[3] = {0xC0000001, 0,0};
131 unsigned long pmmpcila[3] = {0x80000000, 0,0};
132 unsigned long pmmpciha[3] = {0x00000000, 0,0};
5e746fce
SR		 133#endif
134#ifdef CONFIG_PCI_PNP
135#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
136 char *s;
137#endif
c609719b
WD		 138#endif
139
99bcf14d 140#if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
fddae7b8
SR		 141 ptmla_str = getenv("ptm1la");
142 ptmms_str = getenv("ptm1ms");
143 if(NULL != ptmla_str && NULL != ptmms_str ) {
93e14596 144 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
fddae7b8
SR		 145 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
146 }
147
148 ptmla_str = getenv("ptm2la");
149 ptmms_str = getenv("ptm2ms");
150 if(NULL != ptmla_str && NULL != ptmms_str ) {
93e14596 151 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
fddae7b8
SR		 152 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
153 }
154#endif
155
c609719b
WD		 156 /*
157 * Register the hose
158 */
159 hose->first_busno = 0;
160 hose->last_busno = 0xff;
161
162 /* ISA/PCI I/O space */
163 pci_set_region(hose->regions + reg_num++,
164 MIN_PCI_PCI_IOADDR,
165 MIN_PLB_PCI_IOADDR,
166 0x10000,
167 PCI_REGION_IO);
168
169 /* PCI I/O space */
170 pci_set_region(hose->regions + reg_num++,
171 0x00800000,
172 0xe8800000,
173 0x03800000,
174 PCI_REGION_IO);
175
176 reg_num = 2;
177
178 /* Memory spaces */
179 for (i=0; i<2; i++)
180 if (ptmms[i] & 1)
181 {
182 if (!i) hose->pci_fb = hose->regions + reg_num;
183
184 pci_set_region(hose->regions + reg_num++,
185 ptmpcila[i], ptmla[i],
186 ~(ptmms[i] & 0xfffff000) + 1,
187 PCI_REGION_MEM |
ff4e66e9 188 PCI_REGION_SYS_MEMORY);
c609719b
WD		 189 }
190
191 /* PCI memory spaces */
192 for (i=0; i<3; i++)
193 if (pmmma[i] & 1)
194 {
195 pci_set_region(hose->regions + reg_num++,
196 pmmpcila[i], pmmla[i],
197 ~(pmmma[i] & 0xfffff000) + 1,
198 PCI_REGION_MEM);
199 }
200
201 hose->region_count = reg_num;
202
203 pci_setup_indirect(hose,
204 PCICFGADR,
205 PCICFGDATA);
206
207 if (hose->pci_fb)
208 pciauto_region_init(hose->pci_fb);
209
5a1c9ff0 210 /* Let board change/modify hose & do initial checks */
a760b020 211 if (pci_pre_init(hose) == 0) {
5a1c9ff0
MF		 212 printf("PCI: Board-specific initialization failed.\n");
213 printf("PCI: Configuration aborted.\n");
214 return;
215 }
216
c609719b
WD		 217 pci_register_hose(hose);
218
219 /*--------------------------------------------------------------------------+
220 * 405GP PCI Master configuration.
221 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
222 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
223 * Use byte reversed out routines to handle endianess.
224 *--------------------------------------------------------------------------*/
f3e0de60 225 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
c609719b
WD		 226 out32r(PMM0LA, pmmla[0]);
227 out32r(PMM0PCILA, pmmpcila[0]);
228 out32r(PMM0PCIHA, pmmpciha[0]);
229 out32r(PMM0MA, pmmma[0]);
230
231 /*--------------------------------------------------------------------------+
232 * PMM1 is not used. Initialize them to zero.
233 *--------------------------------------------------------------------------*/
f3e0de60 234 out32r(PMM1MA, (pmmma[1]&~0x1));
c609719b
WD		 235 out32r(PMM1LA, pmmla[1]);
236 out32r(PMM1PCILA, pmmpcila[1]);
237 out32r(PMM1PCIHA, pmmpciha[1]);
238 out32r(PMM1MA, pmmma[1]);
239
240 /*--------------------------------------------------------------------------+
241 * PMM2 is not used. Initialize them to zero.
242 *--------------------------------------------------------------------------*/
8bde7f77 243 out32r(PMM2MA, (pmmma[2]&~0x1));
c609719b
WD		 244 out32r(PMM2LA, pmmla[2]);
245 out32r(PMM2PCILA, pmmpcila[2]);
246 out32r(PMM2PCIHA, pmmpciha[2]);
247 out32r(PMM2MA, pmmma[2]);
248
249 /*--------------------------------------------------------------------------+
250 * 405GP PCI Target configuration. (PTM1)
251 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
252 *--------------------------------------------------------------------------*/
253 out32r(PTM1LA, ptmla[0]); /* insert address */
254 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
4654af27 255 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
c609719b
WD		 256
257 /*--------------------------------------------------------------------------+
258 * 405GP PCI Target configuration. (PTM2)
259 *--------------------------------------------------------------------------*/
260 out32r(PTM2LA, ptmla[1]); /* insert address */
4654af27
WD		 261 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
262
c609719b
WD		 263 if (ptmms[1] == 0)
264 {
265 out32r(PTM2MS, 0x00000001); /* set enable bit */
266 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
267 out32r(PTM2MS, 0x00000000); /* disable */
268 }
269 else
270 {
271 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
272 }
273
274 /*
275 * Insert Subsystem Vendor and Device ID
276 */
6d0f6bcf 277 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
c609719b 278#ifdef CONFIG_CPCI405
d0a1364f 279 if (is_pci_host(hose))
6d0f6bcf 280 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
c609719b 281 else
6d0f6bcf 282 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
c609719b 283#else
6d0f6bcf 284 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
c609719b
WD		 285#endif
286
287 /*
288 * Insert Class-code
289 */
6d0f6bcf
JCPV		 290#ifdef CONFIG_SYS_PCI_CLASSCODE
291 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
292#endif /* CONFIG_SYS_PCI_CLASSCODE */
c609719b
WD		 293
294 /*--------------------------------------------------------------------------+
8ed44d91 295 * If PCI speed = 66MHz, set 66MHz capable bit.
c609719b
WD		 296 *--------------------------------------------------------------------------*/
297 if (bd->bi_pci_busfreq >= 66000000) {
298 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
299 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
300 }
301
302#if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
4654af27 303#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
d0a1364f 304 if (is_pci_host(hose) ||
5e746fce 305 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
c609719b
WD		 306#endif
307 {
308 /*--------------------------------------------------------------------------+
309 * Write the 405GP PCI Configuration regs.
310 * Enable 405GP to be a master on the PCI bus (PMM).
311 * Enable 405GP to act as a PCI memory target (PTM).
312 *--------------------------------------------------------------------------*/
313 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
314 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
315 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
316 }
317#endif
318
632e9b67
MF		 319#if defined(CONFIG_405EP)
320 /*
321 * on ppc405ep vendor/device id is not set
322 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
323 * are the correct values.
324 */
325 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
326 pci_write_config_word(PCIDEVID_405GP,
327 PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
428c5639
SR		 328#endif
329
c609719b
WD		 330 /*
331 * Set HCE bit (Host Configuration Enabled)
332 */
333 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
334 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
335
336#ifdef CONFIG_PCI_PNP
337 /*--------------------------------------------------------------------------+
338 * Scan the PCI bus and configure devices found.
339 *--------------------------------------------------------------------------*/
340#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
d0a1364f 341 if (is_pci_host(hose) ||
5e746fce 342 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
c609719b
WD		 343#endif
344 {
345#ifdef CONFIG_PCI_SCAN_SHOW
346 printf("PCI: Bus Dev VenId DevId Class Int\n");
347#endif
c609719b
WD		 348 hose->last_busno = pci_hose_scan(hose);
349 }
350#endif /* CONFIG_PCI_PNP */
351
352}
353
354/*
7817cb20 355 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
c609719b
WD		 356 * be set as an Adapter.
357 *
358 * I (Andrew May) don't know what we should do here, but I don't want
359 * the auto setup of a PCI device disabling what is done pci_405gp_init
360 * as has happened before.
361 */
362void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
363 struct pci_config_table *entry)
364{
365#ifdef DEBUG
8bde7f77 366 printf("405gp_setup_bridge\n");
c609719b
WD		 367#endif
368}
369
370/*
371 *
372 */
373
374void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
375{
376 unsigned char int_line = 0xff;
377
378 /*
379 * Write pci interrupt line register (cpci405 specific)
380 */
381 switch (PCI_DEV(dev) & 0x03)
382 {
383 case 0:
384 int_line = 27 + 2;
385 break;
386 case 1:
387 int_line = 27 + 3;
388 break;
389 case 2:
390 int_line = 27 + 0;
391 break;
392 case 3:
393 int_line = 27 + 1;
394 break;
395 }
396
397 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
398}
399
400void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
401 struct pci_config_table *entry)
402{
403 unsigned int cmdstat = 0;
404
f3fecfe6 405 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
c609719b
WD		 406
407 /* always enable io space on vga boards */
408 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
409 cmdstat |= PCI_COMMAND_IO;
410 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
411}
412
adf32adb
TR		 413#if !(defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \
414 || defined(CONFIG_TARGET_MIP405T))
c609719b
WD		 415
416/*
417 *As is these functs get called out of flash Not a horrible
418 *thing, but something to keep in mind. (no statics?)
419 */
420static struct pci_config_table pci_405gp_config_table[] = {
421/*if VendID is 0 it terminates the table search (ie Walnut)*/
6d0f6bcf
JCPV		 422#ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
423 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
c609719b
WD		 424 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
425#endif
426 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
427 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
428
429 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
430 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
431
432 { }
433};
434
435static struct pci_controller hose = {
436 fixup_irq: pci_405gp_fixup_irq,
437 config_table: pci_405gp_config_table,
438};
439
ad10dd9a 440void pci_init_board(void)
c609719b
WD		 441{
442 /*we want the ptrs to RAM not flash (ie don't use init list)*/
443 hose.fixup_irq = pci_405gp_fixup_irq;
444 hose.config_table = pci_405gp_config_table;
445 pci_405gp_init(&hose);
446}
447
448#endif
449
c609719b
WD		 450#endif /* CONFIG_405GP */
451
452/*-----------------------------------------------------------------------------+
453 * CONFIG_440
454 *-----------------------------------------------------------------------------*/
5a1c9ff0 455#if defined(CONFIG_440)
c609719b 456
db643773 457#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
c609719b 458static struct pci_controller ppc440_hose = {0};
db643773 459#endif
c609719b 460
9a81c612
SR		 461/*
462 * This routine is called to determine if a pci scan should be
463 * performed. With various hardware environments (especially cPCI and
464 * PPMC) it's insufficient to depend on the state of the arbiter enable
465 * bit in the strap register, or generic host/adapter assumptions.
466 *
467 * Rather than hard-code a bad assumption in the general 440 code, the
468 * 440 pci code requires the board to decide at runtime.
469 *
470 * Return 0 for adapter mode, non-zero for host (monarch) mode.
471 *
472 * Weak default implementation: "Normal" boards implement the PCI
473 * host functionality. This can be overridden for PCI adapter boards.
474 */
475int __is_pci_host(struct pci_controller *hose)
476{
477 return 1;
478}
479int is_pci_host(struct pci_controller *hose)
480 __attribute__((weak, alias("__is_pci_host")));
c609719b 481
a760b020
SR		 482#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
483 defined(CONFIG_440GR) || defined(CONFIG_440GRX)
484
485#if defined(CONFIG_SYS_PCI_TARGET_INIT)
1095493a 486/*
a760b020 487 * pci_target_init
1095493a 488 *
a760b020
SR		 489 * The bootstrap configuration provides default settings for the pci
490 * inbound map (PIM). But the bootstrap config choices are limited and
491 * may not be sufficient for a given board.
1095493a 492 */
1095493a
SR		 493void __pci_target_init(struct pci_controller *hose)
494{
495 /*
496 * Set up Direct MMIO registers
497 */
498
499 /*
500 * PowerPC440 EP PCI Master configuration.
501 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
502 * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
503 * Use byte reversed out routines to handle endianess.
504 * Make this region non-prefetchable.
505 */
506 /* PMM0 Mask/Attribute - disabled b4 setting */
507 out_le32((void *)PCIL0_PMM0MA, 0x00000000);
508 /* PMM0 Local Address */
509 out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
510 /* PMM0 PCI Low Address */
511 out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
512 /* PMM0 PCI High Address */
513 out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
514 /* 512M + No prefetching, and enable region */
515 out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
516
517 /* PMM1 Mask/Attribute - disabled b4 setting */
518 out_le32((void *)PCIL0_PMM1MA, 0x00000000);
519 /* PMM1 Local Address */
520 out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
521 /* PMM1 PCI Low Address */
522 out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
523 /* PMM1 PCI High Address */
524 out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
525 /* 512M + No prefetching, and enable region */
526 out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
527
528 out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
529 out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */
530 out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
531 out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */
532
533 /*
534 * Set up Configuration registers
535 */
536
537 /* Program the board's subsystem id/vendor id */
538 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
539 CONFIG_SYS_PCI_SUBSYS_VENDORID);
540 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
541
542 /* Configure command register as bus master */
543 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
544
545 /* 240nS PCI clock */
546 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
547
548 /* No error reporting */
549 pci_write_config_word(0, PCI_ERREN, 0);
550
551 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
552}
a760b020
SR		 553#endif /* CONFIG_SYS_PCI_TARGET_INIT */
554
555/*
556 * pci_pre_init
557 *
558 * This routine is called just prior to registering the hose and gives
559 * the board the opportunity to check things. Returning a value of zero
560 * indicates that things are bad & PCI initialization should be aborted.
561 *
562 * Different boards may wish to customize the pci controller structure
563 * (add regions, override default access routines, etc) or perform
564 * certain pre-initialization actions.
565 *
566 */
567int __pci_pre_init(struct pci_controller *hose)
568{
569 u32 reg;
570
571 /*
572 * Set priority for all PLB3 devices to 0.
573 * Set PLB3 arbiter to fair mode.
574 */
5e7abce9
SR		 575 mfsdr(SDR0_AMP1, reg);
576 mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
577 reg = mfdcr(PLB3A0_ACR);
578 mtdcr(PLB3A0_ACR, reg | 0x80000000);
a760b020
SR		 579
580 /*
581 * Set priority for all PLB4 devices to 0.
582 */
5e7abce9
SR		 583 mfsdr(SDR0_AMP0, reg);
584 mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
585 reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
586 mtdcr(PLB4A0_ACR, reg);
a760b020
SR		 587
588 /*
589 * Set Nebula PLB4 arbiter to fair mode.
590 */
591 /* Segment0 */
5e7abce9
SR		 592 reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
593 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
594 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
595 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
596 mtdcr(PLB4A0_ACR, reg);
a760b020
SR		 597
598 /* Segment1 */
5e7abce9
SR		 599 reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
600 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
601 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
602 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
603 mtdcr(PLB4A1_ACR, reg);
a760b020
SR		 604
605#if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
606 hose->fixup_irq = board_pci_fixup_irq;
607#endif
608
609 return 1;
610}
611
1095493a 612#else /* defined(CONFIG_440EP) ... */
a760b020
SR		 613
614#if defined(CONFIG_SYS_PCI_TARGET_INIT)
1095493a
SR		 615void __pci_target_init(struct pci_controller * hose)
616{
617 /*
618 * Disable everything
619 */
620 out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
621 out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
622 out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
623 out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
624
625 /*
626 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
627 * strapping options do not support sizes such as 128/256 MB.
628 */
629 out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
630 out_le32((void *)PCIL0_PIM0LAH, 0);
631 out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
632 out_le32((void *)PCIL0_BAR0, 0);
633
634 /*
635 * Program the board's subsystem id/vendor id
636 */
637 out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
638 out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
639
640 out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
641 PCI_COMMAND_MEMORY);
642}
a760b020
SR		 643#endif /* CONFIG_SYS_PCI_TARGET_INIT */
644
645int __pci_pre_init(struct pci_controller *hose)
646{
647 /*
648 * This board is always configured as the host & requires the
649 * PCI arbiter to be enabled.
650 */
651 if (!pci_arbiter_enabled()) {
652 printf("PCI: PCI Arbiter disabled!\n");
653 return 0;
654 }
655
656 return 1;
657}
658
1095493a 659#endif /* defined(CONFIG_440EP) ... */
a760b020
SR		 660
661#if defined(CONFIG_SYS_PCI_TARGET_INIT)
1095493a
SR		 662void pci_target_init(struct pci_controller * hose)
663 __attribute__((weak, alias("__pci_target_init")));
a760b020 664#endif /* CONFIG_SYS_PCI_TARGET_INIT */
1095493a 665
a760b020
SR		 666int pci_pre_init(struct pci_controller *hose)
667 __attribute__((weak, alias("__pci_pre_init")));
1095493a 668
6c70049b
SR		 669#if defined(CONFIG_SYS_PCI_MASTER_INIT)
670void __pci_master_init(struct pci_controller *hose)
671{
672 u16 reg;
673
674 /*
675 * Write the PowerPC440 EP PCI Configuration regs.
676 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
677 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
678 */
679 pci_read_config_word(0, PCI_COMMAND, &reg);
680 pci_write_config_word(0, PCI_COMMAND, reg |
681 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
682}
683void pci_master_init(struct pci_controller *hose)
684 __attribute__((weak, alias("__pci_master_init")));
685#endif /* CONFIG_SYS_PCI_MASTER_INIT */
686
db643773 687#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
e5d5ed4b 688static int pci_440_init (struct pci_controller *hose)
c609719b
WD		 689{
690 int reg_num = 0;
c609719b 691
5568e613 692#ifndef CONFIG_DISABLE_PISE_TEST
c609719b
WD		 693 /*--------------------------------------------------------------------------+
694 * The PCI initialization sequence enable bit must be set ... if not abort
3c74e32a 695 * pci setup since updating the bit requires chip reset.
c609719b 696 *--------------------------------------------------------------------------*/
6c5879f3 697#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
5568e613
SR		 698 unsigned long strap;
699
d1c3b275 700 mfsdr(SDR0_SDSTP1,strap);
6e7fb6ea 701 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
3c74e32a
WD		 702 printf("PCI: SDR0_STRP1[PISE] not set.\n");
703 printf("PCI: Configuration aborted.\n");
7f191393 704 return -1;
3c74e32a 705 }
5568e613
SR		 706#elif defined(CONFIG_440GP)
707 unsigned long strap;
708
d1c3b275 709 strap = mfdcr(CPC0_STRP1);
6e7fb6ea 710 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
3c74e32a
WD		 711 printf("PCI: CPC0_STRP1[PISE] not set.\n");
712 printf("PCI: Configuration aborted.\n");
7f191393 713 return -1;
3c74e32a
WD		 714 }
715#endif
5568e613
SR		 716#endif /* CONFIG_DISABLE_PISE_TEST */
717
c609719b
WD		 718 /*--------------------------------------------------------------------------+
719 * PCI controller init
720 *--------------------------------------------------------------------------*/
721 hose->first_busno = 0;
7f191393 722 hose->last_busno = 0;
c609719b 723
fbb0b559 724 /* PCI I/O space */
c609719b
WD		 725 pci_set_region(hose->regions + reg_num++,
726 0x00000000,
ddc922ff 727 PCIL0_IOBASE,
6e7fb6ea
SR		 728 0x10000,
729 PCI_REGION_IO);
c609719b 730
fbb0b559 731 /* PCI memory space */
c609719b 732 pci_set_region(hose->regions + reg_num++,
6d0f6bcf
JCPV		 733 CONFIG_SYS_PCI_TARGBASE,
734 CONFIG_SYS_PCI_MEMBASE,
735#ifdef CONFIG_SYS_PCI_MEMSIZE
736 CONFIG_SYS_PCI_MEMSIZE,
899620c2 737#else
6e7fb6ea 738 0x10000000,
899620c2 739#endif
6e7fb6ea 740 PCI_REGION_MEM );
fbb0b559
MB		 741
742#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
743 defined(CONFIG_PCI_SYS_MEM_SIZE)
744 /* System memory space */
745 pci_set_region(hose->regions + reg_num++,
746 CONFIG_PCI_SYS_MEM_BUS,
747 CONFIG_PCI_SYS_MEM_PHYS,
748 CONFIG_PCI_SYS_MEM_SIZE,
ff4e66e9 749 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
fbb0b559
MB		 750#endif
751
c609719b
WD		 752 hose->region_count = reg_num;
753
ddc922ff 754 pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
c609719b 755
6e7fb6ea 756 /* Let board change/modify hose & do initial checks */
a760b020 757 if (pci_pre_init(hose) == 0) {
6e7fb6ea
SR		 758 printf("PCI: Board-specific initialization failed.\n");
759 printf("PCI: Configuration aborted.\n");
7f191393 760 return -1;
6e7fb6ea 761 }
c609719b
WD		 762
763 pci_register_hose( hose );
764
765 /*--------------------------------------------------------------------------+
766 * PCI target init
767 *--------------------------------------------------------------------------*/
6d0f6bcf 768#if defined(CONFIG_SYS_PCI_TARGET_INIT)
c609719b
WD		 769 pci_target_init(hose); /* Let board setup pci target */
770#else
ddc922ff
NG		 771 out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
772 out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
773 out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
c609719b
WD		 774#endif
775
8ac41e3e
SR		 776#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
777 defined(CONFIG_460EX) || defined(CONFIG_460GT)
ddc922ff
NG		 778 out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
779 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
780#elif defined(PCIL0_BRDGOPT1)
781 out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
782 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */
3c74e32a 783#endif
c609719b
WD		 784
785 /*--------------------------------------------------------------------------+
786 * PCI master init: default is one 256MB region for PCI memory:
6d0f6bcf 787 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
c609719b 788 *--------------------------------------------------------------------------*/
6d0f6bcf 789#if defined(CONFIG_SYS_PCI_MASTER_INIT)
c609719b
WD		 790 pci_master_init(hose); /* Let board setup pci master */
791#else
ddc922ff
NG		 792 out32r( PCIL0_POM0SA, 0 ); /* disable */
793 out32r( PCIL0_POM1SA, 0 ); /* disable */
794 out32r( PCIL0_POM2SA, 0 ); /* disable */
f8853d10 795#if defined(CONFIG_440SPE)
ddc922ff
NG		 796 out32r( PCIL0_POM0LAL, 0x10000000 );
797 out32r( PCIL0_POM0LAH, 0x0000000c );
f8853d10 798#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
ddc922ff
NG		 799 out32r( PCIL0_POM0LAL, 0x20000000 );
800 out32r( PCIL0_POM0LAH, 0x0000000c );
6c5879f3 801#else
ddc922ff
NG		 802 out32r( PCIL0_POM0LAL, 0x00000000 );
803 out32r( PCIL0_POM0LAH, 0x00000003 );
6c5879f3 804#endif
ddc922ff
NG		 805 out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
806 out32r( PCIL0_POM0PCIAH, 0x00000000 );
807 out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
808 out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
c609719b
WD		 809#endif
810
811 /*--------------------------------------------------------------------------+
812 * PCI host configuration -- we don't make any assumptions here ... the
6e7fb6ea
SR		 813 * _board_must_indicate_ what to do -- there's just too many runtime
814 * scenarios in environments like cPCI, PPMC, etc. to make a determination
815 * based on hard-coded values or state of arbiter enable.
c609719b 816 *--------------------------------------------------------------------------*/
6e7fb6ea 817 if (is_pci_host(hose)) {
c609719b 818#ifdef CONFIG_PCI_SCAN_SHOW
6e7fb6ea 819 printf("PCI: Bus Dev VenId DevId Class Int\n");
c609719b 820#endif
887e2ec9
SR		 821#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
822 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
ddc922ff 823 out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
c157d8e2 824#endif
6e7fb6ea
SR		 825 hose->last_busno = pci_hose_scan(hose);
826 }
7f191393 827 return hose->last_busno;
c609719b 828}
db643773 829#endif
c609719b 830
ad10dd9a 831void pci_init_board(void)
c609719b 832{
db643773 833 int busno = 0;
7f191393 834
db643773
SR		 835 /*
836 * Only init PCI when either master or target functionality
837 * is selected.
838 */
839#if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
e5d5ed4b
WD		 840 busno = pci_440_init(&ppc440_hose);
841 if (busno < 0)
842 return;
db643773 843#endif
59d1bda7
DE		 844#if (defined(CONFIG_440SPE) || \
845 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
846 !defined(CONFIG_PCI_DISABLE_PCIE)
7f191393 847 pcie_setup_hoses(busno + 1);
692519b1 848#endif
c609719b
WD		 849}
850
5a1c9ff0 851#endif /* CONFIG_440 */
1d7b874e
SR		 852
853#if defined(CONFIG_405EX)
854void pci_init_board(void)
855{
856#ifdef CONFIG_PCI_SCAN_SHOW
857 printf("PCI: Bus Dev VenId DevId Class Int\n");
858#endif
859 pcie_setup_hoses(0);
860}
861#endif /* CONFIG_405EX */
862
5a1c9ff0 863#endif /* CONFIG_PCI */
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