[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / ecc.c

/*
 *    Copyright (c) 2008 Nuovation System Designs, LLC
 *      Grant Erickson <gerickson@nuovations.com>
 *
 *    (C) Copyright 2005-2009
 *    Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 *    (C) Copyright 2002
 *    Jun Gu, Artesyn Technology, jung@artesyncp.com
 *
 *    (C) Copyright 2001
 *    Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 *    Description:
 *	This file implements generic DRAM ECC initialization for
 *	PowerPC processors using a SDRAM DDR/DDR2 controller,
 *	including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
 *	460EX/GT.
 */

#include <common.h>
#include <asm/ppc4xx.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/cache.h>

#include "ecc.h"

#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \
    defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC)

#if defined(CONFIG_405EX)
/*
 * Currently only 405EX uses 16bit data bus width as an alternative
 * option to 32bit data width (SDRAM0_MCOPT1_WDTH)
 */
#define SDRAM_DATA_ALT_WIDTH	2
#else
#define SDRAM_DATA_ALT_WIDTH	8
#endif

static void wait_ddr_idle(void)
{
	u32 val;

	do {
		mfsdram(SDRAM_MCSTAT, val);
	} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
}

static void program_ecc_addr(unsigned long start_address,
			     unsigned long num_bytes,
			     unsigned long tlb_word2_i_value)
{
	unsigned long current_address;
	unsigned long end_address;
	unsigned long address_increment;
	unsigned long mcopt1;
	char str[] = "ECC generation -";
	char slash[] = "\\|/-\\|/-";
	int loop = 0;
	int loopi = 0;

	current_address = start_address;
	mfsdram(SDRAM_MCOPT1, mcopt1);
	if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
		mtsdram(SDRAM_MCOPT1,
			(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
		sync();
		eieio();
		wait_ddr_idle();

		puts(str);

#ifdef CONFIG_440
		if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
#endif
			/* ECC bit set method for non-cached memory */
			if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
				address_increment = 4;
			else
				address_increment = SDRAM_DATA_ALT_WIDTH;
			end_address = current_address + num_bytes;

			while (current_address < end_address) {
				*((unsigned long *)current_address) = 0;
				current_address += address_increment;

				if ((loop++ % (2 << 20)) == 0) {
					putc('\b');
					putc(slash[loopi++ % 8]);
				}
			}
#ifdef CONFIG_440
		} else {
			/* ECC bit set method for cached memory */
			dcbz_area(start_address, num_bytes);
			/* Write modified dcache lines back to memory */
			clean_dcache_range(start_address, start_address + num_bytes);
		}
#endif /* CONFIG_440 */

		blank_string(strlen(str));

		sync();
		eieio();
		wait_ddr_idle();

		/* clear ECC error repoting registers */
		mtsdram(SDRAM_ECCES, 0xffffffff);
#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
		/*
		 * IBM DDR(1) core (440GX):
		 * Clear Mx bits in SDRAM0_BESR0/1
		 */
		mtsdram(SDRAM0_BESR0, 0xffffffff);
		mtsdram(SDRAM0_BESR1, 0xffffffff);
#elif defined(CONFIG_440)
		/*
		 * 440/460 DDR2 core:
		 * Clear EMID (Error PLB Master ID) in MQ0_ESL
		 */
		mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
#else
		/*
		 * 405EX(r) DDR2 core:
		 * Clear M0ID (Error PLB Master ID) in SDRAM_BESR
		 */
		mtsdram(SDRAM_BESR, 0xf0000000);
#endif

		mtsdram(SDRAM_MCOPT1,
			(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
		sync();
		eieio();
		wait_ddr_idle();
	}
}

#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
void ecc_init(unsigned long * const start, unsigned long size)
{
	/*
	 * Init ECC with cache disabled (on PPC's with IBM DDR
	 * controller (non DDR2), not tested with cache enabled yet
	 */
	program_ecc_addr((u32)start, size, TLB_WORD2_I_ENABLE);
}
#endif

#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
void do_program_ecc(unsigned long tlb_word2_i_value)
{
	unsigned long mcopt1;
	unsigned long mcopt2;
	unsigned long mcstat;
	phys_size_t memsize = sdram_memsize();

	if (memsize > CONFIG_MAX_MEM_MAPPED) {
		printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
		return;
	}

	mfsdram(SDRAM_MCOPT1, mcopt1);
	mfsdram(SDRAM_MCOPT2, mcopt2);

	if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
		/* DDR controller must be enabled and not in self-refresh. */
		mfsdram(SDRAM_MCSTAT, mcstat);
		if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
		    && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
		    && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
			== (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {

			program_ecc_addr(0, memsize, tlb_word2_i_value);
		}
	}
}
#endif

#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */
#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */
Commit	Line	Data
c821b5f1 GE	1	/*
	2	* Copyright (c) 2008 Nuovation System Designs, LLC
	3	* Grant Erickson <gerickson@nuovations.com>
	4	*
fb95169e	5	* (C) Copyright 2005-2009
c821b5f1 GE	6	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	7	*
	8	* (C) Copyright 2002
	9	* Jun Gu, Artesyn Technology, jung@artesyncp.com
	10	*
	11	* (C) Copyright 2001
	12	* Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
	13	*
1a459660	14	* SPDX-License-Identifier: GPL-2.0+
c821b5f1 GE	15	*
	16	* Description:
	17	* This file implements generic DRAM ECC initialization for
	18	* PowerPC processors using a SDRAM DDR/DDR2 controller,
	19	* including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and
	20	* 460EX/GT.
	21	*/
	22
	23	#include <common.h>
b36df561	24	#include <asm/ppc4xx.h>
c821b5f1 GE	25	#include <ppc_asm.tmpl>
	26	#include <ppc_defs.h>
	27	#include <asm/processor.h>
	28	#include <asm/io.h>
fb95169e SR	29	#include <asm/mmu.h>
fb95169e SR	30	#include <asm/cache.h>
c821b5f1 GE	31
	32	#include "ecc.h"
	33
192f90e2 SR	34	#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) \|\| \
192f90e2 SR	35	defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
c821b5f1	36	#if defined(CONFIG_DDR_ECC) \|\| defined(CONFIG_SDRAM_ECC)
fb95169e SR	37
fb95169e SR	38	#if defined(CONFIG_405EX)
c821b5f1	39	/*
fb95169e SR	40	* Currently only 405EX uses 16bit data bus width as an alternative
fb95169e SR	41	* option to 32bit data width (SDRAM0_MCOPT1_WDTH)
c821b5f1	42	*/
fb95169e SR	43	#define SDRAM_DATA_ALT_WIDTH 2
	44	#else
	45	#define SDRAM_DATA_ALT_WIDTH 8
	46	#endif
	47
	48	static void wait_ddr_idle(void)
c821b5f1	49	{
fb95169e SR	50	u32 val;
	51
	52	do {
	53	mfsdram(SDRAM_MCSTAT, val);
	54	} while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
	55	}
	56
	57	static void program_ecc_addr(unsigned long start_address,
	58	unsigned long num_bytes,
	59	unsigned long tlb_word2_i_value)
	60	{
	61	unsigned long current_address;
	62	unsigned long end_address;
	63	unsigned long address_increment;
c821b5f1	64	unsigned long mcopt1;
fb95169e SR	65	char str[] = "ECC generation -";
	66	char slash[] = "\\\|/-\\\|/-";
	67	int loop = 0;
	68	int loopi = 0;
c821b5f1	69
fb95169e SR	70	current_address = start_address;
	71	mfsdram(SDRAM_MCOPT1, mcopt1);
	72	if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
	73	mtsdram(SDRAM_MCOPT1,
	74	(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) \| SDRAM_MCOPT1_MCHK_GEN);
	75	sync();
	76	eieio();
	77	wait_ddr_idle();
	78
	79	puts(str);
c821b5f1	80
fb95169e SR	81	#ifdef CONFIG_440
	82	if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
	83	#endif
	84	/* ECC bit set method for non-cached memory */
	85	if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
	86	address_increment = 4;
	87	else
	88	address_increment = SDRAM_DATA_ALT_WIDTH;
	89	end_address = current_address + num_bytes;
c821b5f1	90
fb95169e SR	91	while (current_address < end_address) {
	92	((unsigned long )current_address) = 0;
	93	current_address += address_increment;
c821b5f1	94
fb95169e SR	95	if ((loop++ % (2 << 20)) == 0) {
	96	putc('\b');
	97	putc(slash[loopi++ % 8]);
	98	}
	99	}
	100	#ifdef CONFIG_440
	101	} else {
	102	/* ECC bit set method for cached memory */
	103	dcbz_area(start_address, num_bytes);
	104	/* Write modified dcache lines back to memory */
	105	clean_dcache_range(start_address, start_address + num_bytes);
	106	}
	107	#endif /* CONFIG_440 */
c821b5f1	108
fb95169e	109	blank_string(strlen(str));
c821b5f1	110
fb95169e SR	111	sync();
	112	eieio();
	113	wait_ddr_idle();
	114
	115	/* clear ECC error repoting registers */
	116	mtsdram(SDRAM_ECCES, 0xffffffff);
b995d7cb SR	117	#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
	118	/*
	119	* IBM DDR(1) core (440GX):
	120	* Clear Mx bits in SDRAM0_BESR0/1
	121	*/
	122	mtsdram(SDRAM0_BESR0, 0xffffffff);
	123	mtsdram(SDRAM0_BESR1, 0xffffffff);
	124	#elif defined(CONFIG_440)
	125	/*
	126	* 440/460 DDR2 core:
	127	* Clear EMID (Error PLB Master ID) in MQ0_ESL
	128	*/
	129	mtdcr(SDRAM_ERRSTATLL, 0xfff00000);
	130	#else
	131	/*
	132	* 405EX(r) DDR2 core:
	133	* Clear M0ID (Error PLB Master ID) in SDRAM_BESR
	134	*/
	135	mtsdram(SDRAM_BESR, 0xf0000000);
	136	#endif
fb95169e SR	137
	138	mtsdram(SDRAM_MCOPT1,
	139	(mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) \| SDRAM_MCOPT1_MCHK_CHK_REP);
	140	sync();
	141	eieio();
	142	wait_ddr_idle();
	143	}
	144	}
	145
	146	#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
	147	void ecc_init(unsigned long * const start, unsigned long size)
	148	{
c821b5f1	149	/*
fb95169e SR	150	* Init ECC with cache disabled (on PPC's with IBM DDR
fb95169e SR	151	* controller (non DDR2), not tested with cache enabled yet
c821b5f1	152	*/
fb95169e SR	153	program_ecc_addr((u32)start, size, TLB_WORD2_I_ENABLE);
	154	}
	155	#endif
c821b5f1	156
fb95169e SR	157	#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
	158	void do_program_ecc(unsigned long tlb_word2_i_value)
	159	{
	160	unsigned long mcopt1;
	161	unsigned long mcopt2;
	162	unsigned long mcstat;
	163	phys_size_t memsize = sdram_memsize();
c821b5f1	164
fb95169e SR	165	if (memsize > CONFIG_MAX_MEM_MAPPED) {
	166	printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n");
	167	return;
c821b5f1 GE	168	}
c821b5f1 GE	169
fb95169e SR	170	mfsdram(SDRAM_MCOPT1, mcopt1);
fb95169e SR	171	mfsdram(SDRAM_MCOPT2, mcopt2);
c821b5f1	172
fb95169e SR	173	if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
	174	/* DDR controller must be enabled and not in self-refresh. */
	175	mfsdram(SDRAM_MCSTAT, mcstat);
	176	if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
	177	&& ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
	178	&& ((mcstat & (SDRAM_MCSTAT_MIC_MASK \| SDRAM_MCSTAT_SRMS_MASK))
	179	== (SDRAM_MCSTAT_MIC_COMP \| SDRAM_MCSTAT_SRMS_NOT_SF))) {
c821b5f1	180
fb95169e SR	181	program_ecc_addr(0, memsize, tlb_word2_i_value);
	182	}
	183	}
c821b5f1	184	}
fb95169e SR	185	#endif
fb95169e SR	186
c821b5f1	187	#endif /* defined(CONFIG_DDR_ECC) \|\| defined(CONFIG_SDRAM_ECC) */
192f90e2	188	#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */