[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / fdt.c

/*
 * (C) Copyright 2007-2008
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <watchdog.h>
#include <command.h>
#include <asm/cache.h>
#include <asm/ppc4xx.h>

#ifdef CONFIG_OF_BOARD_SETUP
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/4xx_pcie.h>

DECLARE_GLOBAL_DATA_PTR;

int __ft_board_setup(void *blob, bd_t *bd)
{
	int rc;
	int i;
	u32 bxcr;
	u32 ranges[EBC_NUM_BANKS * 4];
	u32 *p = ranges;
	char ebc_path[] = "/plb/opb/ebc";

	ft_cpu_setup(blob, bd);

	/*
	 * Read 4xx EBC bus bridge registers to get mappings of the
	 * peripheral banks into the OPB/PLB address space
	 */
	for (i = 0; i < EBC_NUM_BANKS; i++) {
		mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
		bxcr = mfdcr(EBC0_CFGDATA);

		if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
			*p++ = i;
			*p++ = 0;
			*p++ = bxcr & EBC_BXCR_BAS_MASK;
			*p++ = EBC_BXCR_BANK_SIZE(bxcr);
		}
	}


#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
	/* Update reg property in all nor flash nodes too */
	fdt_fixup_nor_flash_size(blob);
#endif

	/* Some 405 PPC's have EBC as direct PLB child in the dts */
	if (fdt_path_offset(blob, ebc_path) < 0)
		strcpy(ebc_path, "/plb/ebc");
	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
				  (p - ranges) * sizeof(u32), 1);
	if (rc) {
		printf("Unable to update property EBC mappings, err=%s\n",
		       fdt_strerror(rc));
	}

	return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
		__attribute__((weak, alias("__ft_board_setup")));

/*
 * Fixup all PCIe nodes by setting the device_type property
 * to "pci-endpoint" instead is "pci" for endpoint ports.
 * This property will get checked later by the Linux driver
 * to properly configure the PCIe port in Linux (again).
 */
void fdt_pcie_setup(void *blob)
{
	const char *compat = "ibm,plb-pciex";
	const char *prop = "device_type";
	const char *prop_val = "pci-endpoint";
	const u32 *port;
	int no;
	int rc;

	/* Search first PCIe node */
	no = fdt_node_offset_by_compatible(blob, -1, compat);
	while (no != -FDT_ERR_NOTFOUND) {
		port = fdt_getprop(blob, no, "port", NULL);
		if (port == NULL) {
			printf("WARNING: could not find port property\n");
		} else {
			if (is_end_point(*port)) {
				rc = fdt_setprop(blob, no, prop, prop_val,
						 strlen(prop_val) + 1);
				if (rc < 0)
					printf("WARNING: could not set %s for %s: %s.\n",
					       prop, compat, fdt_strerror(rc));
			}
		}

		/* Jump to next PCIe node */
		no = fdt_node_offset_by_compatible(blob, no, compat);
	}
}

void ft_cpu_setup(void *blob, bd_t *bd)
{
	sys_info_t sys_info;
	int off, ndepth = 0;

	get_sys_info(&sys_info);

	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
			     bd->bi_intfreq, 1);
	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
			     bd->bi_intfreq, 1);
	do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
	do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);

	if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
		do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
			sys_info.freqEBC, 1);
	else
		do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
			sys_info.freqEBC, 1);

	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);

	/*
	 * Fixup all UART clocks for CPU internal UARTs
	 * (only these UARTs are definitely clocked by gd->arch.uart_clk)
	 *
	 * These UARTs are direct childs of /plb/opb. This code
	 * does not touch any UARTs that are connected to the ebc.
	 */
	off = fdt_path_offset(blob, "/plb/opb");
	while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
		/*
		 * process all sub nodes and stop when we are back
		 * at the starting depth
		 */
		if (ndepth <= 0)
			break;

		/* only update direct childs */
		if ((ndepth == 1) &&
		    (fdt_node_check_compatible(blob, off, "ns16550") == 0))
			fdt_setprop(blob, off,
				    "clock-frequency",
				    (void *)&gd->arch.uart_clk, 4);
	}

	/*
	 * Fixup all available PCIe nodes by setting the device_type property
	 */
	fdt_pcie_setup(blob);
}
#endif /* CONFIG_OF_BOARD_SETUP */
Commit	Line	Data
4f14ed62	1	/*
cb5d88b9	2	* (C) Copyright 2007-2008
4f14ed62 SR	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
4f14ed62 SR	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
4f14ed62 SR	6	*/
4f14ed62 SR	7
4f14ed62 SR	8	#include <common.h>
	9	#include <watchdog.h>
	10	#include <command.h>
	11	#include <asm/cache.h>
b36df561	12	#include <asm/ppc4xx.h>
4f14ed62	13
7ffe3cd6	14	#ifdef CONFIG_OF_BOARD_SETUP
4f14ed62	15	#include <libfdt.h>
13628884	16	#include <fdt_support.h>
24bfedbd	17	#include <asm/4xx_pcie.h>
4f14ed62	18
f10493c6 SR	19	DECLARE_GLOBAL_DATA_PTR;
f10493c6 SR	20
e895a4b0	21	int __ft_board_setup(void blob, bd_t bd)
cb5d88b9	22	{
cb5d88b9	23	int rc;
43cbce69 SR	24	int i;
	25	u32 bxcr;
	26	u32 ranges[EBC_NUM_BANKS * 4];
	27	u32 *p = ranges;
76706cb8	28	char ebc_path[] = "/plb/opb/ebc";
cb5d88b9 SR	29
	30	ft_cpu_setup(blob, bd);
	31
43cbce69 SR	32	/*
	33	* Read 4xx EBC bus bridge registers to get mappings of the
	34	* peripheral banks into the OPB/PLB address space
	35	*/
	36	for (i = 0; i < EBC_NUM_BANKS; i++) {
d1c3b275 SR	37	mtdcr(EBC0_CFGADDR, EBC_BXCR(i));
d1c3b275 SR	38	bxcr = mfdcr(EBC0_CFGDATA);
43cbce69 SR	39
	40	if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) {
	41	*p++ = i;
	42	*p++ = 0;
	43	*p++ = bxcr & EBC_BXCR_BAS_MASK;
	44	*p++ = EBC_BXCR_BANK_SIZE(bxcr);
8a805df1 SR	45	}
	46	}
	47
92b8964b SR	48
92b8964b SR	49	#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
8a805df1 SR	50	/* Update reg property in all nor flash nodes too */
8a805df1 SR	51	fdt_fixup_nor_flash_size(blob);
92b8964b	52	#endif
43cbce69 SR	53
43cbce69 SR	54	/* Some 405 PPC's have EBC as direct PLB child in the dts */
92b8964b	55	if (fdt_path_offset(blob, ebc_path) < 0)
43cbce69 SR	56	strcpy(ebc_path, "/plb/ebc");
	57	rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
	58	(p - ranges) * sizeof(u32), 1);
	59	if (rc) {
	60	printf("Unable to update property EBC mappings, err=%s\n",
cb5d88b9	61	fdt_strerror(rc));
43cbce69	62	}
e895a4b0 SG	63
e895a4b0 SG	64	return 0;
cb5d88b9	65	}
e895a4b0 SG	66	int ft_board_setup(void blob, bd_t bd)
e895a4b0 SG	67	__attribute__((weak, alias("__ft_board_setup")));
cb5d88b9	68
24bfedbd SR	69	/*
	70	* Fixup all PCIe nodes by setting the device_type property
	71	* to "pci-endpoint" instead is "pci" for endpoint ports.
	72	* This property will get checked later by the Linux driver
	73	* to properly configure the PCIe port in Linux (again).
	74	*/
	75	void fdt_pcie_setup(void *blob)
	76	{
	77	const char *compat = "ibm,plb-pciex";
	78	const char *prop = "device_type";
	79	const char *prop_val = "pci-endpoint";
	80	const u32 *port;
	81	int no;
	82	int rc;
	83
	84	/* Search first PCIe node */
	85	no = fdt_node_offset_by_compatible(blob, -1, compat);
	86	while (no != -FDT_ERR_NOTFOUND) {
	87	port = fdt_getprop(blob, no, "port", NULL);
	88	if (port == NULL) {
	89	printf("WARNING: could not find port property\n");
	90	} else {
	91	if (is_end_point(*port)) {
	92	rc = fdt_setprop(blob, no, prop, prop_val,
	93	strlen(prop_val) + 1);
	94	if (rc < 0)
	95	printf("WARNING: could not set %s for %s: %s.\n",
	96	prop, compat, fdt_strerror(rc));
	97	}
	98	}
	99
	100	/* Jump to next PCIe node */
	101	no = fdt_node_offset_by_compatible(blob, no, compat);
	102	}
	103	}
	104
4f14ed62 SR	105	void ft_cpu_setup(void blob, bd_t bd)
4f14ed62 SR	106	{
4f14ed62	107	sys_info_t sys_info;
b129eff5	108	int off, ndepth = 0;
4f14ed62	109
13628884	110	get_sys_info(&sys_info);
4f14ed62	111
328a3403 SR	112	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency",
	113	bd->bi_intfreq, 1);
	114	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "clock-frequency",
	115	bd->bi_intfreq, 1);
13628884 SR	116	do_fixup_by_path_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1);
13628884 SR	117	do_fixup_by_path_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1);
eea5a743 MB	118
	119	if (fdt_path_offset(blob, "/plb/opb/ebc") >= 0)
	120	do_fixup_by_path_u32(blob, "/plb/opb/ebc", "clock-frequency",
	121	sys_info.freqEBC, 1);
	122	else
	123	do_fixup_by_path_u32(blob, "/plb/ebc", "clock-frequency",
	124	sys_info.freqEBC, 1);
	125
13628884	126	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
4f14ed62 SR	127
4f14ed62 SR	128	/*
b129eff5	129	* Fixup all UART clocks for CPU internal UARTs
3a1dc8f1	130	* (only these UARTs are definitely clocked by gd->arch.uart_clk)
b129eff5 MF	131	*
	132	* These UARTs are direct childs of /plb/opb. This code
	133	* does not touch any UARTs that are connected to the ebc.
4f14ed62	134	*/
b129eff5 MF	135	off = fdt_path_offset(blob, "/plb/opb");
	136	while ((off = fdt_next_node(blob, off, &ndepth)) >= 0) {
	137	/*
	138	* process all sub nodes and stop when we are back
	139	* at the starting depth
	140	*/
	141	if (ndepth <= 0)
	142	break;
	143
	144	/* only update direct childs */
	145	if ((ndepth == 1) &&
	146	(fdt_node_check_compatible(blob, off, "ns16550") == 0))
	147	fdt_setprop(blob, off,
	148	"clock-frequency",
3a1dc8f1	149	(void *)&gd->arch.uart_clk, 4);
b129eff5	150	}
4f14ed62	151
24bfedbd SR	152	/*
	153	* Fixup all available PCIe nodes by setting the device_type property
	154	*/
	155	fdt_pcie_setup(blob);
4f14ed62	156	}
7ffe3cd6	157	#endif /* CONFIG_OF_BOARD_SETUP */