[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / traps.c

/*
 * linux/arch/powerpc/kernel/traps.c
 *
 * Copyright (C) 1995-1996  Gary Thomas (gdt@linuxppc.org)
 *
 * Modified by Cort Dougan (cort@cs.nmt.edu)
 * and Paul Mackerras (paulus@cs.anu.edu.au)
 *
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * This file handles the architecture-dependent parts of hardware exceptions
 */

#include <common.h>
#include <command.h>
#include <kgdb.h>
#include <asm/processor.h>

DECLARE_GLOBAL_DATA_PTR;

/* Returns 0 if exception not found and fixup otherwise.  */
extern unsigned long search_exception_table(unsigned long);

/* THIS NEEDS CHANGING to use the board info structure.
 */
#define END_OF_MEM	(gd->bd->bi_memstart + gd->bd->bi_memsize)

static __inline__ void set_tsr(unsigned long val)
{
#if defined(CONFIG_440)
	asm volatile("mtspr 0x150, %0" : : "r" (val));
#else
	asm volatile("mttsr %0" : : "r" (val));
#endif
}

static __inline__ unsigned long get_esr(void)
{
	unsigned long val;

#if defined(CONFIG_440)
	asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
#else
	asm volatile("mfesr %0" : "=r" (val) :);
#endif
	return val;
}

#define ESR_MCI 0x80000000
#define ESR_PIL 0x08000000
#define ESR_PPR 0x04000000
#define ESR_PTR 0x02000000
#define ESR_DST 0x00800000
#define ESR_DIZ 0x00400000
#define ESR_U0F 0x00008000

#if defined(CONFIG_CMD_BEDBUG)
extern void do_bedbug_breakpoint(struct pt_regs *);
#endif

/*
 * Trap & Exception support
 */

void
print_backtrace(unsigned long *sp)
{
	int cnt = 0;
	unsigned long i;

	printf("Call backtrace: ");
	while (sp) {
		if ((uint)sp > END_OF_MEM)
			break;

		i = sp[1];
		if (cnt++ % 7 == 0)
			printf("\n");
		printf("%08lX ", i);
		if (cnt > 32) break;
		sp = (unsigned long *)*sp;
	}
	printf("\n");
}

void show_regs(struct pt_regs * regs)
{
	int i;

	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
	       regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
	       regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
	       regs->msr&MSR_IR ? 1 : 0,
	       regs->msr&MSR_DR ? 1 : 0);

	printf("\n");
	for (i = 0;  i < 32;  i++) {
		if ((i % 8) == 0) {
			printf("GPR%02d: ", i);
		}

		printf("%08lX ", regs->gpr[i]);
		if ((i % 8) == 7) {
			printf("\n");
		}
	}
}


void
_exception(int signr, struct pt_regs *regs)
{
	show_regs(regs);
	print_backtrace((unsigned long *)regs->gpr[1]);
	panic("Exception");
}

void
MachineCheckException(struct pt_regs *regs)
{
	unsigned long fixup, val;
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
	u32 value2;
	int corr_ecc = 0;
	int uncorr_ecc = 0;
#endif

	if ((fixup = search_exception_table(regs->nip)) != 0) {
		regs->nip = fixup;
		val = mfspr(MCSR);
		/* Clear MCSR */
		mtspr(SPRN_MCSR, val);
		return;
	}

#if defined(CONFIG_CMD_KGDB)
	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
		return;
#endif

	printf("Machine Check Exception.\n");
	printf("Caused by (from msr): ");
	printf("regs %p ", regs);

	val = get_esr();

#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
	if (val& ESR_IMCP) {
		printf("Instruction");
		mtspr(ESR, val & ~ESR_IMCP);
	} else {
		printf("Data");
	}
	printf(" machine check.\n");

#elif defined(CONFIG_440) || defined(CONFIG_405EX)
	if (val& ESR_IMCP){
		printf("Instruction Synchronous Machine Check exception\n");
		mtspr(SPRN_ESR, val & ~ESR_IMCP);
	} else {
		val = mfspr(MCSR);
		if (val & MCSR_IB)
			printf("Instruction Read PLB Error\n");
#if defined(CONFIG_440)
		if (val & MCSR_DRB)
			printf("Data Read PLB Error\n");
		if (val & MCSR_DWB)
			printf("Data Write PLB Error\n");
#else
		if (val & MCSR_DB)
			printf("Data PLB Error\n");
#endif
		if (val & MCSR_TLBP)
			printf("TLB Parity Error\n");
		if (val & MCSR_ICP){
			/*flush_instruction_cache(); */
			printf("I-Cache Parity Error\n");
		}
		if (val & MCSR_DCSP)
			printf("D-Cache Search Parity Error\n");
		if (val & MCSR_DCFP)
			printf("D-Cache Flush Parity Error\n");
		if (val & MCSR_IMPE)
			printf("Machine Check exception is imprecise\n");

		/* Clear MCSR */
		mtspr(SPRN_MCSR, val);
	}
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
	mfsdram(DDR0_00, val) ;
	printf("DDR0: DDR0_00 %lx\n", val);
	val = (val >> 16) & 0xff;
	if (val & 0x80)
		printf("DDR0: At least one interrupt active\n");
	if (val & 0x40)
		printf("DDR0: DRAM initialization complete.\n");
	if (val & 0x20) {
		printf("DDR0: Multiple uncorrectable ECC events.\n");
		uncorr_ecc = 1;
	}
	if (val & 0x10) {
		printf("DDR0: Single uncorrectable ECC event.\n");
		uncorr_ecc = 1;
	}
	if (val & 0x08) {
		printf("DDR0: Multiple correctable ECC events.\n");
		corr_ecc = 1;
	}
	if (val & 0x04) {
		printf("DDR0: Single correctable ECC event.\n");
		corr_ecc = 1;
	}
	if (val & 0x02)
		printf("Multiple accesses outside the defined"
		       " physical memory space detected\n");
	if (val & 0x01)
		printf("DDR0: Single access outside the defined"
		       " physical memory space detected.\n");

	mfsdram(DDR0_01, val);
	val = (val >> 8) & 0x7;
	switch (val ) {
	case 0:
		printf("DDR0: Write Out-of-Range command\n");
		break;
	case 1:
		printf("DDR0: Read Out-of-Range command\n");
		break;
	case 2:
		printf("DDR0: Masked write Out-of-Range command\n");
		break;
	case 4:
		printf("DDR0: Wrap write Out-of-Range command\n");
		break;
	case 5:
		printf("DDR0: Wrap read Out-of-Range command\n");
		break;
	default:
		mfsdram(DDR0_01, value2);
		printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
	}
	mfsdram(DDR0_23, val);
	if (((val >> 16) & 0xff) && corr_ecc)
		printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
		       (val >> 16) & 0xff);
	mfsdram(DDR0_23, val);
	if (((val >> 8) & 0xff) && uncorr_ecc)
		printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
		       (val >> 8) & 0xff);
	mfsdram(DDR0_33, val);
	if (val)
		printf("DDR0: Address of command that caused an "
		       "Out-of-Range interrupt %lx\n", val);
	mfsdram(DDR0_34, val);
	if (val && uncorr_ecc)
		printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
	mfsdram(DDR0_35, val);
	if (val && uncorr_ecc)
		printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
	mfsdram(DDR0_36, val);
	if (val && uncorr_ecc)
		printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
	mfsdram(DDR0_37, val);
	if (val && uncorr_ecc)
		printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
	mfsdram(DDR0_38, val);
	if (val && corr_ecc)
		printf("DDR0: Address of correctable ECC event %lx\n", val);
	mfsdram(DDR0_39, val);
	if (val && corr_ecc)
		printf("DDR0: Address of correctable ECC event %lx\n", val);
	mfsdram(DDR0_40, val);
	if (val && corr_ecc)
		printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
	mfsdram(DDR0_41, val);
	if (val && corr_ecc)
		printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
#endif /* CONFIG_440EPX */
#endif /* CONFIG_440 */
	show_regs(regs);
	print_backtrace((unsigned long *)regs->gpr[1]);
	panic("machine check");
}

void
AlignmentException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
		return;
#endif

	show_regs(regs);
	print_backtrace((unsigned long *)regs->gpr[1]);
	panic("Alignment Exception");
}

void
ProgramCheckException(struct pt_regs *regs)
{
	long esr_val;

#if defined(CONFIG_CMD_KGDB)
	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
		return;
#endif

	show_regs(regs);

	esr_val = get_esr();
	if( esr_val & ESR_PIL )
		printf( "** Illegal Instruction **\n" );
	else if( esr_val & ESR_PPR )
		printf( "** Privileged Instruction **\n" );
	else if( esr_val & ESR_PTR )
		printf( "** Trap Instruction **\n" );

	print_backtrace((unsigned long *)regs->gpr[1]);
	panic("Program Check Exception");
}

void
DecrementerPITException(struct pt_regs *regs)
{
	/*
	 * Reset PIT interrupt
	 */
	set_tsr(0x08000000);

	/*
	 * Call timer_interrupt routine in interrupts.c
	 */
	timer_interrupt(NULL);
}


void
UnknownException(struct pt_regs *regs)
{
#if defined(CONFIG_CMD_KGDB)
	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
		return;
#endif

	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
	       regs->nip, regs->msr, regs->trap);
	_exception(0, regs);
}

void
DebugException(struct pt_regs *regs)
{
	printf("Debugger trap at @ %lx\n", regs->nip );
	show_regs(regs);
#if defined(CONFIG_CMD_BEDBUG)
	do_bedbug_breakpoint( regs );
#endif
}

/* Probe an address by reading.  If not present, return -1, otherwise
 * return 0.
 */
int
addr_probe(uint *addr)
{
#if 0
	int	retval;

	__asm__ __volatile__(			\
		"1:	lwz %0,0(%1)\n"		\
		"	eieio\n"		\
		"	li %0,0\n"		\
		"2:\n"				\
		".section .fixup,\"ax\"\n"	\
		"3:	li %0,-1\n"		\
		"	b 2b\n"			\
		".section __ex_table,\"a\"\n"	\
		"	.align 2\n"		\
		"	.long 1b,3b\n"		\
		".text"				\
		: "=r" (retval) : "r"(addr));

	return (retval);
#endif
	return 0;
}
Commit	Line	Data
affae2bf	1	/*
a47a12be	2	* linux/arch/powerpc/kernel/traps.c
affae2bf WD	3	*
	4	* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
	5	*
	6	* Modified by Cort Dougan (cort@cs.nmt.edu)
	7	* and Paul Mackerras (paulus@cs.anu.edu.au)
	8	*
	9	* (C) Copyright 2000
	10	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	11	*
	12	* See file CREDITS for list of people who contributed to this
	13	* project.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of
	18	* the License, or (at your option) any later version.
	19	*
	20	* This program is distributed in the hope that it will be useful,
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* You should have received a copy of the GNU General Public License
	26	* along with this program; if not, write to the Free Software
	27	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	28	* MA 02111-1307 USA
	29	*/
	30
	31	/*
	32	* This file handles the architecture-dependent parts of hardware exceptions
	33	*/
	34
	35	#include <common.h>
	36	#include <command.h>
6f6c26e4	37	#include <kgdb.h>
affae2bf WD	38	#include <asm/processor.h>
affae2bf WD	39
efa35cf1 GB	40	DECLARE_GLOBAL_DATA_PTR;
efa35cf1 GB	41
affae2bf WD	42	/* Returns 0 if exception not found and fixup otherwise. */
	43	extern unsigned long search_exception_table(unsigned long);
	44
	45	/* THIS NEEDS CHANGING to use the board info structure.
	46	*/
efa35cf1	47	#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
affae2bf WD	48
	49	static __inline__ void set_tsr(unsigned long val)
	50	{
	51	#if defined(CONFIG_440)
	52	asm volatile("mtspr 0x150, %0" : : "r" (val));
	53	#else
	54	asm volatile("mttsr %0" : : "r" (val));
	55	#endif
	56	}
	57
	58	static __inline__ unsigned long get_esr(void)
	59	{
	60	unsigned long val;
	61
	62	#if defined(CONFIG_440)
	63	asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
	64	#else
	65	asm volatile("mfesr %0" : "=r" (val) :);
	66	#endif
	67	return val;
	68	}
	69
	70	#define ESR_MCI 0x80000000
	71	#define ESR_PIL 0x08000000
	72	#define ESR_PPR 0x04000000
	73	#define ESR_PTR 0x02000000
	74	#define ESR_DST 0x00800000
	75	#define ESR_DIZ 0x00400000
	76	#define ESR_U0F 0x00008000
	77
3a1ed1e1	78	#if defined(CONFIG_CMD_BEDBUG)
affae2bf WD	79	extern void do_bedbug_breakpoint(struct pt_regs *);
	80	#endif
	81
	82	/*
	83	* Trap & Exception support
	84	*/
	85
	86	void
	87	print_backtrace(unsigned long *sp)
	88	{
83b4cfa3 WD	89	int cnt = 0;
	90	unsigned long i;
	91
	92	printf("Call backtrace: ");
	93	while (sp) {
	94	if ((uint)sp > END_OF_MEM)
	95	break;
	96
	97	i = sp[1];
	98	if (cnt++ % 7 == 0)
	99	printf("\n");
	100	printf("%08lX ", i);
	101	if (cnt > 32) break;
	102	sp = (unsigned long )sp;
	103	}
	104	printf("\n");
affae2bf WD	105	}
	106
	107	void show_regs(struct pt_regs * regs)
	108	{
	109	int i;
	110
efa35cf1	111	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
affae2bf WD	112	regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
	113	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
	114	regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
	115	regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
	116	regs->msr&MSR_IR ? 1 : 0,
	117	regs->msr&MSR_DR ? 1 : 0);
	118
	119	printf("\n");
	120	for (i = 0; i < 32; i++) {
83b4cfa3	121	if ((i % 8) == 0) {
affae2bf WD	122	printf("GPR%02d: ", i);
	123	}
	124
	125	printf("%08lX ", regs->gpr[i]);
83b4cfa3	126	if ((i % 8) == 7) {
affae2bf WD	127	printf("\n");
	128	}
	129	}
	130	}
	131
	132
	133	void
	134	_exception(int signr, struct pt_regs *regs)
	135	{
	136	show_regs(regs);
	137	print_backtrace((unsigned long *)regs->gpr[1]);
efa35cf1	138	panic("Exception");
affae2bf WD	139	}
	140
	141	void
	142	MachineCheckException(struct pt_regs *regs)
	143	{
efa35cf1	144	unsigned long fixup, val;
a1bd6200 NG	145	#if defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
a1bd6200 NG	146	u32 value2;
27a528fb SR	147	int corr_ecc = 0;
27a528fb SR	148	int uncorr_ecc = 0;
a1bd6200	149	#endif
83b4cfa3	150
affae2bf WD	151	if ((fixup = search_exception_table(regs->nip)) != 0) {
affae2bf WD	152	regs->nip = fixup;
c9240981 GB	153	val = mfspr(MCSR);
c9240981 GB	154	/* Clear MCSR */
9ca8d79d	155	mtspr(SPRN_MCSR, val);
affae2bf WD	156	return;
	157	}
	158
3a1ed1e1	159	#if defined(CONFIG_CMD_KGDB)
affae2bf WD	160	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
	161	return;
	162	#endif
	163
efa35cf1	164	printf("Machine Check Exception.\n");
affae2bf	165	printf("Caused by (from msr): ");
efa35cf1 GB	166	printf("regs %p ", regs);
	167
	168	val = get_esr();
	169
c821b5f1	170	#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
efa35cf1 GB	171	if (val& ESR_IMCP) {
	172	printf("Instruction");
	173	mtspr(ESR, val & ~ESR_IMCP);
83b4cfa3	174	} else {
efa35cf1	175	printf("Data");
83b4cfa3	176	}
efa35cf1 GB	177	printf(" machine check.\n");
efa35cf1 GB	178
c821b5f1	179	#elif defined(CONFIG_440) \|\| defined(CONFIG_405EX)
efa35cf1 GB	180	if (val& ESR_IMCP){
	181	printf("Instruction Synchronous Machine Check exception\n");
	182	mtspr(SPRN_ESR, val & ~ESR_IMCP);
83b4cfa3	183	} else {
efa35cf1 GB	184	val = mfspr(MCSR);
	185	if (val & MCSR_IB)
	186	printf("Instruction Read PLB Error\n");
c821b5f1	187	#if defined(CONFIG_440)
efa35cf1 GB	188	if (val & MCSR_DRB)
	189	printf("Data Read PLB Error\n");
	190	if (val & MCSR_DWB)
	191	printf("Data Write PLB Error\n");
c821b5f1 GE	192	#else
	193	if (val & MCSR_DB)
	194	printf("Data PLB Error\n");
	195	#endif
efa35cf1 GB	196	if (val & MCSR_TLBP)
	197	printf("TLB Parity Error\n");
	198	if (val & MCSR_ICP){
	199	/flush_instruction_cache(); /
	200	printf("I-Cache Parity Error\n");
	201	}
	202	if (val & MCSR_DCSP)
	203	printf("D-Cache Search Parity Error\n");
	204	if (val & MCSR_DCFP)
	205	printf("D-Cache Flush Parity Error\n");
	206	if (val & MCSR_IMPE)
	207	printf("Machine Check exception is imprecise\n");
	208
	209	/* Clear MCSR */
	210	mtspr(SPRN_MCSR, val);
	211	}
a1bd6200 NG	212	#if defined(CONFIG_440EPX) \|\| defined(CONFIG_440GRX)
a1bd6200 NG	213	mfsdram(DDR0_00, val) ;
b002144e	214	printf("DDR0: DDR0_00 %lx\n", val);
a1bd6200 NG	215	val = (val >> 16) & 0xff;
	216	if (val & 0x80)
	217	printf("DDR0: At least one interrupt active\n");
	218	if (val & 0x40)
	219	printf("DDR0: DRAM initialization complete.\n");
27a528fb	220	if (val & 0x20) {
a1bd6200	221	printf("DDR0: Multiple uncorrectable ECC events.\n");
27a528fb SR	222	uncorr_ecc = 1;
	223	}
	224	if (val & 0x10) {
a1bd6200	225	printf("DDR0: Single uncorrectable ECC event.\n");
27a528fb SR	226	uncorr_ecc = 1;
	227	}
	228	if (val & 0x08) {
a1bd6200	229	printf("DDR0: Multiple correctable ECC events.\n");
27a528fb SR	230	corr_ecc = 1;
	231	}
	232	if (val & 0x04) {
a1bd6200	233	printf("DDR0: Single correctable ECC event.\n");
27a528fb SR	234	corr_ecc = 1;
27a528fb SR	235	}
a1bd6200 NG	236	if (val & 0x02)
	237	printf("Multiple accesses outside the defined"
	238	" physical memory space detected\n");
	239	if (val & 0x01)
	240	printf("DDR0: Single access outside the defined"
	241	" physical memory space detected.\n");
	242
	243	mfsdram(DDR0_01, val);
	244	val = (val >> 8) & 0x7;
	245	switch (val ) {
	246	case 0:
	247	printf("DDR0: Write Out-of-Range command\n");
	248	break;
	249	case 1:
	250	printf("DDR0: Read Out-of-Range command\n");
	251	break;
	252	case 2:
	253	printf("DDR0: Masked write Out-of-Range command\n");
	254	break;
	255	case 4:
	256	printf("DDR0: Wrap write Out-of-Range command\n");
	257	break;
	258	case 5:
	259	printf("DDR0: Wrap read Out-of-Range command\n");
	260	break;
	261	default:
	262	mfsdram(DDR0_01, value2);
b002144e	263	printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
a1bd6200 NG	264	}
a1bd6200 NG	265	mfsdram(DDR0_23, val);
27a528fb	266	if (((val >> 16) & 0xff) && corr_ecc)
b002144e	267	printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
a1bd6200 NG	268	(val >> 16) & 0xff);
a1bd6200 NG	269	mfsdram(DDR0_23, val);
27a528fb	270	if (((val >> 8) & 0xff) && uncorr_ecc)
b002144e	271	printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
a1bd6200 NG	272	(val >> 8) & 0xff);
	273	mfsdram(DDR0_33, val);
	274	if (val)
	275	printf("DDR0: Address of command that caused an "
b002144e	276	"Out-of-Range interrupt %lx\n", val);
a1bd6200	277	mfsdram(DDR0_34, val);
27a528fb	278	if (val && uncorr_ecc)
b002144e	279	printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
a1bd6200	280	mfsdram(DDR0_35, val);
27a528fb	281	if (val && uncorr_ecc)
b002144e	282	printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
a1bd6200	283	mfsdram(DDR0_36, val);
27a528fb	284	if (val && uncorr_ecc)
b002144e	285	printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
a1bd6200	286	mfsdram(DDR0_37, val);
27a528fb	287	if (val && uncorr_ecc)
b002144e	288	printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
a1bd6200	289	mfsdram(DDR0_38, val);
27a528fb	290	if (val && corr_ecc)
b002144e	291	printf("DDR0: Address of correctable ECC event %lx\n", val);
a1bd6200	292	mfsdram(DDR0_39, val);
27a528fb	293	if (val && corr_ecc)
b002144e	294	printf("DDR0: Address of correctable ECC event %lx\n", val);
a1bd6200	295	mfsdram(DDR0_40, val);
27a528fb	296	if (val && corr_ecc)
b002144e	297	printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
a1bd6200	298	mfsdram(DDR0_41, val);
27a528fb	299	if (val && corr_ecc)
b002144e	300	printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
a1bd6200 NG	301	#endif /* CONFIG_440EPX */
a1bd6200 NG	302	#endif /* CONFIG_440 */
affae2bf WD	303	show_regs(regs);
	304	print_backtrace((unsigned long *)regs->gpr[1]);
	305	panic("machine check");
	306	}
	307
	308	void
	309	AlignmentException(struct pt_regs *regs)
	310	{
3a1ed1e1	311	#if defined(CONFIG_CMD_KGDB)
affae2bf WD	312	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
	313	return;
	314	#endif
	315
	316	show_regs(regs);
	317	print_backtrace((unsigned long *)regs->gpr[1]);
	318	panic("Alignment Exception");
	319	}
	320
	321	void
	322	ProgramCheckException(struct pt_regs *regs)
	323	{
8bde7f77	324	long esr_val;
affae2bf	325
3a1ed1e1	326	#if defined(CONFIG_CMD_KGDB)
affae2bf WD	327	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
	328	return;
	329	#endif
	330
	331	show_regs(regs);
	332
8bde7f77 WD	333	esr_val = get_esr();
8bde7f77 WD	334	if( esr_val & ESR_PIL )
affae2bf	335	printf( " Illegal Instruction \n" );
8bde7f77	336	else if( esr_val & ESR_PPR )
affae2bf	337	printf( " Privileged Instruction \n" );
8bde7f77	338	else if( esr_val & ESR_PTR )
affae2bf WD	339	printf( " Trap Instruction \n" );
	340
	341	print_backtrace((unsigned long *)regs->gpr[1]);
	342	panic("Program Check Exception");
	343	}
	344
	345	void
efa35cf1	346	DecrementerPITException(struct pt_regs *regs)
affae2bf	347	{
8bde7f77 WD	348	/*
	349	* Reset PIT interrupt
	350	*/
	351	set_tsr(0x08000000);
	352
	353	/*
	354	* Call timer_interrupt routine in interrupts.c
	355	*/
	356	timer_interrupt(NULL);
affae2bf WD	357	}
	358
	359
	360	void
	361	UnknownException(struct pt_regs *regs)
	362	{
3a1ed1e1	363	#if defined(CONFIG_CMD_KGDB)
affae2bf WD	364	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
	365	return;
	366	#endif
	367
	368	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
	369	regs->nip, regs->msr, regs->trap);
	370	_exception(0, regs);
	371	}
	372
	373	void
	374	DebugException(struct pt_regs *regs)
	375	{
	376	printf("Debugger trap at @ %lx\n", regs->nip );
	377	show_regs(regs);
3a1ed1e1	378	#if defined(CONFIG_CMD_BEDBUG)
affae2bf WD	379	do_bedbug_breakpoint( regs );
	380	#endif
	381	}
	382
	383	/* Probe an address by reading. If not present, return -1, otherwise
	384	* return 0.
	385	*/
	386	int
	387	addr_probe(uint *addr)
	388	{
	389	#if 0
	390	int retval;
	391
	392	__asm__ __volatile__( \
	393	"1: lwz %0,0(%1)\n" \
83b4cfa3 WD	394	" eieio\n" \
	395	" li %0,0\n" \
	396	"2:\n" \
	397	".section .fixup,\"ax\"\n" \
	398	"3: li %0,-1\n" \
	399	" b 2b\n" \
	400	".section __ex_table,\"a\"\n" \
	401	" .align 2\n" \
	402	" .long 1b,3b\n" \
	403	".text" \
	404	: "=r" (retval) : "r"(addr));
affae2bf WD	405
	406	return (retval);
	407	#endif
	408	return 0;
	409	}