[people/ms/u-boot.git] / arch / powerpc / dts / canyonlands.dts

/*
 * Device Tree Source for AMCC Canyonlands (460EX)
 *
 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

/dts-v1/;

/ {
	#address-cells = <2>;
	#size-cells = <1>;
	model = "amcc,canyonlands";
	compatible = "amcc,canyonlands";
	dcr-parent = <&{/cpus/cpu@0}>;

	aliases {
		ethernet0 = &EMAC0;
		ethernet1 = &EMAC1;
		serial0 = &UART0;
		serial1 = &UART1;
	};

	chosen {
		stdout-path = &UART0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			model = "PowerPC,460EX";
			reg = <0x00000000>;
			clock-frequency = <0>; /* Filled in by U-Boot */
			timebase-frequency = <0>; /* Filled in by U-Boot */
			i-cache-line-size = <32>;
			d-cache-line-size = <32>;
			i-cache-size = <32768>;
			d-cache-size = <32768>;
			dcr-controller;
			dcr-access-method = "native";
			next-level-cache = <&L2C0>;
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
	};

	UIC0: interrupt-controller0 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <0>;
		dcr-reg = <0x0c0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
	};

	UIC1: interrupt-controller1 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <1>;
		dcr-reg = <0x0d0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC2: interrupt-controller2 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <2>;
		dcr-reg = <0x0e0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	UIC3: interrupt-controller3 {
		compatible = "ibm,uic-460ex","ibm,uic";
		interrupt-controller;
		cell-index = <3>;
		dcr-reg = <0x0f0 0x009>;
		#address-cells = <0>;
		#size-cells = <0>;
		#interrupt-cells = <2>;
		interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
		interrupt-parent = <&UIC0>;
	};

	SDR0: sdr {
		compatible = "ibm,sdr-460ex";
		dcr-reg = <0x00e 0x002>;
	};

	CPR0: cpr {
		compatible = "ibm,cpr-460ex";
		dcr-reg = <0x00c 0x002>;
	};

	CPM0: cpm {
		compatible = "ibm,cpm";
		dcr-access-method = "native";
		dcr-reg = <0x160 0x003>;
		unused-units = <0x00000100>;
		idle-doze = <0x02000000>;
		standby = <0xfeff791d>;
	};

	L2C0: l2c {
		compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
		dcr-reg = <0x020 0x008		/* Internal SRAM DCR's */
			   0x030 0x008>;	/* L2 cache DCR's */
		cache-line-size = <32>;		/* 32 bytes */
		cache-size = <262144>;		/* L2, 256K */
		interrupt-parent = <&UIC1>;
		interrupts = <11 1>;
	};

	plb {
		compatible = "ibm,plb-460ex", "ibm,plb4";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;
		clock-frequency = <0>; /* Filled in by U-Boot */

		SDRAM0: sdram {
			compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
			dcr-reg = <0x010 0x002>;
		};

		CRYPTO: crypto@180000 {
			compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
			reg = <4 0x00180000 0x80400>;
			interrupt-parent = <&UIC0>;
			interrupts = <0x1d 0x4>;
		};

		HWRNG: hwrng@110000 {
			compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
			reg = <4 0x00110000 0x50>;
		};

		MAL0: mcmal {
			compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
			dcr-reg = <0x180 0x062>;
			num-tx-chans = <2>;
			num-rx-chans = <16>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-parent = <&UIC2>;
			interrupts = <	/*TXEOB*/ 0x6 0x4
					/*RXEOB*/ 0x7 0x4
					/*SERR*/  0x3 0x4
					/*TXDE*/  0x4 0x4
					/*RXDE*/  0x5 0x4>;
		};

		USB0: ehci@bffd0400 {
			compatible = "ibm,usb-ehci-460ex", "usb-ehci";
			interrupt-parent = <&UIC2>;
			interrupts = <0x1d 4>;
			reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
		};

		USB1: usb@bffd0000 {
			compatible = "ohci-le";
			reg = <4 0xbffd0000 0x60>;
			interrupt-parent = <&UIC2>;
			interrupts = <0x1e 4>;
		};

		USBOTG0: usbotg@bff80000 {
			compatible = "amcc,dwc-otg";
			reg = <0x4 0xbff80000 0x10000>;
			interrupt-parent = <&USBOTG0>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupts = <0x0 0x1 0x2>;
			interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
					 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
					 /* DMA */ 0x2 &UIC0 0xc 0x4>;
		};

		SATA0: sata@bffd1000 {
			compatible = "amcc,sata-460ex";
			reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
			interrupt-parent = <&UIC3>;
			interrupts = <0x0 0x4       /* SATA */
				      0x5 0x4>;     /* AHBDMA */
		};

		POB0: opb {
			compatible = "ibm,opb-460ex", "ibm,opb";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
			clock-frequency = <0>; /* Filled in by U-Boot */

			EBC0: ebc {
				compatible = "ibm,ebc-460ex", "ibm,ebc";
				dcr-reg = <0x012 0x002>;
				#address-cells = <2>;
				#size-cells = <1>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				/* ranges property is supplied by U-Boot */
				interrupts = <0x6 0x4>;
				interrupt-parent = <&UIC1>;

				nor_flash@0,0 {
					compatible = "amd,s29gl512n", "cfi-flash";
					bank-width = <2>;
					reg = <0x00000000 0x00000000 0x04000000>;
					#address-cells = <1>;
					#size-cells = <1>;
					partition@0 {
						label = "kernel";
						reg = <0x00000000 0x001e0000>;
					};
					partition@1e0000 {
						label = "dtb";
						reg = <0x001e0000 0x00020000>;
					};
					partition@200000 {
						label = "ramdisk";
						reg = <0x00200000 0x01400000>;
					};
					partition@1600000 {
						label = "jffs2";
						reg = <0x01600000 0x00400000>;
					};
					partition@1a00000 {
						label = "user";
						reg = <0x01a00000 0x02560000>;
					};
					partition@3f60000 {
						label = "env";
						reg = <0x03f60000 0x00040000>;
					};
					partition@3fa0000 {
						label = "u-boot";
						reg = <0x03fa0000 0x00060000>;
					};
				};

				cpld@2,0 {
					compatible = "amcc,ppc460ex-bcsr";
					reg = <2 0x0 0x9>;
				};

				ndfc@3,0 {
					compatible = "ibm,ndfc";
					reg = <0x00000003 0x00000000 0x00002000>;
					ccr = <0x00001000>;
					bank-settings = <0x80002222>;
					#address-cells = <1>;
					#size-cells = <1>;

					nand {
						#address-cells = <1>;
						#size-cells = <1>;

						partition@0 {
							label = "u-boot";
							reg = <0x00000000 0x00100000>;
						};
						partition@100000 {
							label = "user";
							reg = <0x00000000 0x03f00000>;
						};
					};
				};
			};

			UART0: serial@ef600300 {
				device_type = "serial";
				reg-shift = <0>;
				compatible = "ns16550";
				reg = <0xef600300 0x00000008>;
				virtual-reg = <0xef600300>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC1>;
				interrupts = <0x1 0x4>;
			};

			UART1: serial@ef600400 {
				device_type = "serial";
				reg-shift = <0>;
				compatible = "ns16550";
				reg = <0xef600400 0x00000008>;
				virtual-reg = <0xef600400>;
				clock-frequency = <0>; /* Filled in by U-Boot */
				current-speed = <0>; /* Filled in by U-Boot */
				interrupt-parent = <&UIC0>;
				interrupts = <0x1 0x4>;
			};

			IIC0: i2c@ef600700 {
				compatible = "ibm,iic-460ex", "ibm,iic";
				reg = <0xef600700 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x2 0x4>;
				#address-cells = <1>;
				#size-cells = <0>;
                                rtc@68 {
                                        compatible = "stm,m41t80";
                                        reg = <0x68>;
					interrupt-parent = <&UIC2>;
					interrupts = <0x19 0x8>;
                                };
                                sttm@48 {
                                        compatible = "ad,ad7414";
                                        reg = <0x48>;
					interrupt-parent = <&UIC1>;
					interrupts = <0x14 0x8>;
                                };
			};

			IIC1: i2c@ef600800 {
				compatible = "ibm,iic-460ex", "ibm,iic";
				reg = <0xef600800 0x00000014>;
				interrupt-parent = <&UIC0>;
				interrupts = <0x3 0x4>;
			};

			GPIO0: gpio@ef600b00 {
				compatible = "ibm,ppc4xx-gpio";
				reg = <0xef600b00 0x00000048>;
				gpio-controller;
			};

			ZMII0: emac-zmii@ef600d00 {
				compatible = "ibm,zmii-460ex", "ibm,zmii";
				reg = <0xef600d00 0x0000000c>;
			};

			RGMII0: emac-rgmii@ef601500 {
				compatible = "ibm,rgmii-460ex", "ibm,rgmii";
				reg = <0xef601500 0x00000008>;
				has-mdio;
			};

			TAH0: emac-tah@ef601350 {
				compatible = "ibm,tah-460ex", "ibm,tah";
				reg = <0xef601350 0x00000030>;
			};

			TAH1: emac-tah@ef601450 {
				compatible = "ibm,tah-460ex", "ibm,tah";
				reg = <0xef601450 0x00000030>;
			};

			EMAC0: ethernet@ef600e00 {
				device_type = "network";
				compatible = "ibm,emac-460ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC0>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
						 /*Wake*/   0x1 &UIC2 0x14 0x4>;
				reg = <0xef600e00 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <0>;
				mal-rx-channel = <0>;
				cell-index = <0>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				rx-fifo-size-gige = <16384>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <0>;
				tah-device = <&TAH0>;
				tah-channel = <0>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
			};

			EMAC1: ethernet@ef600f00 {
				device_type = "network";
				compatible = "ibm,emac-460ex", "ibm,emac4sync";
				interrupt-parent = <&EMAC1>;
				interrupts = <0x0 0x1>;
				#interrupt-cells = <1>;
				#address-cells = <0>;
				#size-cells = <0>;
				interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
						 /*Wake*/   0x1 &UIC2 0x15 0x4>;
				reg = <0xef600f00 0x000000c4>;
				local-mac-address = [000000000000]; /* Filled in by U-Boot */
				mal-device = <&MAL0>;
				mal-tx-channel = <1>;
				mal-rx-channel = <8>;
				cell-index = <1>;
				max-frame-size = <9000>;
				rx-fifo-size = <4096>;
				tx-fifo-size = <2048>;
				rx-fifo-size-gige = <16384>;
				phy-mode = "rgmii";
				phy-map = <0x00000000>;
				rgmii-device = <&RGMII0>;
				rgmii-channel = <1>;
				tah-device = <&TAH1>;
				tah-channel = <1>;
				has-inverted-stacr-oc;
				has-new-stacr-staopc;
				mdio-device = <&EMAC0>;
			};
		};

		PCIX0: pci@c0ec00000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
			primary;
			large-inbound-windows;
			enable-msi-hole;
			reg = <0x0000000c 0x0ec00000   0x00000008	/* Config space access */
			       0x00000000 0x00000000 0x00000000		/* no IACK cycles */
			       0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
			       0x0000000c 0x0ec80000 0x00000100	/* Internal registers */
			       0x0000000c 0x0ec80100  0x000000fc>;	/* Internal messaging registers */

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
				  0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
				  0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 0 to 0x3f */
			bus-range = <0x0 0x3f>;

			/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
			interrupt-map-mask = <0x0 0x0 0x0 0x0>;
			interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
		};

		PCIE0: pciex@d00000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
			primary;
			port = <0x0>; /* port number */
			reg = <0x0000000d 0x00000000 0x20000000	/* Config space access */
			       0x0000000c 0x08010000 0x00001000>;	/* Registers */
			dcr-reg = <0x100 0x020>;
			sdr-base = <0x300>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 40 to 0x7f */
			bus-range = <0x40 0x7f>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
		};

		PCIE1: pciex@d20000000 {
			device_type = "pci";
			#interrupt-cells = <1>;
			#size-cells = <2>;
			#address-cells = <3>;
			compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
			primary;
			port = <0x1>; /* port number */
			reg = <0x0000000d 0x20000000 0x20000000	/* Config space access */
			       0x0000000c 0x08011000 0x00001000>;	/* Registers */
			dcr-reg = <0x120 0x020>;
			sdr-base = <0x340>;

			/* Outbound ranges, one memory and one IO,
			 * later cannot be changed
			 */
			ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
				  0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
				  0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;

			/* Inbound 2GB range starting at 0 */
			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;

			/* This drives busses 80 to 0xbf */
			bus-range = <0x80 0xbf>;

			/* Legacy interrupts (note the weird polarity, the bridge seems
			 * to invert PCIe legacy interrupts).
			 * We are de-swizzling here because the numbers are actually for
			 * port of the root complex virtual P2P bridge. But I want
			 * to avoid putting a node for it in the tree, so the numbers
			 * below are basically de-swizzled numbers.
			 * The real slot is on idsel 0, so the swizzling is 1:1
			 */
			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
			interrupt-map = <
				0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
				0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
				0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
				0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
		};

		MSI: ppc4xx-msi@C10000000 {
			compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
			reg = < 0xC 0x10000000 0x100>;
			sdr-base = <0x36C>;
			msi-data = <0x00000000>;
			msi-mask = <0x44440000>;
			interrupt-count = <3>;
			interrupts = <0 1 2 3>;
			interrupt-parent = <&UIC3>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			#size-cells = <0>;
			interrupt-map = <0 &UIC3 0x18 1
					1 &UIC3 0x19 1
					2 &UIC3 0x1A 1
					3 &UIC3 0x1B 1>;
		};
	};
};
Commit	Line	Data
281aea45 SG	1	/*
	2	* Device Tree Source for AMCC Canyonlands (460EX)
	3	*
	4	* Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0
	7	*/
	8
	9	/dts-v1/;
	10
	11	/ {
	12	#address-cells = <2>;
	13	#size-cells = <1>;
	14	model = "amcc,canyonlands";
	15	compatible = "amcc,canyonlands";
	16	dcr-parent = <&{/cpus/cpu@0}>;
	17
	18	aliases {
	19	ethernet0 = &EMAC0;
	20	ethernet1 = &EMAC1;
	21	serial0 = &UART0;
	22	serial1 = &UART1;
	23	};
	24
27502907 SR	25	chosen {
	26	stdout-path = &UART0;
	27	};
	28
281aea45 SG	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu@0 {
	34	device_type = "cpu";
	35	model = "PowerPC,460EX";
	36	reg = <0x00000000>;
	37	clock-frequency = <0>; /* Filled in by U-Boot */
	38	timebase-frequency = <0>; /* Filled in by U-Boot */
	39	i-cache-line-size = <32>;
	40	d-cache-line-size = <32>;
	41	i-cache-size = <32768>;
	42	d-cache-size = <32768>;
	43	dcr-controller;
	44	dcr-access-method = "native";
	45	next-level-cache = <&L2C0>;
	46	};
	47	};
	48
	49	memory {
	50	device_type = "memory";
	51	reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
	52	};
	53
	54	UIC0: interrupt-controller0 {
	55	compatible = "ibm,uic-460ex","ibm,uic";
	56	interrupt-controller;
	57	cell-index = <0>;
	58	dcr-reg = <0x0c0 0x009>;
	59	#address-cells = <0>;
	60	#size-cells = <0>;
	61	#interrupt-cells = <2>;
	62	};
	63
	64	UIC1: interrupt-controller1 {
	65	compatible = "ibm,uic-460ex","ibm,uic";
	66	interrupt-controller;
	67	cell-index = <1>;
	68	dcr-reg = <0x0d0 0x009>;
	69	#address-cells = <0>;
	70	#size-cells = <0>;
	71	#interrupt-cells = <2>;
	72	interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
	73	interrupt-parent = <&UIC0>;
	74	};
	75
	76	UIC2: interrupt-controller2 {
	77	compatible = "ibm,uic-460ex","ibm,uic";
	78	interrupt-controller;
	79	cell-index = <2>;
	80	dcr-reg = <0x0e0 0x009>;
	81	#address-cells = <0>;
	82	#size-cells = <0>;
	83	#interrupt-cells = <2>;
	84	interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
	85	interrupt-parent = <&UIC0>;
	86	};
	87
	88	UIC3: interrupt-controller3 {
	89	compatible = "ibm,uic-460ex","ibm,uic";
	90	interrupt-controller;
	91	cell-index = <3>;
	92	dcr-reg = <0x0f0 0x009>;
93	#address-cells = <0>;
94	#size-cells = <0>;
95	#interrupt-cells = <2>;
96	interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
97	interrupt-parent = <&UIC0>;
98	};
99
100	SDR0: sdr {
101	compatible = "ibm,sdr-460ex";
102	dcr-reg = <0x00e 0x002>;
103	};
104
105	CPR0: cpr {
106	compatible = "ibm,cpr-460ex";
107	dcr-reg = <0x00c 0x002>;
108	};
109
110	CPM0: cpm {
111	compatible = "ibm,cpm";
112	dcr-access-method = "native";
113	dcr-reg = <0x160 0x003>;
114	unused-units = <0x00000100>;
115	idle-doze = <0x02000000>;
116	standby = <0xfeff791d>;
117	};
118
119	L2C0: l2c {
120	compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
121	dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
122	0x030 0x008>; /* L2 cache DCR's */
123	cache-line-size = <32>; /* 32 bytes */
124	cache-size = <262144>; /* L2, 256K */
125	interrupt-parent = <&UIC1>;
126	interrupts = <11 1>;
127	};
128
129	plb {
130	compatible = "ibm,plb-460ex", "ibm,plb4";
131	#address-cells = <2>;
132	#size-cells = <1>;
133	ranges;
134	clock-frequency = <0>; /* Filled in by U-Boot */
135
136	SDRAM0: sdram {
137	compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
138	dcr-reg = <0x010 0x002>;
139	};
140
141	CRYPTO: crypto@180000 {
142	compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
143	reg = <4 0x00180000 0x80400>;
144	interrupt-parent = <&UIC0>;
145	interrupts = <0x1d 0x4>;
146	};
147
148	HWRNG: hwrng@110000 {
149	compatible = "amcc,ppc460ex-rng", "ppc4xx-rng";
150	reg = <4 0x00110000 0x50>;
151	};
152
153	MAL0: mcmal {
154	compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
155	dcr-reg = <0x180 0x062>;
156	num-tx-chans = <2>;
157	num-rx-chans = <16>;
158	#address-cells = <0>;
159	#size-cells = <0>;
160	interrupt-parent = <&UIC2>;
161	interrupts = < /TXEOB/ 0x6 0x4
162	/RXEOB/ 0x7 0x4
163	/SERR/ 0x3 0x4
164	/TXDE/ 0x4 0x4
165	/RXDE/ 0x5 0x4>;
166	};
167
168	USB0: ehci@bffd0400 {
169	compatible = "ibm,usb-ehci-460ex", "usb-ehci";
170	interrupt-parent = <&UIC2>;
171	interrupts = <0x1d 4>;
172	reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
173	};
174
175	USB1: usb@bffd0000 {
176	compatible = "ohci-le";
177	reg = <4 0xbffd0000 0x60>;
178	interrupt-parent = <&UIC2>;
179	interrupts = <0x1e 4>;
180	};
181
182	USBOTG0: usbotg@bff80000 {
183	compatible = "amcc,dwc-otg";
184	reg = <0x4 0xbff80000 0x10000>;
185	interrupt-parent = <&USBOTG0>;
186	#interrupt-cells = <1>;
187	#address-cells = <0>;
188	#size-cells = <0>;
189	interrupts = <0x0 0x1 0x2>;
190	interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
191	/* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
192	/* DMA */ 0x2 &UIC0 0xc 0x4>;
193	};
194
195	SATA0: sata@bffd1000 {
196	compatible = "amcc,sata-460ex";
197	reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
198	interrupt-parent = <&UIC3>;
199	interrupts = <0x0 0x4 /* SATA */
200	0x5 0x4>; /* AHBDMA */
201	};
202
203	POB0: opb {
204	compatible = "ibm,opb-460ex", "ibm,opb";
205	#address-cells = <1>;
206	#size-cells = <1>;
207	ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
208	clock-frequency = <0>; /* Filled in by U-Boot */
209
210	EBC0: ebc {
211	compatible = "ibm,ebc-460ex", "ibm,ebc";
212	dcr-reg = <0x012 0x002>;
213	#address-cells = <2>;
214	#size-cells = <1>;
215	clock-frequency = <0>; /* Filled in by U-Boot */
216	/* ranges property is supplied by U-Boot */
217	interrupts = <0x6 0x4>;
218	interrupt-parent = <&UIC1>;
219
220	nor_flash@0,0 {
221	compatible = "amd,s29gl512n", "cfi-flash";
222	bank-width = <2>;
223	reg = <0x00000000 0x00000000 0x04000000>;
224	#address-cells = <1>;
225	#size-cells = <1>;
226	partition@0 {
227	label = "kernel";
228	reg = <0x00000000 0x001e0000>;
229	};
230	partition@1e0000 {
231	label = "dtb";
232	reg = <0x001e0000 0x00020000>;
233	};
234	partition@200000 {
235	label = "ramdisk";
236	reg = <0x00200000 0x01400000>;
237	};
238	partition@1600000 {
239	label = "jffs2";
240	reg = <0x01600000 0x00400000>;
241	};
242	partition@1a00000 {
243	label = "user";
244	reg = <0x01a00000 0x02560000>;
245	};
246	partition@3f60000 {
247	label = "env";
248	reg = <0x03f60000 0x00040000>;
249	};
250	partition@3fa0000 {
251	label = "u-boot";
252	reg = <0x03fa0000 0x00060000>;
253	};
254	};
255
256	cpld@2,0 {
257	compatible = "amcc,ppc460ex-bcsr";
258	reg = <2 0x0 0x9>;
259	};
260
261	ndfc@3,0 {
262	compatible = "ibm,ndfc";
263	reg = <0x00000003 0x00000000 0x00002000>;
264	ccr = <0x00001000>;
265	bank-settings = <0x80002222>;
266	#address-cells = <1>;
267	#size-cells = <1>;
268
269	nand {
270	#address-cells = <1>;
271	#size-cells = <1>;
272
273	partition@0 {
274	label = "u-boot";
275	reg = <0x00000000 0x00100000>;
276	};
277	partition@100000 {
278	label = "user";
279	reg = <0x00000000 0x03f00000>;
280	};
281	};
282	};
283	};
284
285	UART0: serial@ef600300 {
286	device_type = "serial";
27502907	287	reg-shift = <0>;
281aea45 SG	288	compatible = "ns16550";
	289	reg = <0xef600300 0x00000008>;
	290	virtual-reg = <0xef600300>;
	291	clock-frequency = <0>; /* Filled in by U-Boot */
	292	current-speed = <0>; /* Filled in by U-Boot */
	293	interrupt-parent = <&UIC1>;
	294	interrupts = <0x1 0x4>;
	295	};
	296
	297	UART1: serial@ef600400 {
	298	device_type = "serial";
27502907	299	reg-shift = <0>;
281aea45 SG	300	compatible = "ns16550";
	301	reg = <0xef600400 0x00000008>;
	302	virtual-reg = <0xef600400>;
	303	clock-frequency = <0>; /* Filled in by U-Boot */
	304	current-speed = <0>; /* Filled in by U-Boot */
	305	interrupt-parent = <&UIC0>;
	306	interrupts = <0x1 0x4>;
	307	};
	308
	309	IIC0: i2c@ef600700 {
	310	compatible = "ibm,iic-460ex", "ibm,iic";
	311	reg = <0xef600700 0x00000014>;
	312	interrupt-parent = <&UIC0>;
	313	interrupts = <0x2 0x4>;
	314	#address-cells = <1>;
	315	#size-cells = <0>;
	316	rtc@68 {
	317	compatible = "stm,m41t80";
	318	reg = <0x68>;
	319	interrupt-parent = <&UIC2>;
	320	interrupts = <0x19 0x8>;
	321	};
	322	sttm@48 {
	323	compatible = "ad,ad7414";
	324	reg = <0x48>;
	325	interrupt-parent = <&UIC1>;
	326	interrupts = <0x14 0x8>;
	327	};
	328	};
	329
	330	IIC1: i2c@ef600800 {
	331	compatible = "ibm,iic-460ex", "ibm,iic";
	332	reg = <0xef600800 0x00000014>;
	333	interrupt-parent = <&UIC0>;
	334	interrupts = <0x3 0x4>;
	335	};
	336
	337	GPIO0: gpio@ef600b00 {
	338	compatible = "ibm,ppc4xx-gpio";
	339	reg = <0xef600b00 0x00000048>;
	340	gpio-controller;
	341	};
	342
	343	ZMII0: emac-zmii@ef600d00 {
	344	compatible = "ibm,zmii-460ex", "ibm,zmii";
	345	reg = <0xef600d00 0x0000000c>;
	346	};
	347
	348	RGMII0: emac-rgmii@ef601500 {
	349	compatible = "ibm,rgmii-460ex", "ibm,rgmii";
	350	reg = <0xef601500 0x00000008>;
	351	has-mdio;
	352	};
	353
	354	TAH0: emac-tah@ef601350 {
	355	compatible = "ibm,tah-460ex", "ibm,tah";
	356	reg = <0xef601350 0x00000030>;
	357	};
	358
	359	TAH1: emac-tah@ef601450 {
	360	compatible = "ibm,tah-460ex", "ibm,tah";
	361	reg = <0xef601450 0x00000030>;
	362	};
	363
364	EMAC0: ethernet@ef600e00 {
365	device_type = "network";
366	compatible = "ibm,emac-460ex", "ibm,emac4sync";
367	interrupt-parent = <&EMAC0>;
368	interrupts = <0x0 0x1>;
369	#interrupt-cells = <1>;
370	#address-cells = <0>;
371	#size-cells = <0>;
372	interrupt-map = </Status/ 0x0 &UIC2 0x10 0x4
373	/Wake/ 0x1 &UIC2 0x14 0x4>;
374	reg = <0xef600e00 0x000000c4>;
375	local-mac-address = [000000000000]; /* Filled in by U-Boot */
376	mal-device = <&MAL0>;
377	mal-tx-channel = <0>;
378	mal-rx-channel = <0>;
379	cell-index = <0>;
380	max-frame-size = <9000>;
381	rx-fifo-size = <4096>;
382	tx-fifo-size = <2048>;
383	rx-fifo-size-gige = <16384>;
384	phy-mode = "rgmii";
385	phy-map = <0x00000000>;
386	rgmii-device = <&RGMII0>;
387	rgmii-channel = <0>;
388	tah-device = <&TAH0>;
389	tah-channel = <0>;
390	has-inverted-stacr-oc;
391	has-new-stacr-staopc;
392	};
393
394	EMAC1: ethernet@ef600f00 {
395	device_type = "network";
396	compatible = "ibm,emac-460ex", "ibm,emac4sync";
397	interrupt-parent = <&EMAC1>;
398	interrupts = <0x0 0x1>;
399	#interrupt-cells = <1>;
400	#address-cells = <0>;
401	#size-cells = <0>;
402	interrupt-map = </Status/ 0x0 &UIC2 0x11 0x4
403	/Wake/ 0x1 &UIC2 0x15 0x4>;
404	reg = <0xef600f00 0x000000c4>;
405	local-mac-address = [000000000000]; /* Filled in by U-Boot */
406	mal-device = <&MAL0>;
407	mal-tx-channel = <1>;
408	mal-rx-channel = <8>;
409	cell-index = <1>;
410	max-frame-size = <9000>;
411	rx-fifo-size = <4096>;
412	tx-fifo-size = <2048>;
413	rx-fifo-size-gige = <16384>;
414	phy-mode = "rgmii";
415	phy-map = <0x00000000>;
416	rgmii-device = <&RGMII0>;
417	rgmii-channel = <1>;
418	tah-device = <&TAH1>;
419	tah-channel = <1>;
420	has-inverted-stacr-oc;
421	has-new-stacr-staopc;
422	mdio-device = <&EMAC0>;
423	};
424	};
425
426	PCIX0: pci@c0ec00000 {
427	device_type = "pci";
428	#interrupt-cells = <1>;
429	#size-cells = <2>;
430	#address-cells = <3>;
431	compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
432	primary;
433	large-inbound-windows;
434	enable-msi-hole;
435	reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
436	0x00000000 0x00000000 0x00000000 /* no IACK cycles */
437	0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
438	0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
439	0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
440
441	/* Outbound ranges, one memory and one IO,
442	* later cannot be changed
443	*/
444	ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
445	0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
446	0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
447
448	/* Inbound 2GB range starting at 0 */
449	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
450
451	/* This drives busses 0 to 0x3f */
452	bus-range = <0x0 0x3f>;
453
454	/* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
455	interrupt-map-mask = <0x0 0x0 0x0 0x0>;
456	interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
457	};
458
459	PCIE0: pciex@d00000000 {
460	device_type = "pci";
461	#interrupt-cells = <1>;
462	#size-cells = <2>;
463	#address-cells = <3>;
464	compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
465	primary;
466	port = <0x0>; /* port number */
467	reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
468	0x0000000c 0x08010000 0x00001000>; /* Registers */
469	dcr-reg = <0x100 0x020>;
470	sdr-base = <0x300>;
471
472	/* Outbound ranges, one memory and one IO,
473	* later cannot be changed
474	*/
475	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
476	0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
477	0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
478
479	/* Inbound 2GB range starting at 0 */
480	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
481
482	/* This drives busses 40 to 0x7f */
483	bus-range = <0x40 0x7f>;
484
485	/* Legacy interrupts (note the weird polarity, the bridge seems
486	* to invert PCIe legacy interrupts).
487	* We are de-swizzling here because the numbers are actually for
488	* port of the root complex virtual P2P bridge. But I want
489	* to avoid putting a node for it in the tree, so the numbers
490	* below are basically de-swizzled numbers.
491	* The real slot is on idsel 0, so the swizzling is 1:1
492	*/
493	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
494	interrupt-map = <
495	0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
496	0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
497	0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
498	0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
499	};
500
501	PCIE1: pciex@d20000000 {
502	device_type = "pci";
503	#interrupt-cells = <1>;
504	#size-cells = <2>;
505	#address-cells = <3>;
506	compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
507	primary;
508	port = <0x1>; /* port number */
509	reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
510	0x0000000c 0x08011000 0x00001000>; /* Registers */
511	dcr-reg = <0x120 0x020>;
512	sdr-base = <0x340>;
513
514	/* Outbound ranges, one memory and one IO,
515	* later cannot be changed
516	*/
517	ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
518	0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
519	0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
520
521	/* Inbound 2GB range starting at 0 */
522	dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
523
524	/* This drives busses 80 to 0xbf */
525	bus-range = <0x80 0xbf>;
526
527	/* Legacy interrupts (note the weird polarity, the bridge seems
528	* to invert PCIe legacy interrupts).
529	* We are de-swizzling here because the numbers are actually for
530	* port of the root complex virtual P2P bridge. But I want
531	* to avoid putting a node for it in the tree, so the numbers
532	* below are basically de-swizzled numbers.
533	* The real slot is on idsel 0, so the swizzling is 1:1
534	*/
535	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
536	interrupt-map = <
537	0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
538	0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
539	0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
540	0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
541	};
542
543	MSI: ppc4xx-msi@C10000000 {
544	compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
545	reg = < 0xC 0x10000000 0x100>;
546	sdr-base = <0x36C>;
547	msi-data = <0x00000000>;
548	msi-mask = <0x44440000>;
549	interrupt-count = <3>;
550	interrupts = <0 1 2 3>;
551	interrupt-parent = <&UIC3>;
552	#interrupt-cells = <1>;
553	#address-cells = <0>;
554	#size-cells = <0>;
555	interrupt-map = <0 &UIC3 0x18 1
556	1 &UIC3 0x19 1
557	2 &UIC3 0x1A 1
558	3 &UIC3 0x1B 1>;
559	};
560	};
561	};