[people/ms/u-boot.git] / arch / powerpc / include / asm / 4xx_pcie.h

/*
 * Copyright (c) 2005 Cisco Systems.  All rights reserved.
 * Roland Dreier <rolandd@cisco.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __4XX_PCIE_H
#define __4XX_PCIE_H

#include <ppc4xx.h>
#include <pci.h>

#define DCRN_SDR0_CFGADDR	0x00e
#define DCRN_SDR0_CFGDATA	0x00f

#if defined(CONFIG_440SPE)
#define CONFIG_SYS_PCIE_NR_PORTS	3

#define CONFIG_SYS_PCIE_ADDR_HIGH	0x0000000d

#define DCRN_PCIE0_BASE		0x100
#define DCRN_PCIE1_BASE		0x120
#define DCRN_PCIE2_BASE		0x140

#define PCIE0_SDR		0x300
#define PCIE1_SDR		0x340
#define PCIE2_SDR		0x370
#endif

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define CONFIG_SYS_PCIE_NR_PORTS	2

#define CONFIG_SYS_PCIE_ADDR_HIGH	0x0000000d

#define DCRN_PCIE0_BASE		0x100
#define DCRN_PCIE1_BASE		0x120

#define PCIE0_SDR		0x300
#define PCIE1_SDR		0x340
#endif

#if defined(CONFIG_405EX)
#define CONFIG_SYS_PCIE_NR_PORTS	2

#define CONFIG_SYS_PCIE_ADDR_HIGH	0x00000000

#define	DCRN_PCIE0_BASE		0x040
#define	DCRN_PCIE1_BASE		0x060

#define PCIE0_SDR		0x400
#define PCIE1_SDR		0x440
#endif

#define PCIE0			DCRN_PCIE0_BASE
#define PCIE1			DCRN_PCIE1_BASE
#define PCIE2			DCRN_PCIE2_BASE

#define DCRN_PEGPL_CFGBAH(base)		(base + 0x00)
#define DCRN_PEGPL_CFGBAL(base)		(base + 0x01)
#define DCRN_PEGPL_CFGMSK(base)		(base + 0x02)
#define DCRN_PEGPL_MSGBAH(base)		(base + 0x03)
#define DCRN_PEGPL_MSGBAL(base)		(base + 0x04)
#define DCRN_PEGPL_MSGMSK(base)		(base + 0x05)
#define DCRN_PEGPL_OMR1BAH(base)	(base + 0x06)
#define DCRN_PEGPL_OMR1BAL(base)	(base + 0x07)
#define DCRN_PEGPL_OMR1MSKH(base)	(base + 0x08)
#define DCRN_PEGPL_OMR1MSKL(base)	(base + 0x09)
#define DCRN_PEGPL_REGBAH(base)		(base + 0x12)
#define DCRN_PEGPL_REGBAL(base)		(base + 0x13)
#define DCRN_PEGPL_REGMSK(base)		(base + 0x14)
#define DCRN_PEGPL_SPECIAL(base)	(base + 0x15)
#define DCRN_PEGPL_CFG(base)		(base + 0x16)

/*
 * System DCRs (SDRs)
 */
#define PESDR0_PLLLCT1		0x03a0
#define PESDR0_PLLLCT2		0x03a1
#define PESDR0_PLLLCT3		0x03a2

/* common regs, at for all 4xx with PCIe core */
#define SDRN_PESDR_UTLSET1(n)		(sdr_base(n) + 0x00)
#define SDRN_PESDR_UTLSET2(n)		(sdr_base(n) + 0x01)
#define SDRN_PESDR_DLPSET(n)		(sdr_base(n) + 0x02)
#define SDRN_PESDR_LOOP(n)		(sdr_base(n) + 0x03)
#define SDRN_PESDR_RCSSET(n)		(sdr_base(n) + 0x04)
#define SDRN_PESDR_RCSSTS(n)		(sdr_base(n) + 0x05)

#if defined(CONFIG_440SPE)
#define SDRN_PESDR_HSSL0SET1(n)		(sdr_base(n) + 0x06)
#define SDRN_PESDR_HSSL0SET2(n)		(sdr_base(n) + 0x07)
#define SDRN_PESDR_HSSL0STS(n)		(sdr_base(n) + 0x08)
#define SDRN_PESDR_HSSL1SET1(n)		(sdr_base(n) + 0x09)
#define SDRN_PESDR_HSSL1SET2(n)		(sdr_base(n) + 0x0a)
#define SDRN_PESDR_HSSL1STS(n)		(sdr_base(n) + 0x0b)
#define SDRN_PESDR_HSSL2SET1(n)		(sdr_base(n) + 0x0c)
#define SDRN_PESDR_HSSL2SET2(n)		(sdr_base(n) + 0x0d)
#define SDRN_PESDR_HSSL2STS(n)		(sdr_base(n) + 0x0e)
#define SDRN_PESDR_HSSL3SET1(n)		(sdr_base(n) + 0x0f)
#define SDRN_PESDR_HSSL3SET2(n)		(sdr_base(n) + 0x10)
#define SDRN_PESDR_HSSL3STS(n)		(sdr_base(n) + 0x11)

#define PESDR0_UTLSET1		0x0300
#define PESDR0_UTLSET2		0x0301
#define PESDR0_DLPSET		0x0302
#define PESDR0_LOOP		0x0303
#define PESDR0_RCSSET		0x0304
#define PESDR0_RCSSTS		0x0305
#define PESDR0_HSSL0SET1	0x0306
#define PESDR0_HSSL0SET2	0x0307
#define PESDR0_HSSL0STS		0x0308
#define PESDR0_HSSL1SET1	0x0309
#define PESDR0_HSSL1SET2	0x030a
#define PESDR0_HSSL1STS		0x030b
#define PESDR0_HSSL2SET1	0x030c
#define PESDR0_HSSL2SET2	0x030d
#define PESDR0_HSSL2STS		0x030e
#define PESDR0_HSSL3SET1	0x030f
#define PESDR0_HSSL3SET2	0x0310
#define PESDR0_HSSL3STS		0x0311
#define PESDR0_HSSL4SET1	0x0312
#define PESDR0_HSSL4SET2	0x0313
#define PESDR0_HSSL4STS		0x0314
#define PESDR0_HSSL5SET1	0x0315
#define PESDR0_HSSL5SET2	0x0316
#define PESDR0_HSSL5STS		0x0317
#define PESDR0_HSSL6SET1	0x0318
#define PESDR0_HSSL6SET2	0x0319
#define PESDR0_HSSL6STS		0x031a
#define PESDR0_HSSL7SET1	0x031b
#define PESDR0_HSSL7SET2	0x031c
#define PESDR0_HSSL7STS		0x031d
#define PESDR0_HSSCTLSET	0x031e
#define PESDR0_LANE_ABCD	0x031f
#define PESDR0_LANE_EFGH	0x0320

#define PESDR1_UTLSET1		0x0340
#define PESDR1_UTLSET2		0x0341
#define PESDR1_DLPSET		0x0342
#define PESDR1_LOOP		0x0343
#define PESDR1_RCSSET		0x0344
#define PESDR1_RCSSTS		0x0345
#define PESDR1_HSSL0SET1	0x0346
#define PESDR1_HSSL0SET2	0x0347
#define PESDR1_HSSL0STS		0x0348
#define PESDR1_HSSL1SET1	0x0349
#define PESDR1_HSSL1SET2	0x034a
#define PESDR1_HSSL1STS		0x034b
#define PESDR1_HSSL2SET1	0x034c
#define PESDR1_HSSL2SET2	0x034d
#define PESDR1_HSSL2STS		0x034e
#define PESDR1_HSSL3SET1	0x034f
#define PESDR1_HSSL3SET2	0x0350
#define PESDR1_HSSL3STS		0x0351
#define PESDR1_HSSCTLSET	0x0352
#define PESDR1_LANE_ABCD	0x0353

#define PESDR2_UTLSET1		0x0370
#define PESDR2_UTLSET2		0x0371
#define PESDR2_DLPSET		0x0372
#define PESDR2_LOOP		0x0373
#define PESDR2_RCSSET		0x0374
#define PESDR2_RCSSTS		0x0375
#define PESDR2_HSSL0SET1	0x0376
#define PESDR2_HSSL0SET2	0x0377
#define PESDR2_HSSL0STS		0x0378
#define PESDR2_HSSL1SET1	0x0379
#define PESDR2_HSSL1SET2	0x037a
#define PESDR2_HSSL1STS		0x037b
#define PESDR2_HSSL2SET1	0x037c
#define PESDR2_HSSL2SET2	0x037d
#define PESDR2_HSSL2STS		0x037e
#define PESDR2_HSSL3SET1	0x037f
#define PESDR2_HSSL3SET2	0x0380
#define PESDR2_HSSL3STS		0x0381
#define PESDR2_HSSCTLSET	0x0382
#define PESDR2_LANE_ABCD	0x0383

#elif defined(CONFIG_405EX)

#define SDRN_PESDR_PHYSET1(n)		(sdr_base(n) + 0x06)
#define SDRN_PESDR_PHYSET2(n)		(sdr_base(n) + 0x07)
#define SDRN_PESDR_BIST(n)		(sdr_base(n) + 0x08)
#define SDRN_PESDR_LPB(n)		(sdr_base(n) + 0x0b)
#define SDRN_PESDR_PHYSTA(n)		(sdr_base(n) + 0x0c)

#define PESDR0_UTLSET1		0x0400
#define PESDR0_UTLSET2		0x0401
#define PESDR0_DLPSET		0x0402
#define PESDR0_LOOP		0x0403
#define PESDR0_RCSSET		0x0404
#define PESDR0_RCSSTS		0x0405
#define PESDR0_PHYSET1		0x0406
#define PESDR0_PHYSET2		0x0407
#define PESDR0_BIST		0x0408
#define PESDR0_LPB		0x040B
#define PESDR0_PHYSTA		0x040C

#define PESDR1_UTLSET1		0x0440
#define PESDR1_UTLSET2		0x0441
#define PESDR1_DLPSET		0x0442
#define PESDR1_LOOP		0x0443
#define PESDR1_RCSSET		0x0444
#define PESDR1_RCSSTS		0x0445
#define PESDR1_PHYSET1		0x0446
#define PESDR1_PHYSET2		0x0447
#define PESDR1_BIST		0x0448
#define PESDR1_LPB		0x044B
#define PESDR1_PHYSTA		0x044C

#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)

#define PESDR0_L0BIST		0x0308	/* PE0 L0 built in self test */
#define PESDR0_L0BISTSTS	0x0309	/* PE0 L0 built in self test status */
#define PESDR0_L0CDRCTL		0x030A	/* PE0 L0 CDR control */
#define PESDR0_L0DRV		0x030B	/* PE0 L0 drive */
#define PESDR0_L0REC		0x030C	/* PE0 L0 receiver */
#define PESDR0_L0LPB		0x030D	/* PE0 L0 loopback */
#define PESDR0_L0CLK		0x030E	/* PE0 L0 clocking */
#define PESDR0_PHY_CTL_RST	0x030F	/* PE0 PHY control reset */
#define PESDR0_RSTSTA		0x0310	/* PE0 reset status */
#define PESDR0_OBS		0x0311	/* PE0 observation register */
#define PESDR0_L0ERRC		0x0320	/* PE0 L0 error counter */

#define PESDR1_L0BIST		0x0348	/* PE1 L0 built in self test */
#define PESDR1_L1BIST		0x0349	/* PE1 L1 built in self test */
#define PESDR1_L2BIST		0x034A	/* PE1 L2 built in self test */
#define PESDR1_L3BIST		0x034B	/* PE1 L3 built in self test */
#define PESDR1_L0BISTSTS	0x034C	/* PE1 L0 built in self test status */
#define PESDR1_L1BISTSTS	0x034D	/* PE1 L1 built in self test status */
#define PESDR1_L2BISTSTS	0x034E	/* PE1 L2 built in self test status */
#define PESDR1_L3BISTSTS	0x034F	/* PE1 L3 built in self test status */
#define PESDR1_L0CDRCTL		0x0350	/* PE1 L0 CDR control */
#define PESDR1_L1CDRCTL		0x0351	/* PE1 L1 CDR control */
#define PESDR1_L2CDRCTL		0x0352	/* PE1 L2 CDR control */
#define PESDR1_L3CDRCTL		0x0353	/* PE1 L3 CDR control */
#define PESDR1_L0DRV		0x0354	/* PE1 L0 drive */
#define PESDR1_L1DRV		0x0355	/* PE1 L1 drive */
#define PESDR1_L2DRV		0x0356	/* PE1 L2 drive */
#define PESDR1_L3DRV		0x0357	/* PE1 L3 drive */
#define PESDR1_L0REC		0x0358	/* PE1 L0 receiver */
#define PESDR1_L1REC		0x0359	/* PE1 L1 receiver */
#define PESDR1_L2REC		0x035A	/* PE1 L2 receiver */
#define PESDR1_L3REC		0x035B	/* PE1 L3 receiver */
#define PESDR1_L0LPB		0x035C	/* PE1 L0 loopback */
#define PESDR1_L1LPB		0x035D	/* PE1 L1 loopback */
#define PESDR1_L2LPB		0x035E	/* PE1 L2 loopback */
#define PESDR1_L3LPB		0x035F	/* PE1 L3 loopback */
#define PESDR1_L0CLK		0x0360	/* PE1 L0 clocking */
#define PESDR1_L1CLK		0x0361	/* PE1 L1 clocking */
#define PESDR1_L2CLK		0x0362	/* PE1 L2 clocking */
#define PESDR1_L3CLK		0x0363	/* PE1 L3 clocking */
#define PESDR1_PHY_CTL_RST	0x0364	/* PE1 PHY control reset */
#define PESDR1_RSTSTA		0x0365	/* PE1 reset status */
#define PESDR1_OBS		0x0366	/* PE1 observation register */
#define PESDR1_L0ERRC		0x0368	/* PE1 L0 error counter */
#define PESDR1_L1ERRC		0x0369	/* PE1 L1 error counter */
#define PESDR1_L2ERRC		0x036A	/* PE1 L2 error counter */
#define PESDR1_L3ERRC		0x036B	/* PE1 L3 error counter */
#define PESDR0_IHS1		0x036C	/* PE interrupt handler interfact setting 1 */
#define PESDR0_IHS2		0x036D	/* PE interrupt handler interfact setting 2 */

#endif

/* SDR Bit Mappings */
#define PESDRx_RCSSET_HLDPLB	0x10000000
#define PESDRx_RCSSET_RSTGU	0x01000000
#define PESDRx_RCSSET_RDY       0x00100000
#define PESDRx_RCSSET_RSTDL     0x00010000
#define PESDRx_RCSSET_RSTPYN    0x00001000

#define PESDRx_RCSSTS_PLBIDL	0x10000000
#define PESDRx_RCSSTS_HRSTRQ	0x01000000
#define PESDRx_RCSSTS_PGRST	0x00100000
#define PESDRx_RCSSTS_VC0ACT	0x00010000
#define PESDRx_RCSSTS_BMEN	0x00000100

/*
 * UTL register offsets
 */
#define	PEUTL_PBCTL		0x00
#define PEUTL_PBBSZ		0x20
#define PEUTL_OPDBSZ		0x68
#define PEUTL_IPHBSZ		0x70
#define PEUTL_IPDBSZ		0x78
#define PEUTL_OUTTR		0x90
#define PEUTL_INTR		0x98
#define PEUTL_PCTL		0xa0
#define	PEUTL_RCSTA		0xb0
#define PEUTL_RCIRQEN		0xb8

/*
 * Config space register offsets
 */
#define PECFG_BAR0LMPA		0x210
#define PECFG_BAR0HMPA		0x214
#define PECFG_BAR1MPA		0x218
#define PECFG_BAR2LMPA		0x220
#define PECFG_BAR2HMPA		0x224

#define PECFG_PIMEN		0x33c
#define PECFG_PIM0LAL		0x340
#define PECFG_PIM0LAH		0x344
#define PECFG_PIM1LAL		0x348
#define PECFG_PIM1LAH		0x34c
#define PECFG_PIM01SAL		0x350
#define PECFG_PIM01SAH		0x354

#define PECFG_POM0LAL		0x380
#define PECFG_POM0LAH		0x384

#define SDR_READ(offset) ({\
	mtdcr(DCRN_SDR0_CFGADDR, offset); \
	mfdcr(DCRN_SDR0_CFGDATA);})

#define SDR_WRITE(offset, data) ({\
	mtdcr(DCRN_SDR0_CFGADDR, offset); \
	mtdcr(DCRN_SDR0_CFGDATA,data);})

#define GPL_DMER_MASK_DISA	0x02000000

#define U64_TO_U32_LOW(val)	((u32)((val) & 0x00000000ffffffffULL))
#define U64_TO_U32_HIGH(val)	((u32)((val) >> 32))

/*
 * Prototypes
 */
int ppc4xx_init_pcie(void);
int ppc4xx_init_pcie_rootport(int port);
int ppc4xx_init_pcie_endport(int port);
void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
int pcie_hose_scan(struct pci_controller *hose, int bus);

/*
 * Function to determine root port or endport from env variable.
 */
static inline int is_end_point(int port)
{
	char s[10], *tk;
	char *pcie_mode = getenv("pcie_mode");

	if (pcie_mode == NULL)
		return 0;

	strcpy(s, pcie_mode);
	tk = strtok(s, ":");

	switch (port) {
	case 0:
		if (tk != NULL) {
			if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
				return 1;
			else
				return 0;
		}
		else
			return 0;

	case 1:
		tk = strtok(NULL, ":");
		if (tk != NULL) {
			if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
				return 1;
			else
				return 0;
		}
		else
			return 0;

	case 2:
		tk = strtok(NULL, ":");
		if (tk != NULL)
			tk = strtok(NULL, ":");
		if (tk != NULL) {
			if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
				return 1;
			else
				return 0;
		}
		else
			return 0;
	}

	return 0;
}

static inline void mdelay(int n)
{
	u32 ms = n;

	while (ms--)
		udelay(1000);
}

#if defined(PCIE0_SDR)
static inline u32 sdr_base(int port)
{
	switch (port) {
	default:	/* to satisfy compiler */
	case 0:
		return PCIE0_SDR;
	case 1:
		return PCIE1_SDR;
#if CONFIG_SYS_PCIE_NR_PORTS > 2
	case 2:
		return PCIE2_SDR;
#endif
	}
}
#endif /* defined(PCIE0_SDR) */

#endif /* __4XX_PCIE_H */
Commit	Line	Data
692519b1 RJ	1	/*
	2	* Copyright (c) 2005 Cisco Systems. All rights reserved.
	3	* Roland Dreier <rolandd@cisco.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
	10
026f7110 SR	11	#ifndef __4XX_PCIE_H
026f7110 SR	12	#define __4XX_PCIE_H
692519b1	13
24bfedbd	14	#include <ppc4xx.h>
5cd0130e	15	#include <pci.h>
24bfedbd	16
692519b1 RJ	17	#define DCRN_SDR0_CFGADDR 0x00e
	18	#define DCRN_SDR0_CFGDATA 0x00f
	19
03d344bb	20	#if defined(CONFIG_440SPE)
6d0f6bcf	21	#define CONFIG_SYS_PCIE_NR_PORTS 3
97923770	22
6d0f6bcf	23	#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
97923770	24
692519b1 RJ	25	#define DCRN_PCIE0_BASE 0x100
	26	#define DCRN_PCIE1_BASE 0x120
	27	#define DCRN_PCIE2_BASE 0x140
97923770 SR	28
	29	#define PCIE0_SDR 0x300
	30	#define PCIE1_SDR 0x340
	31	#define PCIE2_SDR 0x370
03d344bb SR	32	#endif
03d344bb SR	33
999ecd5a	34	#if defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
6d0f6bcf	35	#define CONFIG_SYS_PCIE_NR_PORTS 2
999ecd5a	36
6d0f6bcf	37	#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
999ecd5a SR	38
	39	#define DCRN_PCIE0_BASE 0x100
	40	#define DCRN_PCIE1_BASE 0x120
	41
	42	#define PCIE0_SDR 0x300
	43	#define PCIE1_SDR 0x340
	44	#endif
	45
03d344bb	46	#if defined(CONFIG_405EX)
6d0f6bcf	47	#define CONFIG_SYS_PCIE_NR_PORTS 2
97923770	48
6d0f6bcf	49	#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000
97923770	50
03d344bb SR	51	#define DCRN_PCIE0_BASE 0x040
03d344bb SR	52	#define DCRN_PCIE1_BASE 0x060
97923770 SR	53
	54	#define PCIE0_SDR 0x400
	55	#define PCIE1_SDR 0x440
03d344bb SR	56	#endif
03d344bb SR	57
692519b1 RJ	58	#define PCIE0 DCRN_PCIE0_BASE
	59	#define PCIE1 DCRN_PCIE1_BASE
	60	#define PCIE2 DCRN_PCIE2_BASE
	61
	62	#define DCRN_PEGPL_CFGBAH(base) (base + 0x00)
	63	#define DCRN_PEGPL_CFGBAL(base) (base + 0x01)
	64	#define DCRN_PEGPL_CFGMSK(base) (base + 0x02)
	65	#define DCRN_PEGPL_MSGBAH(base) (base + 0x03)
	66	#define DCRN_PEGPL_MSGBAL(base) (base + 0x04)
	67	#define DCRN_PEGPL_MSGMSK(base) (base + 0x05)
	68	#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06)
	69	#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07)
	70	#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08)
	71	#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09)
	72	#define DCRN_PEGPL_REGBAH(base) (base + 0x12)
	73	#define DCRN_PEGPL_REGBAL(base) (base + 0x13)
	74	#define DCRN_PEGPL_REGMSK(base) (base + 0x14)
	75	#define DCRN_PEGPL_SPECIAL(base) (base + 0x15)
15ee4734	76	#define DCRN_PEGPL_CFG(base) (base + 0x16)
692519b1 RJ	77
	78	/*
	79	* System DCRs (SDRs)
	80	*/
	81	#define PESDR0_PLLLCT1 0x03a0
	82	#define PESDR0_PLLLCT2 0x03a1
	83	#define PESDR0_PLLLCT3 0x03a2
	84
999ecd5a	85	/* common regs, at for all 4xx with PCIe core */
03d344bb SR	86	#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00)
	87	#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01)
	88	#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02)
	89	#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03)
	90	#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04)
	91	#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05)
	92
	93	#if defined(CONFIG_440SPE)
	94	#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06)
	95	#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07)
	96	#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08)
	97	#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09)
	98	#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a)
	99	#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b)
	100	#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c)
	101	#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d)
	102	#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e)
	103	#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f)
	104	#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10)
	105	#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11)
	106
692519b1 RJ	107	#define PESDR0_UTLSET1 0x0300
	108	#define PESDR0_UTLSET2 0x0301
	109	#define PESDR0_DLPSET 0x0302
	110	#define PESDR0_LOOP 0x0303
	111	#define PESDR0_RCSSET 0x0304
	112	#define PESDR0_RCSSTS 0x0305
	113	#define PESDR0_HSSL0SET1 0x0306
	114	#define PESDR0_HSSL0SET2 0x0307
	115	#define PESDR0_HSSL0STS 0x0308
	116	#define PESDR0_HSSL1SET1 0x0309
	117	#define PESDR0_HSSL1SET2 0x030a
	118	#define PESDR0_HSSL1STS 0x030b
	119	#define PESDR0_HSSL2SET1 0x030c
	120	#define PESDR0_HSSL2SET2 0x030d
	121	#define PESDR0_HSSL2STS 0x030e
	122	#define PESDR0_HSSL3SET1 0x030f
	123	#define PESDR0_HSSL3SET2 0x0310
	124	#define PESDR0_HSSL3STS 0x0311
	125	#define PESDR0_HSSL4SET1 0x0312
	126	#define PESDR0_HSSL4SET2 0x0313
	127	#define PESDR0_HSSL4STS 0x0314
	128	#define PESDR0_HSSL5SET1 0x0315
	129	#define PESDR0_HSSL5SET2 0x0316
	130	#define PESDR0_HSSL5STS 0x0317
	131	#define PESDR0_HSSL6SET1 0x0318
	132	#define PESDR0_HSSL6SET2 0x0319
	133	#define PESDR0_HSSL6STS 0x031a
	134	#define PESDR0_HSSL7SET1 0x031b
	135	#define PESDR0_HSSL7SET2 0x031c
	136	#define PESDR0_HSSL7STS 0x031d
	137	#define PESDR0_HSSCTLSET 0x031e
	138	#define PESDR0_LANE_ABCD 0x031f
	139	#define PESDR0_LANE_EFGH 0x0320
	140
	141	#define PESDR1_UTLSET1 0x0340
	142	#define PESDR1_UTLSET2 0x0341
	143	#define PESDR1_DLPSET 0x0342
	144	#define PESDR1_LOOP 0x0343
	145	#define PESDR1_RCSSET 0x0344
	146	#define PESDR1_RCSSTS 0x0345
	147	#define PESDR1_HSSL0SET1 0x0346
	148	#define PESDR1_HSSL0SET2 0x0347
	149	#define PESDR1_HSSL0STS 0x0348
	150	#define PESDR1_HSSL1SET1 0x0349
	151	#define PESDR1_HSSL1SET2 0x034a
	152	#define PESDR1_HSSL1STS 0x034b
	153	#define PESDR1_HSSL2SET1 0x034c
	154	#define PESDR1_HSSL2SET2 0x034d
	155	#define PESDR1_HSSL2STS 0x034e
	156	#define PESDR1_HSSL3SET1 0x034f
	157	#define PESDR1_HSSL3SET2 0x0350
	158	#define PESDR1_HSSL3STS 0x0351
	159	#define PESDR1_HSSCTLSET 0x0352
	160	#define PESDR1_LANE_ABCD 0x0353
	161
	162	#define PESDR2_UTLSET1 0x0370
	163	#define PESDR2_UTLSET2 0x0371
	164	#define PESDR2_DLPSET 0x0372
	165	#define PESDR2_LOOP 0x0373
	166	#define PESDR2_RCSSET 0x0374
	167	#define PESDR2_RCSSTS 0x0375
	168	#define PESDR2_HSSL0SET1 0x0376
	169	#define PESDR2_HSSL0SET2 0x0377
	170	#define PESDR2_HSSL0STS 0x0378
171	#define PESDR2_HSSL1SET1 0x0379
172	#define PESDR2_HSSL1SET2 0x037a
173	#define PESDR2_HSSL1STS 0x037b
174	#define PESDR2_HSSL2SET1 0x037c
175	#define PESDR2_HSSL2SET2 0x037d
176	#define PESDR2_HSSL2STS 0x037e
177	#define PESDR2_HSSL3SET1 0x037f
178	#define PESDR2_HSSL3SET2 0x0380
179	#define PESDR2_HSSL3STS 0x0381
180	#define PESDR2_HSSCTLSET 0x0382
181	#define PESDR2_LANE_ABCD 0x0383
182
03d344bb SR	183	#elif defined(CONFIG_405EX)
	184
	185	#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06)
	186	#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07)
	187	#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08)
	188	#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b)
	189	#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c)
	190
	191	#define PESDR0_UTLSET1 0x0400
	192	#define PESDR0_UTLSET2 0x0401
	193	#define PESDR0_DLPSET 0x0402
	194	#define PESDR0_LOOP 0x0403
	195	#define PESDR0_RCSSET 0x0404
	196	#define PESDR0_RCSSTS 0x0405
	197	#define PESDR0_PHYSET1 0x0406
	198	#define PESDR0_PHYSET2 0x0407
	199	#define PESDR0_BIST 0x0408
	200	#define PESDR0_LPB 0x040B
	201	#define PESDR0_PHYSTA 0x040C
	202
	203	#define PESDR1_UTLSET1 0x0440
	204	#define PESDR1_UTLSET2 0x0441
	205	#define PESDR1_DLPSET 0x0442
	206	#define PESDR1_LOOP 0x0443
	207	#define PESDR1_RCSSET 0x0444
	208	#define PESDR1_RCSSTS 0x0445
	209	#define PESDR1_PHYSET1 0x0446
	210	#define PESDR1_PHYSET2 0x0447
	211	#define PESDR1_BIST 0x0448
	212	#define PESDR1_LPB 0x044B
	213	#define PESDR1_PHYSTA 0x044C
	214
999ecd5a SR	215	#elif defined(CONFIG_460EX) \|\| defined(CONFIG_460GT)
	216
	217	#define PESDR0_L0BIST 0x0308 /* PE0 L0 built in self test */
	218	#define PESDR0_L0BISTSTS 0x0309 /* PE0 L0 built in self test status */
	219	#define PESDR0_L0CDRCTL 0x030A /* PE0 L0 CDR control */
	220	#define PESDR0_L0DRV 0x030B /* PE0 L0 drive */
	221	#define PESDR0_L0REC 0x030C /* PE0 L0 receiver */
	222	#define PESDR0_L0LPB 0x030D /* PE0 L0 loopback */
	223	#define PESDR0_L0CLK 0x030E /* PE0 L0 clocking */
	224	#define PESDR0_PHY_CTL_RST 0x030F /* PE0 PHY control reset */
	225	#define PESDR0_RSTSTA 0x0310 /* PE0 reset status */
	226	#define PESDR0_OBS 0x0311 /* PE0 observation register */
	227	#define PESDR0_L0ERRC 0x0320 /* PE0 L0 error counter */
	228
	229	#define PESDR1_L0BIST 0x0348 /* PE1 L0 built in self test */
	230	#define PESDR1_L1BIST 0x0349 /* PE1 L1 built in self test */
	231	#define PESDR1_L2BIST 0x034A /* PE1 L2 built in self test */
	232	#define PESDR1_L3BIST 0x034B /* PE1 L3 built in self test */
	233	#define PESDR1_L0BISTSTS 0x034C /* PE1 L0 built in self test status */
	234	#define PESDR1_L1BISTSTS 0x034D /* PE1 L1 built in self test status */
	235	#define PESDR1_L2BISTSTS 0x034E /* PE1 L2 built in self test status */
	236	#define PESDR1_L3BISTSTS 0x034F /* PE1 L3 built in self test status */
	237	#define PESDR1_L0CDRCTL 0x0350 /* PE1 L0 CDR control */
	238	#define PESDR1_L1CDRCTL 0x0351 /* PE1 L1 CDR control */
	239	#define PESDR1_L2CDRCTL 0x0352 /* PE1 L2 CDR control */
	240	#define PESDR1_L3CDRCTL 0x0353 /* PE1 L3 CDR control */
	241	#define PESDR1_L0DRV 0x0354 /* PE1 L0 drive */
	242	#define PESDR1_L1DRV 0x0355 /* PE1 L1 drive */
	243	#define PESDR1_L2DRV 0x0356 /* PE1 L2 drive */
	244	#define PESDR1_L3DRV 0x0357 /* PE1 L3 drive */
	245	#define PESDR1_L0REC 0x0358 /* PE1 L0 receiver */
	246	#define PESDR1_L1REC 0x0359 /* PE1 L1 receiver */
	247	#define PESDR1_L2REC 0x035A /* PE1 L2 receiver */
	248	#define PESDR1_L3REC 0x035B /* PE1 L3 receiver */
	249	#define PESDR1_L0LPB 0x035C /* PE1 L0 loopback */
	250	#define PESDR1_L1LPB 0x035D /* PE1 L1 loopback */
	251	#define PESDR1_L2LPB 0x035E /* PE1 L2 loopback */
	252	#define PESDR1_L3LPB 0x035F /* PE1 L3 loopback */
	253	#define PESDR1_L0CLK 0x0360 /* PE1 L0 clocking */
	254	#define PESDR1_L1CLK 0x0361 /* PE1 L1 clocking */
	255	#define PESDR1_L2CLK 0x0362 /* PE1 L2 clocking */
	256	#define PESDR1_L3CLK 0x0363 /* PE1 L3 clocking */
	257	#define PESDR1_PHY_CTL_RST 0x0364 /* PE1 PHY control reset */
	258	#define PESDR1_RSTSTA 0x0365 /* PE1 reset status */
	259	#define PESDR1_OBS 0x0366 /* PE1 observation register */
	260	#define PESDR1_L0ERRC 0x0368 /* PE1 L0 error counter */
	261	#define PESDR1_L1ERRC 0x0369 /* PE1 L1 error counter */
	262	#define PESDR1_L2ERRC 0x036A /* PE1 L2 error counter */
	263	#define PESDR1_L3ERRC 0x036B /* PE1 L3 error counter */
	264	#define PESDR0_IHS1 0x036C /* PE interrupt handler interfact setting 1 */
	265	#define PESDR0_IHS2 0x036D /* PE interrupt handler interfact setting 2 */
	266
03d344bb SR	267	#endif
03d344bb SR	268
999ecd5a SR	269	/* SDR Bit Mappings */
	270	#define PESDRx_RCSSET_HLDPLB 0x10000000
	271	#define PESDRx_RCSSET_RSTGU 0x01000000
	272	#define PESDRx_RCSSET_RDY 0x00100000
	273	#define PESDRx_RCSSET_RSTDL 0x00010000
	274	#define PESDRx_RCSSET_RSTPYN 0x00001000
	275
	276	#define PESDRx_RCSSTS_PLBIDL 0x10000000
	277	#define PESDRx_RCSSTS_HRSTRQ 0x01000000
	278	#define PESDRx_RCSSTS_PGRST 0x00100000
	279	#define PESDRx_RCSSTS_VC0ACT 0x00010000
	280	#define PESDRx_RCSSTS_BMEN 0x00000100
	281
692519b1 RJ	282	/*
	283	* UTL register offsets
	284	*/
f31d38b9	285	#define PEUTL_PBCTL 0x00
692519b1 RJ	286	#define PEUTL_PBBSZ 0x20
	287	#define PEUTL_OPDBSZ 0x68
	288	#define PEUTL_IPHBSZ 0x70
	289	#define PEUTL_IPDBSZ 0x78
	290	#define PEUTL_OUTTR 0x90
	291	#define PEUTL_INTR 0x98
	292	#define PEUTL_PCTL 0xa0
f31d38b9	293	#define PEUTL_RCSTA 0xb0
692519b1 RJ	294	#define PEUTL_RCIRQEN 0xb8
	295
	296	/*
	297	* Config space register offsets
	298	*/
	299	#define PECFG_BAR0LMPA 0x210
	300	#define PECFG_BAR0HMPA 0x214
2b393b0f	301	#define PECFG_BAR1MPA 0x218
5cb4af47 SR	302	#define PECFG_BAR2LMPA 0x220
5cb4af47 SR	303	#define PECFG_BAR2HMPA 0x224
2b393b0f	304
692519b1 RJ	305	#define PECFG_PIMEN 0x33c
	306	#define PECFG_PIM0LAL 0x340
	307	#define PECFG_PIM0LAH 0x344
c9240981 GB	308	#define PECFG_PIM1LAL 0x348
c9240981 GB	309	#define PECFG_PIM1LAH 0x34c
2b393b0f SR	310	#define PECFG_PIM01SAL 0x350
	311	#define PECFG_PIM01SAH 0x354
	312
692519b1 RJ	313	#define PECFG_POM0LAL 0x380
	314	#define PECFG_POM0LAH 0x384
	315
	316	#define SDR_READ(offset) ({\
	317	mtdcr(DCRN_SDR0_CFGADDR, offset); \
	318	mfdcr(DCRN_SDR0_CFGDATA);})
	319
	320	#define SDR_WRITE(offset, data) ({\
	321	mtdcr(DCRN_SDR0_CFGADDR, offset); \
	322	mtdcr(DCRN_SDR0_CFGDATA,data);})
	323
15ee4734	324	#define GPL_DMER_MASK_DISA 0x02000000
c9240981	325
97923770 SR	326	#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
	327	#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
	328
d4cb2d17 SR	329	/*
	330	* Prototypes
	331	*/
026f7110 SR	332	int ppc4xx_init_pcie(void);
026f7110 SR	333	int ppc4xx_init_pcie_rootport(int port);
03d344bb	334	int ppc4xx_init_pcie_endport(int port);
026f7110 SR	335	void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port);
026f7110 SR	336	int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port);
692519b1	337	int pcie_hose_scan(struct pci_controller *hose, int bus);
026f7110	338
d4cb2d17 SR	339	/*
	340	* Function to determine root port or endport from env variable.
	341	*/
	342	static inline int is_end_point(int port)
	343	{
5cb4af47 SR	344	char s[10], *tk;
5cb4af47 SR	345	char *pcie_mode = getenv("pcie_mode");
d4cb2d17	346
5cb4af47 SR	347	if (pcie_mode == NULL)
	348	return 0;
	349
	350	strcpy(s, pcie_mode);
d4cb2d17 SR	351	tk = strtok(s, ":");
	352
	353	switch (port) {
	354	case 0:
	355	if (tk != NULL) {
	356	if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
	357	return 1;
	358	else
	359	return 0;
	360	}
	361	else
	362	return 0;
	363
	364	case 1:
	365	tk = strtok(NULL, ":");
	366	if (tk != NULL) {
	367	if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
	368	return 1;
	369	else
	370	return 0;
	371	}
	372	else
	373	return 0;
	374
	375	case 2:
	376	tk = strtok(NULL, ":");
	377	if (tk != NULL)
	378	tk = strtok(NULL, ":");
	379	if (tk != NULL) {
	380	if (!(strcmp(tk, "ep") && strcmp(tk, "EP")))
	381	return 1;
	382	else
	383	return 0;
	384	}
	385	else
	386	return 0;
	387	}
	388
	389	return 0;
	390	}
	391
03d344bb SR	392	static inline void mdelay(int n)
	393	{
	394	u32 ms = n;
	395
	396	while (ms--)
	397	udelay(1000);
	398	}
	399
24bfedbd	400	#if defined(PCIE0_SDR)
03d344bb SR	401	static inline u32 sdr_base(int port)
	402	{
	403	switch (port) {
	404	default: /* to satisfy compiler */
	405	case 0:
	406	return PCIE0_SDR;
	407	case 1:
	408	return PCIE1_SDR;
6d0f6bcf	409	#if CONFIG_SYS_PCIE_NR_PORTS > 2
03d344bb SR	410	case 2:
	411	return PCIE2_SDR;
	412	#endif
	413	}
	414	}
24bfedbd	415	#endif /* defined(PCIE0_SDR) */
03d344bb	416
026f7110	417	#endif /* __4XX_PCIE_H */