[people/ms/u-boot.git] / arch / powerpc / include / asm / 5xx_immap.h

/*
 * (C) Copyright 2003
 * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * File:		5xx_immap.h
 *
 * Discription:		MPC555 Internal Memory Map
 *
 */

#ifndef __IMMAP_5XX__
#define __IMMAP_5XX__

/* System Configuration Registers.
*/
typedef	struct sys_conf {
	uint sc_siumcr;
	uint sc_sypcr;
	char res1[6];
	ushort sc_swsr;
	uint sc_sipend;
	uint sc_simask;
	uint sc_siel;
	uint sc_sivec;
	uint sc_tesr;
	uint sc_sgpiodt1;
	uint sc_sgpiodt2;
	uint sc_sgpiocr;
	uint sc_emcr;
	uint sc_res1aa;
	uint sc_res1ab;
	uint sc_pdmcr;
	char res3[192];
} sysconf5xx_t;


/* Memory Controller Registers.
*/
typedef struct	mem_ctlr {
	uint memc_br0;
	uint memc_or0;
	uint memc_br1;
	uint memc_or1;
	uint memc_br2;
	uint memc_or2;
	uint memc_br3;
	uint memc_or3;
	char res1[32];
	uint memc_dmbr;
	uint memc_dmor;
	char res2[48];
	ushort memc_mstat;
	ushort memc_res4a;
	char res3[132];
} memctl5xx_t;

/* System Integration Timers.
*/
typedef struct	sys_int_timers {
	ushort sit_tbscr;
	char res1[2];
	uint sit_tbref0;
	uint sit_tbref1;
	char res2[20];
	ushort sit_rtcsc;
	char res3[2];
	uint sit_rtc;
	uint sit_rtsec;
	uint sit_rtcal;
	char res4[16];
	ushort sit_piscr;
	char res5[2];
	uint sit_pitc;
	uint sit_pitr;
	char res6[52];
} sit5xx_t;

/* Clocks and Reset
*/
typedef struct clk_and_reset {
	uint car_sccr;
	uint car_plprcr;
	ushort car_rsr;
	ushort car_res7a;
	ushort car_colir;
	ushort car_res7b;
	ushort car_vsrmcr;
	ushort car_res7c;
	char res1[108];

} car5xx_t;

#define TBSCR_TBE		((ushort)0x0001)

/* System Integration Timer Keys
*/
typedef struct sitk {
	uint sitk_tbscrk;
	uint sitk_tbref0k;
	uint sitk_tbref1k;
	uint sitk_tbk;
	char res1[16];
	uint sitk_rtcsck;
	uint sitk_rtck;
	uint sitk_rtseck;
	uint sitk_rtcalk;
	char res2[16];
	uint sitk_piscrk;
	uint sitk_pitck;
	char res3[56];
} sitk5xx_t;

/* Clocks and Reset Keys.
*/
typedef struct cark {
	uint	cark_sccrk;
	uint	cark_plprcrk;
	uint	cark_rsrk;
	char	res1[1140];
} cark8xx_t;

/* The key to unlock registers maintained by keep-alive power.
*/
#define KAPWR_KEY	((unsigned int)0x55ccaa33)

/* Flash Configuration
*/
typedef struct fl {
	uint fl_cmfmcr;
	uint fl_cmftst;
	uint fl_cmfctl;
	char res1[52];
} fl5xx_t;

/* Dpram Control
*/
typedef struct dprc {
	ushort dprc_dptmcr;
	ushort dprc_ramtst;
	ushort dprc_rambar;
	ushort dprc_misrh;
	ushort dprc_misrl;
	ushort dprc_miscnt;
} dprc5xx_t;

/* Time Processor Unit
*/
typedef struct tpu {
	ushort tpu_tpumcr;
	ushort tpu_tcr;
	ushort tpu_dscr;
	ushort tpu_dssr;
	ushort tpu_ticr;
	ushort tpu_cier;
	ushort tpu_cfsr0;
	ushort tpu_cfsr1;
	ushort tpu_cfsr2;
	ushort tpu_cfsr3;
	ushort tpu_hsqr0;
	ushort tpu_hsqr1;
	ushort tpu_hsrr0;
	ushort tpu_hsrr1;
	ushort tpu_cpr0;
	ushort tpu_cpr1;
	ushort tpu_cisr;
	ushort tpu_lr;
	ushort tpu_sglr;
	ushort tpu_dcnr;
	ushort tpu_tpumcr2;
	ushort tpu_tpumcr3;
	ushort tpu_isdr;
	ushort tpu_iscr;
	char   res1[208];
	char   tpu[16][16];
	char   res2[512];
} tpu5xx_t;

/* QADC
*/
typedef struct qadc {
	ushort qadc_64mcr;
	ushort qadc_64test;
	ushort qadc_64int;
	u_char  qadc_portqa;
	u_char  qadc_portqb;
	ushort qadc_ddrqa;
	ushort qadc_qacr0;
	ushort qadc_qacr1;
	ushort qadc_qacr2;
	ushort qadc_qasr0;
	ushort qadc_qasr1;
	char   res1[492];
       /* command convertion word table */
	ushort qadc_ccw[64];
       /* result word table, unsigned right justified */
	ushort qadc_rjurr[64];
       /* result word table, signed left justified */
	ushort qadc_ljsrr[64];
       /* result word table, unsigned left justified */
	ushort qadc_ljurr[64];
} qadc5xx_t;

/* QSMCM
*/
typedef struct qsmcm {
	ushort qsmcm_qsmcr;
	ushort qsmcm_qtest;
	ushort qsmcm_qdsci_il;
	ushort qsmcm_qspi_il;
	ushort qsmcm_scc1r0;
	ushort qsmcm_scc1r1;
	ushort qsmcm_sc1sr;
	ushort qsmcm_sc1dr;
	char   res1[2];
	char   res2[2];
	ushort qsmcm_portqs;
	u_char qsmcm_pqspar;
	u_char qsmcm_ddrqs;
	ushort qsmcm_spcr0;
	ushort qsmcm_spcr1;
	ushort qsmcm_spcr2;
	u_char qsmcm_spcr3;
	u_char qsmcm_spsr;
	ushort qsmcm_scc2r0;
	ushort qsmcm_scc2r1;
	ushort qsmcm_sc2sr;
	ushort qsmcm_sc2dr;
	ushort qsmcm_qsci1cr;
	ushort qsmcm_qsci1sr;
	ushort qsmcm_sctq[16];
	ushort qsmcm_scrq[16];
	char   res3[212];
	ushort qsmcm_recram[32];
	ushort qsmcm_tranram[32];
	u_char qsmcm_comdram[32];
	char   res[3616];
} qsmcm5xx_t;


/* MIOS
*/

typedef struct mios {
	ushort mios_mpwmsm0perr;                 /* mpwmsm0 */
	ushort mios_mpwmsm0pulr;
	ushort mios_mpwmsm0cntr;
	ushort mios_mpwmsm0scr;
	ushort mios_mpwmsm1perr;                 /* mpwmsm1 */
	ushort mios_mpwmsm1pulr;
	ushort mios_mpwmsm1cntr;
	ushort mios_mpwmsm1scr;
	ushort mios_mpwmsm2perr;                 /* mpwmsm2 */
	ushort mios_mpwmsm2pulr;
	ushort mios_mpwmsm2cntr;
	ushort mios_mpwmsm2scr;
	ushort mios_mpwmsm3perr;                 /* mpwmsm3 */
	ushort mios_mpwmsm3pulr;
	ushort mios_mpwmsm3cntr;
	ushort mios_mpwmsm3scr;
	char res1[16];
	ushort mios_mmcsm6cnt;                   /* mmcsm6 */
	ushort mios_mmcsm6mlr;
	ushort mios_mmcsm6scrd, mmcsm6scr;
	char res2[32];
	ushort mios_mdasm11ar;                   /* mdasm11 */
	ushort mios_mdasm11br;
	ushort mios_mdasm11scrd, mdasm11scr;
	ushort mios_mdasm12ar;                   /* mdasm12 */
	ushort mios_mdasm12br;
	ushort mios_mdasm12scrd, mdasm12scr;
	ushort mios_mdasm13ar;                   /* mdasm13 */
	ushort mios_mdasm13br;
	ushort mios_mdasm13scrd, mdasm13scr;
	ushort mios_mdasm14ar;                   /* mdasm14 */
	ushort mios_mdasm14br;
	ushort mios_mdasm14scrd, mdasm14scr;
	ushort mios_mdasm15ar;                   /* mdasm15 */
	ushort mios_mdasm15br;
	ushort mios_mdasm15scrd, mdasm15scr;
	ushort mios_mpwmsm16perr;                /* mpwmsm16 */
	ushort mios_mpwmsm16pulr;
	ushort mios_mpwmsm16cntr;
	ushort mios_mpwmsm16scr;
	ushort mios_mpwmsm17perr;                /* mpwmsm17 */
	ushort mios_mpwmsm17pulr;
	ushort mios_mpwmsm17cntr;
	ushort mios_mpwmsm17scr;
	ushort mios_mpwmsm18perr;                /* mpwmsm18 */
	ushort mios_mpwmsm18pulr;
	ushort mios_mpwmsm18cntr;
	ushort mios_mpwmsm18scr;
	ushort mios_mpwmsm19perr;                /* mpwmsm19 */
	ushort mios_mpwmsm19pulr;
	ushort mios_mpwmsm19cntr;
	ushort mios_mpwmsm19scr;
	char res3[16];
	ushort mios_mmcsm22cnt;                  /* mmcsm22 */
	ushort mios_mmcsm22mlr;
	ushort mios_mmcsm22scrd, mmcsm22scr;
	char res4[32];
	ushort mios_mdasm27ar;                   /* mdasm27 */
	ushort mios_mdasm27br;
	ushort mios_mdasm27scrd, mdasm27scr;
	ushort mios_mdasm28ar;                   /*mdasm28 */
	ushort mios_mdasm28br;
	ushort mios_mdasm28scrd, mdasm28scr;
	ushort mios_mdasm29ar;                   /* mdasm29 */
	ushort mios_mdasm29br;
	ushort mios_mdasm29scrd, mdasm29scr;
	ushort mios_mdasm30ar;                   /* mdasm30 */
	ushort mios_mdasm30br;
	ushort mios_mdasm30scrd, mdasm30scr;
	ushort mios_mdasm31ar;                   /* mdasm31 */
	ushort mios_mdasm31br;
	ushort mios_mdasm31scrd, mdasm31scr;
	ushort mios_mpiosm32dr;
	ushort mios_mpiosm32ddr;
	char res5[1788];
	ushort mios_mios1tpcr;
	char mios_res13[2];
	ushort mios_mios1vnr;
	ushort mios_mios1mcr;
	char res6[12];
	ushort mios_res42z;
	ushort mios_mcpsmscr;
	char res7[1000];
	ushort mios_mios1sr0;
	char res12[2];
	ushort mios_mios1er0;
	ushort mios_mios1rpr0;
	char res8[40];
	ushort mios_mios1lvl0;
	char res9[14];
	ushort mios_mios1sr1;
	char res10[2];
	ushort mios_mios1er1;
	ushort mios_mios1rpr1;
	char res11[40];
	ushort mios_mios1lvl1;
	char res13[1038];
} mios5xx_t;

/* Toucan Module
*/
typedef struct tcan {
	ushort tcan_tcnmcr;
	ushort tcan_cantcr;
	ushort tcan_canicr;
	u_char tcan_canctrl0;
	u_char tcan_canctrl1;
	u_char tcan_presdiv;
	u_char tcan_canctrl2;
	ushort tcan_timer;
	char res1[4];
	ushort tcan_rxgmskhi;
	ushort tcan_rxgmsklo;
	ushort tcan_rx14mskhi;
	ushort tcan_rx14msklo;
	ushort tcan_rx15mskhi;
	ushort tcan_rx15msklo;
	char res2[4];
	ushort tcan_estat;
	ushort tcan_imask;
	ushort tcan_iflag;
	u_char tcan_rxectr;
	u_char tcan_txectr;
	char res3[88];
	struct {
	       ushort scr;
	       ushort id_high;
	       ushort id_low;
	       u_char data[8];
		   char res4[2];
	    } tcan_mbuff[16];
	    char res5[640];
} tcan5xx_t;

/* UIMB
*/
typedef struct uimb {
	uint uimb_umcr;
	char res1[12];
	uint uimb_utstcreg;
	char res2[12];
	uint uimb_uipend;
} uimb5xx_t;


/* Internal Memory Map MPC555
*/
typedef struct immap {
	char               res1[262144];	/* CMF Flash A 256 Kbytes */
	char               res2[196608];	/* CMF Flash B 192 Kbytes */
	char               res3[2670592];	/* Reserved for Flash */
	sysconf5xx_t       im_siu_conf;		/* SIU Configuration */
	memctl5xx_t	   im_memctl;		/* Memory Controller */
	sit5xx_t           im_sit;		/* System Integration Timers */
	car5xx_t	   im_clkrst;		/* Clocks and Reset */
	sitk5xx_t          im_sitk;		/* System Integration Timer Keys*/
	cark8xx_t          im_clkrstk;		/* Clocks and Resert Keys */
	fl5xx_t	           im_fla;	        /* Flash Module A */
	fl5xx_t	           im_flb;	        /* Flash Module B */
	char               res4[14208];		/* Reserved for SIU */
	dprc5xx_t	   im_dprc;		/* Dpram Control Register */
	char               res5[8180];		/* Reserved */
	char               dptram[6144];	/* Dptram */
	char               res6[2048];		/* Reserved */
	tpu5xx_t	   im_tpua;		/* Time Proessing Unit A */
	tpu5xx_t	   im_tpub;		/* Time Processing Unit B */
	qadc5xx_t	   im_qadca;		/* QADC A */
	qadc5xx_t	   im_qadcb;		/* QADC B */
	qsmcm5xx_t	   im_qsmcm;		/* SCI and SPI */
	mios5xx_t	   im_mios;		/* MIOS */
	tcan5xx_t          im_tcana;		/* Toucan A */
	tcan5xx_t          im_tcanb;		/* Toucan B */
	char               res7[1792];		/* Reserved */
	uimb5xx_t          im_uimb;	        /* UIMB */
} immap_t;

#endif /* __IMMAP_5XX__ */
Commit	Line	Data
0db5bca8 WD	1	/*
	2	* (C) Copyright 2003
	3	* Martin Winistoerfer, martinwinistoerfer@gmx.ch.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
0db5bca8 WD	6	*/
	7
	8	/*
	9	* File: 5xx_immap.h
8bde7f77	10	*
0db5bca8	11	* Discription: MPC555 Internal Memory Map
8bde7f77	12	*
0db5bca8	13	*/
8bde7f77	14
0db5bca8 WD	15	#ifndef __IMMAP_5XX__
	16	#define __IMMAP_5XX__
	17
	18	/* System Configuration Registers.
	19	*/
	20	typedef struct sys_conf {
8bde7f77 WD	21	uint sc_siumcr;
	22	uint sc_sypcr;
	23	char res1[6];
	24	ushort sc_swsr;
	25	uint sc_sipend;
	26	uint sc_simask;
	27	uint sc_siel;
	28	uint sc_sivec;
	29	uint sc_tesr;
	30	uint sc_sgpiodt1;
	31	uint sc_sgpiodt2;
	32	uint sc_sgpiocr;
	33	uint sc_emcr;
	34	uint sc_res1aa;
	35	uint sc_res1ab;
	36	uint sc_pdmcr;
	37	char res3[192];
0db5bca8 WD	38	} sysconf5xx_t;
	39
	40
	41	/* Memory Controller Registers.
	42	*/
	43	typedef struct mem_ctlr {
8bde7f77 WD	44	uint memc_br0;
	45	uint memc_or0;
	46	uint memc_br1;
	47	uint memc_or1;
	48	uint memc_br2;
	49	uint memc_or2;
	50	uint memc_br3;
	51	uint memc_or3;
	52	char res1[32];
	53	uint memc_dmbr;
	54	uint memc_dmor;
	55	char res2[48];
	56	ushort memc_mstat;
	57	ushort memc_res4a;
	58	char res3[132];
0db5bca8 WD	59	} memctl5xx_t;
	60
	61	/* System Integration Timers.
	62	*/
	63	typedef struct sys_int_timers {
8bde7f77 WD	64	ushort sit_tbscr;
	65	char res1[2];
	66	uint sit_tbref0;
	67	uint sit_tbref1;
	68	char res2[20];
	69	ushort sit_rtcsc;
	70	char res3[2];
	71	uint sit_rtc;
	72	uint sit_rtsec;
	73	uint sit_rtcal;
	74	char res4[16];
	75	ushort sit_piscr;
	76	char res5[2];
	77	uint sit_pitc;
	78	uint sit_pitr;
	79	char res6[52];
0db5bca8 WD	80	} sit5xx_t;
	81
	82	/* Clocks and Reset
	83	*/
	84	typedef struct clk_and_reset {
8bde7f77 WD	85	uint car_sccr;
	86	uint car_plprcr;
	87	ushort car_rsr;
	88	ushort car_res7a;
	89	ushort car_colir;
	90	ushort car_res7b;
	91	ushort car_vsrmcr;
	92	ushort car_res7c;
	93	char res1[108];
0db5bca8 WD	94
	95	} car5xx_t;
	96
	97	#define TBSCR_TBE ((ushort)0x0001)
	98
	99	/* System Integration Timer Keys
	100	*/
	101	typedef struct sitk {
8bde7f77 WD	102	uint sitk_tbscrk;
	103	uint sitk_tbref0k;
	104	uint sitk_tbref1k;
	105	uint sitk_tbk;
	106	char res1[16];
	107	uint sitk_rtcsck;
	108	uint sitk_rtck;
	109	uint sitk_rtseck;
	110	uint sitk_rtcalk;
	111	char res2[16];
	112	uint sitk_piscrk;
	113	uint sitk_pitck;
	114	char res3[56];
0db5bca8 WD	115	} sitk5xx_t;
	116
	117	/* Clocks and Reset Keys.
	118	*/
	119	typedef struct cark {
	120	uint cark_sccrk;
	121	uint cark_plprcrk;
	122	uint cark_rsrk;
	123	char res1[1140];
	124	} cark8xx_t;
	125
	126	/* The key to unlock registers maintained by keep-alive power.
	127	*/
	128	#define KAPWR_KEY ((unsigned int)0x55ccaa33)
	129
	130	/* Flash Configuration
	131	*/
	132	typedef struct fl {
8bde7f77 WD	133	uint fl_cmfmcr;
	134	uint fl_cmftst;
	135	uint fl_cmfctl;
	136	char res1[52];
0db5bca8 WD	137	} fl5xx_t;
	138
	139	/* Dpram Control
	140	*/
8bde7f77 WD	141	typedef struct dprc {
	142	ushort dprc_dptmcr;
	143	ushort dprc_ramtst;
	144	ushort dprc_rambar;
	145	ushort dprc_misrh;
	146	ushort dprc_misrl;
	147	ushort dprc_miscnt;
0db5bca8 WD	148	} dprc5xx_t;
	149
	150	/* Time Processor Unit
	151	*/
	152	typedef struct tpu {
8bde7f77 WD	153	ushort tpu_tpumcr;
	154	ushort tpu_tcr;
	155	ushort tpu_dscr;
	156	ushort tpu_dssr;
	157	ushort tpu_ticr;
	158	ushort tpu_cier;
	159	ushort tpu_cfsr0;
	160	ushort tpu_cfsr1;
	161	ushort tpu_cfsr2;
	162	ushort tpu_cfsr3;
	163	ushort tpu_hsqr0;
	164	ushort tpu_hsqr1;
	165	ushort tpu_hsrr0;
	166	ushort tpu_hsrr1;
	167	ushort tpu_cpr0;
	168	ushort tpu_cpr1;
	169	ushort tpu_cisr;
	170	ushort tpu_lr;
	171	ushort tpu_sglr;
	172	ushort tpu_dcnr;
	173	ushort tpu_tpumcr2;
	174	ushort tpu_tpumcr3;
	175	ushort tpu_isdr;
	176	ushort tpu_iscr;
	177	char res1[208];
	178	char tpu[16][16];
	179	char res2[512];
0db5bca8 WD	180	} tpu5xx_t;
	181
	182	/* QADC
	183	*/
	184	typedef struct qadc {
8bde7f77 WD	185	ushort qadc_64mcr;
	186	ushort qadc_64test;
	187	ushort qadc_64int;
	188	u_char qadc_portqa;
	189	u_char qadc_portqb;
	190	ushort qadc_ddrqa;
	191	ushort qadc_qacr0;
	192	ushort qadc_qacr1;
	193	ushort qadc_qacr2;
	194	ushort qadc_qasr0;
	195	ushort qadc_qasr1;
	196	char res1[492];
0db5bca8	197	/* command convertion word table */
8bde7f77	198	ushort qadc_ccw[64];
0db5bca8	199	/* result word table, unsigned right justified */
8bde7f77	200	ushort qadc_rjurr[64];
0db5bca8	201	/* result word table, signed left justified */
8bde7f77	202	ushort qadc_ljsrr[64];
0db5bca8	203	/* result word table, unsigned left justified */
8bde7f77	204	ushort qadc_ljurr[64];
0db5bca8 WD	205	} qadc5xx_t;
	206
	207	/* QSMCM
	208	*/
	209	typedef struct qsmcm {
8bde7f77 WD	210	ushort qsmcm_qsmcr;
	211	ushort qsmcm_qtest;
	212	ushort qsmcm_qdsci_il;
	213	ushort qsmcm_qspi_il;
	214	ushort qsmcm_scc1r0;
	215	ushort qsmcm_scc1r1;
	216	ushort qsmcm_sc1sr;
	217	ushort qsmcm_sc1dr;
	218	char res1[2];
	219	char res2[2];
	220	ushort qsmcm_portqs;
	221	u_char qsmcm_pqspar;
	222	u_char qsmcm_ddrqs;
	223	ushort qsmcm_spcr0;
	224	ushort qsmcm_spcr1;
	225	ushort qsmcm_spcr2;
	226	u_char qsmcm_spcr3;
	227	u_char qsmcm_spsr;
	228	ushort qsmcm_scc2r0;
	229	ushort qsmcm_scc2r1;
	230	ushort qsmcm_sc2sr;
	231	ushort qsmcm_sc2dr;
	232	ushort qsmcm_qsci1cr;
	233	ushort qsmcm_qsci1sr;
	234	ushort qsmcm_sctq[16];
	235	ushort qsmcm_scrq[16];
	236	char res3[212];
	237	ushort qsmcm_recram[32];
	238	ushort qsmcm_tranram[32];
	239	u_char qsmcm_comdram[32];
	240	char res[3616];
0db5bca8 WD	241	} qsmcm5xx_t;
	242
	243
	244	/* MIOS
	245	*/
	246
	247	typedef struct mios {
8bde7f77 WD	248	ushort mios_mpwmsm0perr; /* mpwmsm0 */
	249	ushort mios_mpwmsm0pulr;
	250	ushort mios_mpwmsm0cntr;
	251	ushort mios_mpwmsm0scr;
	252	ushort mios_mpwmsm1perr; /* mpwmsm1 */
	253	ushort mios_mpwmsm1pulr;
	254	ushort mios_mpwmsm1cntr;
	255	ushort mios_mpwmsm1scr;
	256	ushort mios_mpwmsm2perr; /* mpwmsm2 */
	257	ushort mios_mpwmsm2pulr;
	258	ushort mios_mpwmsm2cntr;
	259	ushort mios_mpwmsm2scr;
	260	ushort mios_mpwmsm3perr; /* mpwmsm3 */
	261	ushort mios_mpwmsm3pulr;
	262	ushort mios_mpwmsm3cntr;
	263	ushort mios_mpwmsm3scr;
	264	char res1[16];
	265	ushort mios_mmcsm6cnt; /* mmcsm6 */
	266	ushort mios_mmcsm6mlr;
	267	ushort mios_mmcsm6scrd, mmcsm6scr;
	268	char res2[32];
	269	ushort mios_mdasm11ar; /* mdasm11 */
	270	ushort mios_mdasm11br;
	271	ushort mios_mdasm11scrd, mdasm11scr;
	272	ushort mios_mdasm12ar; /* mdasm12 */
	273	ushort mios_mdasm12br;
	274	ushort mios_mdasm12scrd, mdasm12scr;
	275	ushort mios_mdasm13ar; /* mdasm13 */
	276	ushort mios_mdasm13br;
	277	ushort mios_mdasm13scrd, mdasm13scr;
	278	ushort mios_mdasm14ar; /* mdasm14 */
	279	ushort mios_mdasm14br;
	280	ushort mios_mdasm14scrd, mdasm14scr;
	281	ushort mios_mdasm15ar; /* mdasm15 */
	282	ushort mios_mdasm15br;
	283	ushort mios_mdasm15scrd, mdasm15scr;
	284	ushort mios_mpwmsm16perr; /* mpwmsm16 */
	285	ushort mios_mpwmsm16pulr;
	286	ushort mios_mpwmsm16cntr;
	287	ushort mios_mpwmsm16scr;
	288	ushort mios_mpwmsm17perr; /* mpwmsm17 */
	289	ushort mios_mpwmsm17pulr;
	290	ushort mios_mpwmsm17cntr;
	291	ushort mios_mpwmsm17scr;
	292	ushort mios_mpwmsm18perr; /* mpwmsm18 */
	293	ushort mios_mpwmsm18pulr;
	294	ushort mios_mpwmsm18cntr;
	295	ushort mios_mpwmsm18scr;
	296	ushort mios_mpwmsm19perr; /* mpwmsm19 */
	297	ushort mios_mpwmsm19pulr;
	298	ushort mios_mpwmsm19cntr;
	299	ushort mios_mpwmsm19scr;
	300	char res3[16];
	301	ushort mios_mmcsm22cnt; /* mmcsm22 */
	302	ushort mios_mmcsm22mlr;
	303	ushort mios_mmcsm22scrd, mmcsm22scr;
	304	char res4[32];
	305	ushort mios_mdasm27ar; /* mdasm27 */
	306	ushort mios_mdasm27br;
	307	ushort mios_mdasm27scrd, mdasm27scr;
	308	ushort mios_mdasm28ar; /mdasm28 /
	309	ushort mios_mdasm28br;
	310	ushort mios_mdasm28scrd, mdasm28scr;
	311	ushort mios_mdasm29ar; /* mdasm29 */
312	ushort mios_mdasm29br;
313	ushort mios_mdasm29scrd, mdasm29scr;
314	ushort mios_mdasm30ar; /* mdasm30 */
315	ushort mios_mdasm30br;
316	ushort mios_mdasm30scrd, mdasm30scr;
317	ushort mios_mdasm31ar; /* mdasm31 */
318	ushort mios_mdasm31br;
319	ushort mios_mdasm31scrd, mdasm31scr;
320	ushort mios_mpiosm32dr;
321	ushort mios_mpiosm32ddr;
322	char res5[1788];
323	ushort mios_mios1tpcr;
324	char mios_res13[2];
325	ushort mios_mios1vnr;
326	ushort mios_mios1mcr;
327	char res6[12];
328	ushort mios_res42z;
329	ushort mios_mcpsmscr;
330	char res7[1000];
331	ushort mios_mios1sr0;
332	char res12[2];
333	ushort mios_mios1er0;
334	ushort mios_mios1rpr0;
335	char res8[40];
336	ushort mios_mios1lvl0;
337	char res9[14];
338	ushort mios_mios1sr1;
339	char res10[2];
340	ushort mios_mios1er1;
341	ushort mios_mios1rpr1;
342	char res11[40];
343	ushort mios_mios1lvl1;
344	char res13[1038];
0db5bca8 WD	345	} mios5xx_t;
	346
	347	/* Toucan Module
	348	*/
	349	typedef struct tcan {
8bde7f77 WD	350	ushort tcan_tcnmcr;
	351	ushort tcan_cantcr;
	352	ushort tcan_canicr;
	353	u_char tcan_canctrl0;
	354	u_char tcan_canctrl1;
	355	u_char tcan_presdiv;
	356	u_char tcan_canctrl2;
	357	ushort tcan_timer;
	358	char res1[4];
	359	ushort tcan_rxgmskhi;
	360	ushort tcan_rxgmsklo;
	361	ushort tcan_rx14mskhi;
	362	ushort tcan_rx14msklo;
	363	ushort tcan_rx15mskhi;
	364	ushort tcan_rx15msklo;
	365	char res2[4];
	366	ushort tcan_estat;
	367	ushort tcan_imask;
	368	ushort tcan_iflag;
	369	u_char tcan_rxectr;
	370	u_char tcan_txectr;
	371	char res3[88];
	372	struct {
	373	ushort scr;
	374	ushort id_high;
	375	ushort id_low;
	376	u_char data[8];
	377	char res4[2];
0db5bca8 WD	378	} tcan_mbuff[16];
	379	char res5[640];
	380	} tcan5xx_t;
	381
	382	/* UIMB
	383	*/
	384	typedef struct uimb {
8bde7f77 WD	385	uint uimb_umcr;
	386	char res1[12];
	387	uint uimb_utstcreg;
	388	char res2[12];
	389	uint uimb_uipend;
0db5bca8 WD	390	} uimb5xx_t;
	391
	392
0db5bca8 WD	393	/* Internal Memory Map MPC555
	394	*/
	395	typedef struct immap {
53677ef1 WD	396	char res1[262144]; /* CMF Flash A 256 Kbytes */
	397	char res2[196608]; /* CMF Flash B 192 Kbytes */
	398	char res3[2670592]; /* Reserved for Flash */
	399	sysconf5xx_t im_siu_conf; /* SIU Configuration */
8bde7f77 WD	400	memctl5xx_t im_memctl; /* Memory Controller */
	401	sit5xx_t im_sit; /* System Integration Timers */
	402	car5xx_t im_clkrst; /* Clocks and Reset */
53677ef1 WD	403	sitk5xx_t im_sitk; /* System Integration Timer Keys*/
53677ef1 WD	404	cark8xx_t im_clkrstk; /* Clocks and Resert Keys */
8bde7f77 WD	405	fl5xx_t im_fla; /* Flash Module A */
8bde7f77 WD	406	fl5xx_t im_flb; /* Flash Module B */
53677ef1 WD	407	char res4[14208]; /* Reserved for SIU */
	408	dprc5xx_t im_dprc; /* Dpram Control Register */
	409	char res5[8180]; /* Reserved */
	410	char dptram[6144]; /* Dptram */
	411	char res6[2048]; /* Reserved */
8bde7f77	412	tpu5xx_t im_tpua; /* Time Proessing Unit A */
53677ef1 WD	413	tpu5xx_t im_tpub; /* Time Processing Unit B */
	414	qadc5xx_t im_qadca; /* QADC A */
	415	qadc5xx_t im_qadcb; /* QADC B */
8bde7f77	416	qsmcm5xx_t im_qsmcm; /* SCI and SPI */
53677ef1 WD	417	mios5xx_t im_mios; /* MIOS */
	418	tcan5xx_t im_tcana; /* Toucan A */
	419	tcan5xx_t im_tcanb; /* Toucan B */
	420	char res7[1792]; /* Reserved */
8bde7f77	421	uimb5xx_t im_uimb; /* UIMB */
0db5bca8 WD	422	} immap_t;
	423
	424	#endif /* __IMMAP_5XX__ */