[people/ms/u-boot.git] / arch / powerpc / include / asm / 8xx_immap.h


/*
 * MPC8xx Internal Memory Map
 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
 *
 * The I/O on the MPC860 is comprised of blocks of special registers
 * and the dual port ram for the Communication Processor Module.
 * Within this space are functional units such as the SIU, memory
 * controller, system timers, and other control functions.  It is
 * a combination that I found difficult to separate into logical
 * functional files.....but anyone else is welcome to try.  -- Dan
 */
#ifndef __IMMAP_8XX__
#define __IMMAP_8XX__

/* System configuration registers.
*/
typedef	struct sys_conf {
	uint	sc_siumcr;
	uint	sc_sypcr;
	uint	sc_swt;
	char	res1[2];
	ushort	sc_swsr;
	uint	sc_sipend;
	uint	sc_simask;
	uint	sc_siel;
	uint	sc_sivec;
	uint	sc_tesr;
	char	res2[0xc];
	uint	sc_sdcr;
	char	res3[0x4c];
} sysconf8xx_t;

/* PCMCIA configuration registers.
*/
typedef struct pcmcia_conf {
	uint	pcmc_pbr0;
	uint	pcmc_por0;
	uint	pcmc_pbr1;
	uint	pcmc_por1;
	uint	pcmc_pbr2;
	uint	pcmc_por2;
	uint	pcmc_pbr3;
	uint	pcmc_por3;
	uint	pcmc_pbr4;
	uint	pcmc_por4;
	uint	pcmc_pbr5;
	uint	pcmc_por5;
	uint	pcmc_pbr6;
	uint	pcmc_por6;
	uint	pcmc_pbr7;
	uint	pcmc_por7;
	char	res1[0x20];
	uint	pcmc_pgcra;
	uint	pcmc_pgcrb;
	uint	pcmc_pscr;
	char	res2[4];
	uint	pcmc_pipr;
	char	res3[4];
	uint	pcmc_per;
	char	res4[4];
} pcmconf8xx_t;

/* Memory controller registers.
*/
typedef struct	mem_ctlr {
	uint	memc_br0;
	uint	memc_or0;
	uint	memc_br1;
	uint	memc_or1;
	uint	memc_br2;
	uint	memc_or2;
	uint	memc_br3;
	uint	memc_or3;
	uint	memc_br4;
	uint	memc_or4;
	uint	memc_br5;
	uint	memc_or5;
	uint	memc_br6;
	uint	memc_or6;
	uint	memc_br7;
	uint	memc_or7;
	char	res1[0x24];
	uint	memc_mar;
	uint	memc_mcr;
	char	res2[4];
	uint	memc_mamr;
	uint	memc_mbmr;
	ushort	memc_mstat;
	ushort	memc_mptpr;
	uint	memc_mdr;
	char	res3[0x80];
} memctl8xx_t;

/* System Integration Timers.
*/
typedef struct	sys_int_timers {
	ushort	sit_tbscr;
	char	res0[0x02];
	uint	sit_tbreff0;
	uint	sit_tbreff1;
	char	res1[0x14];
	ushort	sit_rtcsc;
	char	res2[0x02];
	uint	sit_rtc;
	uint	sit_rtsec;
	uint	sit_rtcal;
	char	res3[0x10];
	ushort	sit_piscr;
	char	res4[2];
	uint	sit_pitc;
	uint	sit_pitr;
	char	res5[0x34];
} sit8xx_t;

#define TBSCR_TBIRQ_MASK	((ushort)0xff00)
#define TBSCR_REFA		((ushort)0x0080)
#define TBSCR_REFB		((ushort)0x0040)
#define TBSCR_REFAE		((ushort)0x0008)
#define TBSCR_REFBE		((ushort)0x0004)
#define TBSCR_TBF		((ushort)0x0002)
#define TBSCR_TBE		((ushort)0x0001)

#define RTCSC_RTCIRQ_MASK	((ushort)0xff00)
#define RTCSC_SEC		((ushort)0x0080)
#define RTCSC_ALR		((ushort)0x0040)
#define RTCSC_38K		((ushort)0x0010)
#define RTCSC_SIE		((ushort)0x0008)
#define RTCSC_ALE		((ushort)0x0004)
#define RTCSC_RTF		((ushort)0x0002)
#define RTCSC_RTE		((ushort)0x0001)

#define PISCR_PIRQ_MASK		((ushort)0xff00)
#define PISCR_PS		((ushort)0x0080)
#define PISCR_PIE		((ushort)0x0004)
#define PISCR_PTF		((ushort)0x0002)
#define PISCR_PTE		((ushort)0x0001)

/* Clocks and Reset.
*/
typedef struct clk_and_reset {
	uint	car_sccr;
	uint	car_plprcr;
	uint	car_rsr;
	char	res[0x74];        /* Reserved area                  */
} car8xx_t;

/* System Integration Timers keys.
*/
typedef struct sitk {
	uint	sitk_tbscrk;
	uint	sitk_tbreff0k;
	uint	sitk_tbreff1k;
	uint	sitk_tbk;
	char	res1[0x10];
	uint	sitk_rtcsck;
	uint	sitk_rtck;
	uint	sitk_rtseck;
	uint	sitk_rtcalk;
	char	res2[0x10];
	uint	sitk_piscrk;
	uint	sitk_pitck;
	char	res3[0x38];
} sitk8xx_t;

/* Clocks and reset keys.
*/
typedef struct cark {
	uint	cark_sccrk;
	uint	cark_plprcrk;
	uint	cark_rsrk;
	char	res[0x474];
} cark8xx_t;

/* The key to unlock registers maintained by keep-alive power.
*/
#define KAPWR_KEY	((unsigned int)0x55ccaa33)

/* Video interface.  MPC823 Only.
*/
typedef struct vid823 {
	ushort	vid_vccr;
	ushort	res1;
	u_char	vid_vsr;
	u_char	res2;
	u_char	vid_vcmr;
	u_char	res3;
	uint	vid_vbcb;
	uint	res4;
	uint	vid_vfcr0;
	uint	vid_vfaa0;
	uint	vid_vfba0;
	uint	vid_vfcr1;
	uint	vid_vfaa1;
	uint	vid_vfba1;
	u_char	res5[0x18];
} vid823_t;

/* LCD interface.  823 Only.
*/
typedef struct lcd {
	uint	lcd_lccr;
	uint	lcd_lchcr;
	uint	lcd_lcvcr;
	char	res1[4];
	uint	lcd_lcfaa;
	uint	lcd_lcfba;
	char	lcd_lcsr;
	char	res2[0x7];
} lcd823_t;

/* I2C
*/
typedef struct i2c {
	u_char	i2c_i2mod;
	char	res1[3];
	u_char	i2c_i2add;
	char	res2[3];
	u_char	i2c_i2brg;
	char	res3[3];
	u_char	i2c_i2com;
	char	res4[3];
	u_char	i2c_i2cer;
	char	res5[3];
	u_char	i2c_i2cmr;
	char	res6[0x8b];
} i2c8xx_t;

/* DMA control/status registers.
*/
typedef struct sdma_csr {
	char	res1[4];
	uint	sdma_sdar;
	u_char	sdma_sdsr;
	char	res3[3];
	u_char	sdma_sdmr;
	char	res4[3];
	u_char	sdma_idsr1;
	char	res5[3];
	u_char	sdma_idmr1;
	char	res6[3];
	u_char	sdma_idsr2;
	char	res7[3];
	u_char	sdma_idmr2;
	char	res8[0x13];
} sdma8xx_t;

/* Communication Processor Module Interrupt Controller.
*/
typedef struct cpm_ic {
	ushort	cpic_civr;
	char	res[0xe];
	uint	cpic_cicr;
	uint	cpic_cipr;
	uint	cpic_cimr;
	uint	cpic_cisr;
} cpic8xx_t;

/* Input/Output Port control/status registers.
*/
typedef struct io_port {
	ushort	iop_padir;
	ushort	iop_papar;
	ushort	iop_paodr;
	ushort	iop_padat;
	char	res1[8];
	ushort	iop_pcdir;
	ushort	iop_pcpar;
	ushort	iop_pcso;
	ushort	iop_pcdat;
	ushort	iop_pcint;
	char	res2[6];
	ushort	iop_pddir;
	ushort	iop_pdpar;
	char	res3[2];
	ushort	iop_pddat;
	uint	utmode;
	char	res4[4];
} iop8xx_t;

/* Communication Processor Module Timers
*/
typedef struct cpm_timers {
	ushort	cpmt_tgcr;
	char	res1[0xe];
	ushort	cpmt_tmr1;
	ushort	cpmt_tmr2;
	ushort	cpmt_trr1;
	ushort	cpmt_trr2;
	ushort	cpmt_tcr1;
	ushort	cpmt_tcr2;
	ushort	cpmt_tcn1;
	ushort	cpmt_tcn2;
	ushort	cpmt_tmr3;
	ushort	cpmt_tmr4;
	ushort	cpmt_trr3;
	ushort	cpmt_trr4;
	ushort	cpmt_tcr3;
	ushort	cpmt_tcr4;
	ushort	cpmt_tcn3;
	ushort	cpmt_tcn4;
	ushort	cpmt_ter1;
	ushort	cpmt_ter2;
	ushort	cpmt_ter3;
	ushort	cpmt_ter4;
	char	res2[8];
} cpmtimer8xx_t;

/* Finally, the Communication Processor stuff.....
*/
typedef struct scc {		/* Serial communication channels */
	uint	scc_gsmrl;
	uint	scc_gsmrh;
	ushort	scc_psmr;
	char	res1[2];
	ushort	scc_todr;
	ushort	scc_dsr;
	ushort	scc_scce;
	char	res2[2];
	ushort	scc_sccm;
	char	res3;
	u_char	scc_sccs;
	char	res4[8];
} scc_t;

typedef struct smc {		/* Serial management channels */
	char	res1[2];
	ushort	smc_smcmr;
	char	res2[2];
	u_char	smc_smce;
	char	res3[3];
	u_char	smc_smcm;
	char	res4[5];
} smc_t;

/* MPC860T Fast Ethernet Controller.  It isn't part of the CPM, but
 * it fits within the address space.
 */

typedef struct fec {
	uint	fec_addr_low;		/* lower 32 bits of station address	*/
	ushort	fec_addr_high;		/* upper 16 bits of station address	*/
	ushort	res1;			/* reserved				*/
	uint	fec_hash_table_high;	/* upper 32-bits of hash table		*/
	uint	fec_hash_table_low;	/* lower 32-bits of hash table		*/
	uint	fec_r_des_start;	/* beginning of Rx descriptor ring	*/
	uint	fec_x_des_start;	/* beginning of Tx descriptor ring	*/
	uint	fec_r_buff_size;	/* Rx buffer size			*/
	uint	res2[9];		/* reserved				*/
	uint	fec_ecntrl;		/* ethernet control register		*/
	uint	fec_ievent;		/* interrupt event register		*/
	uint	fec_imask;		/* interrupt mask register		*/
	uint	fec_ivec;		/* interrupt level and vector status	*/
	uint	fec_r_des_active;	/* Rx ring updated flag			*/
	uint	fec_x_des_active;	/* Tx ring updated flag			*/
	uint	res3[10];		/* reserved				*/
	uint	fec_mii_data;		/* MII data register			*/
	uint	fec_mii_speed;		/* MII speed control register		*/
	uint	res4[17];		/* reserved				*/
	uint	fec_r_bound;		/* end of RAM (read-only)		*/
	uint	fec_r_fstart;		/* Rx FIFO start address		*/
	uint	res5[6];		/* reserved				*/
	uint	fec_x_fstart;		/* Tx FIFO start address		*/
	uint	res6[17];		/* reserved				*/
	uint	fec_fun_code;		/* fec SDMA function code		*/
	uint	res7[3];		/* reserved				*/
	uint	fec_r_cntrl;		/* Rx control register			*/
	uint	fec_r_hash;		/* Rx hash register			*/
	uint	res8[14];		/* reserved				*/
	uint	fec_x_cntrl;		/* Tx control register			*/
	uint	res9[0x1e];		/* reserved				*/
} fec_t;

/* The FEC and LCD color map share the same address space....
 * I guess we will never see an 823T :-).
 */
union fec_lcd {
	fec_t	fl_un_fec;
	u_char	fl_un_cmap[0x200];
};

typedef struct comm_proc {
	/* General control and status registers.
	*/
	ushort	cp_cpcr;
	u_char	res1[2];
	ushort	cp_rccr;
	u_char	res2;
	u_char	cp_rmds;
	u_char	res3[4];
	ushort	cp_cpmcr1;
	ushort	cp_cpmcr2;
	ushort	cp_cpmcr3;
	ushort	cp_cpmcr4;
	u_char	res4[2];
	ushort	cp_rter;
	u_char	res5[2];
	ushort	cp_rtmr;
	u_char	res6[0x14];

	/* Baud rate generators.
	*/
	uint	cp_brgc1;
	uint	cp_brgc2;
	uint	cp_brgc3;
	uint	cp_brgc4;

	/* Serial Communication Channels.
	*/
	scc_t	cp_scc[4];

	/* Serial Management Channels.
	*/
	smc_t	cp_smc[2];

	/* Serial Peripheral Interface.
	*/
	ushort	cp_spmode;
	u_char	res7[4];
	u_char	cp_spie;
	u_char	res8[3];
	u_char	cp_spim;
	u_char	res9[2];
	u_char	cp_spcom;
	u_char	res10[2];

	/* Parallel Interface Port.
	*/
	u_char	res11[2];
	ushort	cp_pipc;
	u_char	res12[2];
	ushort	cp_ptpr;
	uint	cp_pbdir;
	uint	cp_pbpar;
	u_char	res13[2];
	ushort	cp_pbodr;
	uint	cp_pbdat;

	/* Port E - MPC87x/88x only.
	 */
	uint	cp_pedir;
	uint	cp_pepar;
	uint	cp_peso;
	uint	cp_peodr;
	uint	cp_pedat;

	/* Communications Processor Timing Register -
	   Contains RMII Timing for the FECs on MPC87x/88x only.
	*/
	uint	cp_cptr;

	/* Serial Interface and Time Slot Assignment.
	*/
	uint	cp_simode;
	u_char	cp_sigmr;
	u_char	res15;
	u_char	cp_sistr;
	u_char	cp_sicmr;
	u_char	res16[4];
	uint	cp_sicr;
	uint	cp_sirp;
	u_char	res17[0xc];

	/* 256 bytes of MPC823 video controller RAM array.
	*/
	u_char	cp_vcram[0x100];
	u_char	cp_siram[0x200];

	/* The fast ethernet controller is not really part of the CPM,
	 * but it resides in the address space.
	 * The LCD color map is also here.
	 */
	union	fec_lcd	fl_un;
#define cp_fec		fl_un.fl_un_fec
#define lcd_cmap	fl_un.fl_un_cmap
	char	res18[0xE00];

	/* The MPC885 family has a second FEC here */
	fec_t	cp_fec2;
#define cp_fec1	cp_fec	/* consistency macro */

	/* Dual Ported RAM follows.
	 * There are many different formats for this memory area
	 * depending upon the devices used and options chosen.
	 * Some processors don't have all of it populated.
	 */
	u_char	cp_dpmem[0x1C00];	/* BD / Data / ucode */
	u_char	cp_dparam[0x400];	/* Parameter RAM */
} cpm8xx_t;

/* Internal memory map.
*/
typedef struct immap {
	sysconf8xx_t	im_siu_conf;	/* SIU Configuration */
	pcmconf8xx_t	im_pcmcia;	/* PCMCIA Configuration */
	memctl8xx_t	im_memctl;	/* Memory Controller */
	sit8xx_t	im_sit;		/* System integration timers */
	car8xx_t	im_clkrst;	/* Clocks and reset */
	sitk8xx_t	im_sitk;	/* Sys int timer keys */
	cark8xx_t	im_clkrstk;	/* Clocks and reset keys */
	vid823_t	im_vid;		/* Video (823 only) */
	lcd823_t	im_lcd;		/* LCD (823 only) */
	i2c8xx_t	im_i2c;		/* I2C control/status */
	sdma8xx_t	im_sdma;	/* SDMA control/status */
	cpic8xx_t	im_cpic;	/* CPM Interrupt Controller */
	iop8xx_t	im_ioport;	/* IO Port control/status */
	cpmtimer8xx_t	im_cpmtimer;	/* CPM timers */
	cpm8xx_t	im_cpm;		/* Communication processor */
} immap_t;

#endif /* __IMMAP_8XX__ */
Commit	Line	Data
5745185e WD	1
	2	/*
	3	* MPC8xx Internal Memory Map
	4	* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
	5	*
	6	* The I/O on the MPC860 is comprised of blocks of special registers
	7	* and the dual port ram for the Communication Processor Module.
	8	* Within this space are functional units such as the SIU, memory
	9	* controller, system timers, and other control functions. It is
	10	* a combination that I found difficult to separate into logical
	11	* functional files.....but anyone else is welcome to try. -- Dan
	12	*/
	13	#ifndef __IMMAP_8XX__
	14	#define __IMMAP_8XX__
	15
	16	/* System configuration registers.
	17	*/
	18	typedef struct sys_conf {
	19	uint sc_siumcr;
	20	uint sc_sypcr;
	21	uint sc_swt;
	22	char res1[2];
	23	ushort sc_swsr;
	24	uint sc_sipend;
	25	uint sc_simask;
	26	uint sc_siel;
	27	uint sc_sivec;
	28	uint sc_tesr;
	29	char res2[0xc];
	30	uint sc_sdcr;
	31	char res3[0x4c];
	32	} sysconf8xx_t;
	33
	34	/* PCMCIA configuration registers.
	35	*/
	36	typedef struct pcmcia_conf {
	37	uint pcmc_pbr0;
	38	uint pcmc_por0;
	39	uint pcmc_pbr1;
	40	uint pcmc_por1;
	41	uint pcmc_pbr2;
	42	uint pcmc_por2;
	43	uint pcmc_pbr3;
	44	uint pcmc_por3;
	45	uint pcmc_pbr4;
	46	uint pcmc_por4;
	47	uint pcmc_pbr5;
	48	uint pcmc_por5;
	49	uint pcmc_pbr6;
	50	uint pcmc_por6;
	51	uint pcmc_pbr7;
	52	uint pcmc_por7;
	53	char res1[0x20];
	54	uint pcmc_pgcra;
	55	uint pcmc_pgcrb;
	56	uint pcmc_pscr;
	57	char res2[4];
	58	uint pcmc_pipr;
	59	char res3[4];
	60	uint pcmc_per;
	61	char res4[4];
	62	} pcmconf8xx_t;
	63
	64	/* Memory controller registers.
65	*/
66	typedef struct mem_ctlr {
67	uint memc_br0;
68	uint memc_or0;
69	uint memc_br1;
70	uint memc_or1;
71	uint memc_br2;
72	uint memc_or2;
73	uint memc_br3;
74	uint memc_or3;
75	uint memc_br4;
76	uint memc_or4;
77	uint memc_br5;
78	uint memc_or5;
79	uint memc_br6;
80	uint memc_or6;
81	uint memc_br7;
82	uint memc_or7;
83	char res1[0x24];
84	uint memc_mar;
85	uint memc_mcr;
86	char res2[4];
87	uint memc_mamr;
88	uint memc_mbmr;
89	ushort memc_mstat;
90	ushort memc_mptpr;
91	uint memc_mdr;
92	char res3[0x80];
93	} memctl8xx_t;
94
95	/* System Integration Timers.
96	*/
97	typedef struct sys_int_timers {
98	ushort sit_tbscr;
99	char res0[0x02];
100	uint sit_tbreff0;
101	uint sit_tbreff1;
102	char res1[0x14];
103	ushort sit_rtcsc;
104	char res2[0x02];
105	uint sit_rtc;
106	uint sit_rtsec;
107	uint sit_rtcal;
108	char res3[0x10];
109	ushort sit_piscr;
110	char res4[2];
111	uint sit_pitc;
112	uint sit_pitr;
113	char res5[0x34];
114	} sit8xx_t;
115
116	#define TBSCR_TBIRQ_MASK ((ushort)0xff00)
117	#define TBSCR_REFA ((ushort)0x0080)
118	#define TBSCR_REFB ((ushort)0x0040)
119	#define TBSCR_REFAE ((ushort)0x0008)
120	#define TBSCR_REFBE ((ushort)0x0004)
121	#define TBSCR_TBF ((ushort)0x0002)
122	#define TBSCR_TBE ((ushort)0x0001)
123
124	#define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
125	#define RTCSC_SEC ((ushort)0x0080)
126	#define RTCSC_ALR ((ushort)0x0040)
127	#define RTCSC_38K ((ushort)0x0010)
128	#define RTCSC_SIE ((ushort)0x0008)
129	#define RTCSC_ALE ((ushort)0x0004)
130	#define RTCSC_RTF ((ushort)0x0002)
131	#define RTCSC_RTE ((ushort)0x0001)
132
133	#define PISCR_PIRQ_MASK ((ushort)0xff00)
134	#define PISCR_PS ((ushort)0x0080)
135	#define PISCR_PIE ((ushort)0x0004)
136	#define PISCR_PTF ((ushort)0x0002)
137	#define PISCR_PTE ((ushort)0x0001)
138
139	/* Clocks and Reset.
140	*/
141	typedef struct clk_and_reset {
142	uint car_sccr;
143	uint car_plprcr;
144	uint car_rsr;
145	char res[0x74]; /* Reserved area */
146	} car8xx_t;
147
148	/* System Integration Timers keys.
149	*/
150	typedef struct sitk {
151	uint sitk_tbscrk;
152	uint sitk_tbreff0k;
153	uint sitk_tbreff1k;
154	uint sitk_tbk;
155	char res1[0x10];
156	uint sitk_rtcsck;
157	uint sitk_rtck;
158	uint sitk_rtseck;
159	uint sitk_rtcalk;
160	char res2[0x10];
161	uint sitk_piscrk;
162	uint sitk_pitck;
163	char res3[0x38];
164	} sitk8xx_t;
165
166	/* Clocks and reset keys.
167	*/
168	typedef struct cark {
169	uint cark_sccrk;
170	uint cark_plprcrk;
171	uint cark_rsrk;
172	char res[0x474];
173	} cark8xx_t;
174
175	/* The key to unlock registers maintained by keep-alive power.
176	*/
177	#define KAPWR_KEY ((unsigned int)0x55ccaa33)
178
179	/* Video interface. MPC823 Only.
180	*/
181	typedef struct vid823 {
182	ushort vid_vccr;
183	ushort res1;
184	u_char vid_vsr;
185	u_char res2;
186	u_char vid_vcmr;
187	u_char res3;
188	uint vid_vbcb;
189	uint res4;
190	uint vid_vfcr0;
191	uint vid_vfaa0;
192	uint vid_vfba0;
193	uint vid_vfcr1;
194	uint vid_vfaa1;
195	uint vid_vfba1;
196	u_char res5[0x18];
197	} vid823_t;
198
199	/* LCD interface. 823 Only.
200	*/
201	typedef struct lcd {
202	uint lcd_lccr;
203	uint lcd_lchcr;
204	uint lcd_lcvcr;
205	char res1[4];
206	uint lcd_lcfaa;
207	uint lcd_lcfba;
208	char lcd_lcsr;
209	char res2[0x7];
210	} lcd823_t;
211
212	/* I2C
213	*/
214	typedef struct i2c {
215	u_char i2c_i2mod;
216	char res1[3];
217	u_char i2c_i2add;
218	char res2[3];
219	u_char i2c_i2brg;
220	char res3[3];
221	u_char i2c_i2com;
222	char res4[3];
223	u_char i2c_i2cer;
224	char res5[3];
225	u_char i2c_i2cmr;
226	char res6[0x8b];
227	} i2c8xx_t;
228
229	/* DMA control/status registers.
230	*/
231	typedef struct sdma_csr {
232	char res1[4];
233	uint sdma_sdar;
234	u_char sdma_sdsr;
235	char res3[3];
236	u_char sdma_sdmr;
237	char res4[3];
238	u_char sdma_idsr1;
239	char res5[3];
240	u_char sdma_idmr1;
241	char res6[3];
242	u_char sdma_idsr2;
243	char res7[3];
244	u_char sdma_idmr2;
245	char res8[0x13];
246	} sdma8xx_t;
247
248	/* Communication Processor Module Interrupt Controller.
249	*/
250	typedef struct cpm_ic {
251	ushort cpic_civr;
252	char res[0xe];
253	uint cpic_cicr;
254	uint cpic_cipr;
255	uint cpic_cimr;
256	uint cpic_cisr;
257	} cpic8xx_t;
258
259	/* Input/Output Port control/status registers.
260	*/
261	typedef struct io_port {
262	ushort iop_padir;
263	ushort iop_papar;
264	ushort iop_paodr;
265	ushort iop_padat;
266	char res1[8];
267	ushort iop_pcdir;
268	ushort iop_pcpar;
269	ushort iop_pcso;
270	ushort iop_pcdat;
271	ushort iop_pcint;
272	char res2[6];
273	ushort iop_pddir;
274	ushort iop_pdpar;
275	char res3[2];
276	ushort iop_pddat;
277	uint utmode;
278	char res4[4];
279	} iop8xx_t;
280
281	/* Communication Processor Module Timers
282	*/
283	typedef struct cpm_timers {
284	ushort cpmt_tgcr;
285	char res1[0xe];
286	ushort cpmt_tmr1;
287	ushort cpmt_tmr2;
288	ushort cpmt_trr1;
289	ushort cpmt_trr2;
290	ushort cpmt_tcr1;
291	ushort cpmt_tcr2;
292	ushort cpmt_tcn1;
293	ushort cpmt_tcn2;
294	ushort cpmt_tmr3;
295	ushort cpmt_tmr4;
296	ushort cpmt_trr3;
297	ushort cpmt_trr4;
298	ushort cpmt_tcr3;
299	ushort cpmt_tcr4;
300	ushort cpmt_tcn3;
301	ushort cpmt_tcn4;
302	ushort cpmt_ter1;
303	ushort cpmt_ter2;
304	ushort cpmt_ter3;
305	ushort cpmt_ter4;
306	char res2[8];
307	} cpmtimer8xx_t;
308
309	/* Finally, the Communication Processor stuff.....
310	*/
311	typedef struct scc { /* Serial communication channels */
312	uint scc_gsmrl;
313	uint scc_gsmrh;
314	ushort scc_psmr;
315	char res1[2];
316	ushort scc_todr;
317	ushort scc_dsr;
318	ushort scc_scce;
319	char res2[2];
320	ushort scc_sccm;
321	char res3;
322	u_char scc_sccs;
323	char res4[8];
324	} scc_t;
325
326	typedef struct smc { /* Serial management channels */
327	char res1[2];
328	ushort smc_smcmr;
329	char res2[2];
330	u_char smc_smce;
331	char res3[3];
332	u_char smc_smcm;
333	char res4[5];
334	} smc_t;
335
336	/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
337	* it fits within the address space.
338	*/
339
340	typedef struct fec {
341	uint fec_addr_low; /* lower 32 bits of station address */
342	ushort fec_addr_high; /* upper 16 bits of station address */
343	ushort res1; /* reserved */
344	uint fec_hash_table_high; /* upper 32-bits of hash table */
345	uint fec_hash_table_low; /* lower 32-bits of hash table */
346	uint fec_r_des_start; /* beginning of Rx descriptor ring */
347	uint fec_x_des_start; /* beginning of Tx descriptor ring */
348	uint fec_r_buff_size; /* Rx buffer size */
349	uint res2[9]; /* reserved */
350	uint fec_ecntrl; /* ethernet control register */
351	uint fec_ievent; /* interrupt event register */
352	uint fec_imask; /* interrupt mask register */
353	uint fec_ivec; /* interrupt level and vector status */
354	uint fec_r_des_active; /* Rx ring updated flag */
355	uint fec_x_des_active; /* Tx ring updated flag */
356	uint res3[10]; /* reserved */
357	uint fec_mii_data; /* MII data register */
358	uint fec_mii_speed; /* MII speed control register */
359	uint res4[17]; /* reserved */
360	uint fec_r_bound; /* end of RAM (read-only) */
361	uint fec_r_fstart; /* Rx FIFO start address */
362	uint res5[6]; /* reserved */
363	uint fec_x_fstart; /* Tx FIFO start address */
364	uint res6[17]; /* reserved */
365	uint fec_fun_code; /* fec SDMA function code */
366	uint res7[3]; /* reserved */
367	uint fec_r_cntrl; /* Rx control register */
368	uint fec_r_hash; /* Rx hash register */
369	uint res8[14]; /* reserved */
370	uint fec_x_cntrl; /* Tx control register */
371	uint res9[0x1e]; /* reserved */
372	} fec_t;
373
374	/* The FEC and LCD color map share the same address space....
375	* I guess we will never see an 823T :-).
376	*/
377	union fec_lcd {
378	fec_t fl_un_fec;
379	u_char fl_un_cmap[0x200];
380	};
381
382	typedef struct comm_proc {
383	/* General control and status registers.
384	*/
385	ushort cp_cpcr;
386	u_char res1[2];
387	ushort cp_rccr;
388	u_char res2;
389	u_char cp_rmds;
390	u_char res3[4];
391	ushort cp_cpmcr1;
392	ushort cp_cpmcr2;
393	ushort cp_cpmcr3;
394	ushort cp_cpmcr4;
395	u_char res4[2];
396	ushort cp_rter;
397	u_char res5[2];
398	ushort cp_rtmr;
399	u_char res6[0x14];
400
401	/* Baud rate generators.
402	*/
403	uint cp_brgc1;
404	uint cp_brgc2;
405	uint cp_brgc3;
406	uint cp_brgc4;
407
408	/* Serial Communication Channels.
409	*/
410	scc_t cp_scc[4];
411
412	/* Serial Management Channels.
413	*/
414	smc_t cp_smc[2];
415
416	/* Serial Peripheral Interface.
417	*/
418	ushort cp_spmode;
419	u_char res7[4];
420	u_char cp_spie;
421	u_char res8[3];
422	u_char cp_spim;
423	u_char res9[2];
424	u_char cp_spcom;
425	u_char res10[2];
426
427	/* Parallel Interface Port.
428	*/
429	u_char res11[2];
430	ushort cp_pipc;
431	u_char res12[2];
432	ushort cp_ptpr;
433	uint cp_pbdir;
434	uint cp_pbpar;
435	u_char res13[2];
436	ushort cp_pbodr;
437	uint cp_pbdat;
180d3f74 WD	438
	439	/* Port E - MPC87x/88x only.
	440	*/
	441	uint cp_pedir;
	442	uint cp_pepar;
	443	uint cp_peso;
	444	uint cp_peodr;
	445	uint cp_pedat;
	446
	447	/* Communications Processor Timing Register -
	448	Contains RMII Timing for the FECs on MPC87x/88x only.
	449	*/
	450	uint cp_cptr;
5745185e WD	451
	452	/* Serial Interface and Time Slot Assignment.
	453	*/
	454	uint cp_simode;
	455	u_char cp_sigmr;
	456	u_char res15;
	457	u_char cp_sistr;
	458	u_char cp_sicmr;
	459	u_char res16[4];
	460	uint cp_sicr;
	461	uint cp_sirp;
	462	u_char res17[0xc];
	463
	464	/* 256 bytes of MPC823 video controller RAM array.
	465	*/
	466	u_char cp_vcram[0x100];
	467	u_char cp_siram[0x200];
	468
	469	/* The fast ethernet controller is not really part of the CPM,
	470	* but it resides in the address space.
	471	* The LCD color map is also here.
	472	*/
	473	union fec_lcd fl_un;
	474	#define cp_fec fl_un.fl_un_fec
	475	#define lcd_cmap fl_un.fl_un_cmap
a6ab4bf9 WD	476	char res18[0xE00];
a6ab4bf9 WD	477
1114257c	478	/* The MPC885 family has a second FEC here */
a6ab4bf9 WD	479	fec_t cp_fec2;
a6ab4bf9 WD	480	#define cp_fec1 cp_fec /* consistency macro */
5745185e WD	481
	482	/* Dual Ported RAM follows.
	483	* There are many different formats for this memory area
	484	* depending upon the devices used and options chosen.
	485	* Some processors don't have all of it populated.
	486	*/
	487	u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
	488	u_char cp_dparam[0x400]; /* Parameter RAM */
	489	} cpm8xx_t;
	490
	491	/* Internal memory map.
	492	*/
	493	typedef struct immap {
	494	sysconf8xx_t im_siu_conf; /* SIU Configuration */
	495	pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
	496	memctl8xx_t im_memctl; /* Memory Controller */
	497	sit8xx_t im_sit; /* System integration timers */
	498	car8xx_t im_clkrst; /* Clocks and reset */
	499	sitk8xx_t im_sitk; /* Sys int timer keys */
	500	cark8xx_t im_clkrstk; /* Clocks and reset keys */
	501	vid823_t im_vid; /* Video (823 only) */
	502	lcd823_t im_lcd; /* LCD (823 only) */
	503	i2c8xx_t im_i2c; /* I2C control/status */
	504	sdma8xx_t im_sdma; /* SDMA control/status */
	505	cpic8xx_t im_cpic; /* CPM Interrupt Controller */
	506	iop8xx_t im_ioport; /* IO Port control/status */
	507	cpmtimer8xx_t im_cpmtimer; /* CPM timers */
	508	cpm8xx_t im_cpm; /* Communication processor */
	509	} immap_t;
	510
	511	#endif /* __IMMAP_8XX__ */