projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 416fef1a WD |
1 | /* |
| 2 | * include/asm-ppc/cache.h | |
| 3 | */ | |
| 4 | #ifndef __ARCH_PPC_CACHE_H | |
| 5 | #define __ARCH_PPC_CACHE_H | |
| 6 | ||
| 416fef1a WD |
7 | #include <asm/processor.h> |
| 8 | ||
| 9 | /* bytes per L1 cache line */ | |
| 5b8e76c3 | 10 | #if defined(CONFIG_PPC64BRIDGE) |
| 9b94ac61 | 11 | #define L1_CACHE_SHIFT 7 |
| 0f060c3b KG |
12 | #elif defined(CONFIG_E500MC) |
| 13 | #define L1_CACHE_SHIFT 6 | |
| 416fef1a | 14 | #else |
| 9b94ac61 | 15 | #define L1_CACHE_SHIFT 5 |
| b009f3ec | 16 | #endif |
| 9b94ac61 SR |
17 | |
| 18 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | |
| 19 | ||
| 0991701a AS |
20 | /* |
| 21 | * Use the L1 data cache line size value for the minimum DMA buffer alignment | |
| 22 | * on PowerPC. | |
| 23 | */ | |
| 24 | #define ARCH_DMA_MINALIGN L1_CACHE_BYTES | |
| 25 | ||
| 9b94ac61 | 26 | /* |
| 6d0f6bcf | 27 | * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too |
| 9b94ac61 | 28 | */ |
| 6d0f6bcf JCPV |
29 | #ifndef CONFIG_SYS_CACHELINE_SIZE |
| 30 | #define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES | |
| 9b94ac61 | 31 | #endif |
| 416fef1a WD |
32 | |
| 33 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) | |
| 34 | #define L1_CACHE_PAGES 8 | |
| 35 | ||
| 36 | #define SMP_CACHE_BYTES L1_CACHE_BYTES | |
| 37 | ||
| 38 | #ifdef MODULE | |
| 39 | #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) | |
| 40 | #else | |
| 41 | #define __cacheline_aligned \ | |
| 42 | __attribute__((__aligned__(L1_CACHE_BYTES), \ | |
| 43 | __section__(".data.cacheline_aligned"))) | |
| 44 | #endif | |
| 45 | ||
| 46 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) | |
| 47 | extern void flush_dcache_range(unsigned long start, unsigned long stop); | |
| 48 | extern void clean_dcache_range(unsigned long start, unsigned long stop); | |
| 49 | extern void invalidate_dcache_range(unsigned long start, unsigned long stop); | |
| 9b94ac61 SR |
50 | extern void flush_dcache(void); |
| 51 | extern void invalidate_dcache(void); | |
| 54e091d3 | 52 | extern void invalidate_icache(void); |
| 6d0f6bcf | 53 | #ifdef CONFIG_SYS_INIT_RAM_LOCK |
| 416fef1a | 54 | extern void unlock_ram_in_cache(void); |
| 6d0f6bcf | 55 | #endif /* CONFIG_SYS_INIT_RAM_LOCK */ |
| 416fef1a WD |
56 | #endif /* __ASSEMBLY__ */ |
| 57 | ||
| 7cb72723 TY |
58 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
| 59 | int l2cache_init(void); | |
| 60 | void enable_cpc(void); | |
| 61 | void disable_cpc_sram(void); | |
| 62 | #endif | |
| 63 | ||
| 416fef1a WD |
64 | /* prep registers for L2 */ |
| 65 | #define CACHECRBA 0x80000823 /* Cache configuration register address */ | |
| 66 | #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ | |
| 67 | #define L2CACHE_512KB 0x00 /* 512KB */ | |
| 68 | #define L2CACHE_256KB 0x01 /* 256KB */ | |
| 69 | #define L2CACHE_1MB 0x02 /* 1MB */ | |
| 70 | #define L2CACHE_NONE 0x03 /* NONE */ | |
| 71 | #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ | |
| 72 | ||
| 416fef1a | 73 | #endif |