projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 47d41cc3 | 1 | /* |
| b8cdd014 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
| 47d41cc3 | 3 | * |
| 1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 47d41cc3 KG |
5 | */ |
| 6 | ||
| 7 | #ifndef _ASM_CONFIG_H_ | |
| 8 | #define _ASM_CONFIG_H_ | |
| 9 | ||
| 243be8e2 KG |
10 | #ifdef CONFIG_MPC85xx |
| 11 | #include <asm/config_mpc85xx.h> | |
| 12 | #endif | |
| 13 | ||
| 14 | #ifdef CONFIG_MPC86xx | |
| 15 | #include <asm/config_mpc86xx.h> | |
| 5614e71b YS |
16 | #endif |
| 17 | ||
| 18 | #ifdef CONFIG_MPC83xx | |
| 243be8e2 KG |
19 | #endif |
| 20 | ||
| 7ac3cc20 YS |
21 | #ifndef HWCONFIG_BUFFER_SIZE |
| 22 | #define HWCONFIG_BUFFER_SIZE 256 | |
| 23 | #endif | |
| 24 | ||
| 273feafe MH |
25 | /* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ |
| 26 | #if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) | |
| 27 | # ifndef CONFIG_HARD_SPI | |
| 28 | # define CONFIG_HARD_SPI | |
| 29 | # endif | |
| 30 | #endif | |
| 31 | ||
| a16028da | 32 | #define CONFIG_LMB |
| fca43cc8 | 33 | #define CONFIG_SYS_BOOT_RAMDISK_HIGH |
| a16028da | 34 | |
| 87c90639 | 35 | #ifndef CONFIG_MAX_MEM_MAPPED |
| 98f705c9 | 36 | #if defined(CONFIG_E500) || \ |
| d29d17d7 YS |
37 | defined(CONFIG_MPC86xx) || \ |
| 38 | defined(CONFIG_E300) | |
| 87c90639 KG |
39 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) |
| 40 | #else | |
| 2ede879f | 41 | #define CONFIG_MAX_MEM_MAPPED (256 << 20) |
| 87c90639 KG |
42 | #endif |
| 43 | #endif | |
| 44 | ||
| f732a759 PT |
45 | /* Check if boards need to enable FSL DMA engine for SDRAM init */ |
| 46 | #if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC) | |
| 47 | #if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \ | |
| 48 | ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \ | |
| 49 | !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) | |
| 017f11f6 | 50 | #define CONFIG_FSL_DMA |
| 47d41cc3 | 51 | #endif |
| 017f11f6 PT |
52 | #endif |
| 53 | ||
| 5ccd29c3 PT |
54 | /* |
| 55 | * Provide a default boot page translation virtual address that lines up with | |
| 56 | * Freescale's default e500 reset page. | |
| 57 | */ | |
| 58 | #if (defined(CONFIG_E500) && defined(CONFIG_MP)) | |
| 59 | #ifndef CONFIG_BPTR_VIRT_ADDR | |
| 60 | #define CONFIG_BPTR_VIRT_ADDR 0xfffff000 | |
| 61 | #endif | |
| 62 | #endif | |
| 63 | ||
| f51cdaf1 BB |
64 | /* Since so many PPC SOCs have a semi-common LBC, define this here */ |
| 65 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ | |
| 66 | defined(CONFIG_MPC83xx) | |
| d789b5f5 | 67 | #if !defined(CONFIG_FSL_IFC) |
| f51cdaf1 BB |
68 | #define CONFIG_FSL_LBC |
| 69 | #endif | |
| d789b5f5 | 70 | #endif |
| f51cdaf1 | 71 | |
| 063c1263 | 72 | /* The TSEC driver uses the PHYLIB infrastructure */ |
| 990d06b0 | 73 | #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB) |
| 063c1263 AF |
74 | #include <config_phylib_all_drivers.h> |
| 75 | #endif /* TSEC_ENET */ | |
| 063c1263 | 76 | |
| c916d7c9 | 77 | /* The FMAN driver uses the PHYLIB infrastructure */ |
| c916d7c9 | 78 | |
| f2a37fcd AA |
79 | /* All PPC boards must swap IDE bytes */ |
| 80 | #define CONFIG_IDE_SWAP_IO | |
| 81 | ||
| f27445cb TC |
82 | #if defined(CONFIG_DM_SERIAL) |
| 83 | /* | |
| 84 | * TODO: Convert this to a clock driver exists that can give us the UART | |
| 85 | * clock here. | |
| 86 | */ | |
| 87 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() | |
| 88 | #endif | |
| 89 | ||
| 017f11f6 | 90 | #endif /* _ASM_CONFIG_H_ */ |